Add support for Cortex-A76/Neoverse-N1 to hwpmc
This adds support for the Cortex-A76 and Neoverse-N1 PMU counters to pmc. While here add more PMCR_IDCODE values and check the implementers code is correct before setting the PMU type. Reviewed by: bz, emaste (looks reasonable to me) Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D25959
This commit is contained in:
parent
d9fe3aed75
commit
da11e1f9ee
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=364153
@ -176,6 +176,11 @@ static const struct pmc_event_descr cortex_a57_event_table[] =
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__PMC_EV_ALIAS_ARMV8_CORTEX_A57()
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__PMC_EV_ALIAS_ARMV8_CORTEX_A57()
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};
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};
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static const struct pmc_event_descr cortex_a76_event_table[] =
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{
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__PMC_EV_ALIAS_ARMV8_CORTEX_A76()
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};
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/*
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/*
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* PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
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* PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
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*
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*
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@ -193,6 +198,7 @@ PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
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PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
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PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
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PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);
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PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);
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PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);
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PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);
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PMC_MDEP_TABLE(cortex_a76, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);
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PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
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PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
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PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K);
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PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K);
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PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON);
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PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON);
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@ -235,6 +241,7 @@ PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
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#if defined(__aarch64__)
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#if defined(__aarch64__)
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PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
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PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
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PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
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PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
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PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64);
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#endif
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#endif
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#if defined(__mips__)
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#if defined(__mips__)
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PMC_CLASS_TABLE_DESC(beri, BERI, beri, mips);
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PMC_CLASS_TABLE_DESC(beri, BERI, beri, mips);
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@ -817,6 +824,9 @@ static struct pmc_event_alias cortex_a53_aliases[] = {
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static struct pmc_event_alias cortex_a57_aliases[] = {
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static struct pmc_event_alias cortex_a57_aliases[] = {
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EV_ALIAS(NULL, NULL)
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EV_ALIAS(NULL, NULL)
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};
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};
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static struct pmc_event_alias cortex_a76_aliases[] = {
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EV_ALIAS(NULL, NULL)
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};
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static int
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static int
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arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
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arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
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struct pmc_op_pmcallocate *pmc_config __unused)
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struct pmc_op_pmcallocate *pmc_config __unused)
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@ -1273,6 +1283,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
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ev = cortex_a57_event_table;
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ev = cortex_a57_event_table;
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count = PMC_EVENT_TABLE_SIZE(cortex_a57);
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count = PMC_EVENT_TABLE_SIZE(cortex_a57);
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break;
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break;
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case PMC_CPU_ARMV8_CORTEX_A76:
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ev = cortex_a76_event_table;
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count = PMC_EVENT_TABLE_SIZE(cortex_a76);
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break;
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}
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}
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break;
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break;
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case PMC_CLASS_BERI:
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case PMC_CLASS_BERI:
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@ -1518,6 +1532,10 @@ pmc_init(void)
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PMC_MDEP_INIT(cortex_a57);
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PMC_MDEP_INIT(cortex_a57);
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pmc_class_table[n] = &cortex_a57_class_table_descr;
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pmc_class_table[n] = &cortex_a57_class_table_descr;
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break;
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break;
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case PMC_CPU_ARMV8_CORTEX_A76:
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PMC_MDEP_INIT(cortex_a76);
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pmc_class_table[n] = &cortex_a76_class_table_descr;
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break;
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#endif
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#endif
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#if defined(__mips__)
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#if defined(__mips__)
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case PMC_CPU_MIPS_BERI:
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case PMC_CPU_MIPS_BERI:
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@ -1658,6 +1676,10 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
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ev = cortex_a57_event_table;
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ev = cortex_a57_event_table;
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evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57);
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evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57);
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break;
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break;
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case PMC_CPU_ARMV8_CORTEX_A76:
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ev = cortex_a76_event_table;
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evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76);
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break;
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default: /* Unknown CPU type. */
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default: /* Unknown CPU type. */
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break;
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break;
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}
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}
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@ -857,11 +857,20 @@
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#define PMCR_LC (1 << 6) /* Long cycle count enable */
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#define PMCR_LC (1 << 6) /* Long cycle count enable */
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#define PMCR_IMP_SHIFT 24 /* Implementer code */
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#define PMCR_IMP_SHIFT 24 /* Implementer code */
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#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
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#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
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#define PMCR_IMP_ARM 0x41
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#define PMCR_IDCODE_SHIFT 16 /* Identification code */
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#define PMCR_IDCODE_SHIFT 16 /* Identification code */
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#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
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#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
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#define PMCR_IDCODE_CORTEX_A57 0x01
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#define PMCR_IDCODE_CORTEX_A57 0x01
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#define PMCR_IDCODE_CORTEX_A72 0x02
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#define PMCR_IDCODE_CORTEX_A72 0x02
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#define PMCR_IDCODE_CORTEX_A53 0x03
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#define PMCR_IDCODE_CORTEX_A53 0x03
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#define PMCR_IDCODE_CORTEX_A73 0x04
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#define PMCR_IDCODE_CORTEX_A35 0x0a
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#define PMCR_IDCODE_CORTEX_A76 0x0b
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#define PMCR_IDCODE_NEOVERSE_N1 0x0c
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#define PMCR_IDCODE_CORTEX_A77 0x10
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#define PMCR_IDCODE_CORTEX_A55 0x45
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#define PMCR_IDCODE_NEOVERSE_E1 0x46
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#define PMCR_IDCODE_CORTEX_A75 0x4a
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#define PMCR_N_SHIFT 11 /* Number of counters implemented */
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#define PMCR_N_SHIFT 11 /* Number of counters implemented */
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#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
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#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
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@ -479,11 +479,12 @@ pmc_arm64_initialize()
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{
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{
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struct pmc_mdep *pmc_mdep;
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struct pmc_mdep *pmc_mdep;
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struct pmc_classdep *pcd;
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struct pmc_classdep *pcd;
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int idcode;
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int idcode, impcode;
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int reg;
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int reg;
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reg = arm64_pmcr_read();
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reg = arm64_pmcr_read();
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arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
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arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
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impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT;
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idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT;
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idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT;
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PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
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PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
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@ -498,13 +499,24 @@ pmc_arm64_initialize()
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/* Just one class */
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/* Just one class */
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pmc_mdep = pmc_mdep_alloc(1);
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pmc_mdep = pmc_mdep_alloc(1);
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switch (idcode) {
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switch(impcode) {
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case PMCR_IDCODE_CORTEX_A57:
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case PMCR_IMP_ARM:
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case PMCR_IDCODE_CORTEX_A72:
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switch (idcode) {
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57;
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case PMCR_IDCODE_CORTEX_A76:
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case PMCR_IDCODE_NEOVERSE_N1:
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76;
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break;
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case PMCR_IDCODE_CORTEX_A57:
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case PMCR_IDCODE_CORTEX_A72:
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57;
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break;
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default:
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case PMCR_IDCODE_CORTEX_A53:
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
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break;
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}
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break;
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break;
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default:
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default:
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case PMCR_IDCODE_CORTEX_A53:
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
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break;
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break;
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}
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}
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@ -955,7 +955,7 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
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__PMC_EV_ALIAS("BR_RETURN_RETIRED", ARMV8_EVENT_0EH) \
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__PMC_EV_ALIAS("BR_RETURN_RETIRED", ARMV8_EVENT_0EH) \
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__PMC_EV_ALIAS("UNALIGNED_LDST_RETIRED",ARMV8_EVENT_0FH)
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__PMC_EV_ALIAS("UNALIGNED_LDST_RETIRED",ARMV8_EVENT_0FH)
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#define __PMC_EV_ALIAS_ARMV8_CORTEX_A57() \
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#define __PMC_EV_ALIAS_ARMV8_CORTEX_A57_A76() \
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__PMC_EV_ALIAS_ARMV8_COMMON() \
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__PMC_EV_ALIAS_ARMV8_COMMON() \
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__PMC_EV_ALIAS("INST_SPEC", ARMV8_EVENT_1BH) \
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__PMC_EV_ALIAS("INST_SPEC", ARMV8_EVENT_1BH) \
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__PMC_EV_ALIAS("TTBR_WRITE_RETIRED", ARMV8_EVENT_1CH) \
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__PMC_EV_ALIAS("TTBR_WRITE_RETIRED", ARMV8_EVENT_1CH) \
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@ -975,10 +975,6 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
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__PMC_EV_ALIAS("L2D_CACHE_WB_VICTIM", ARMV8_EVENT_56H) \
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__PMC_EV_ALIAS("L2D_CACHE_WB_VICTIM", ARMV8_EVENT_56H) \
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__PMC_EV_ALIAS("L2D_CACHE_WB_CLEAN", ARMV8_EVENT_57H) \
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__PMC_EV_ALIAS("L2D_CACHE_WB_CLEAN", ARMV8_EVENT_57H) \
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__PMC_EV_ALIAS("L2D_CACHE_INVAL", ARMV8_EVENT_58H) \
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__PMC_EV_ALIAS("L2D_CACHE_INVAL", ARMV8_EVENT_58H) \
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__PMC_EV_ALIAS("BUS_ACCESS_SHARED", ARMV8_EVENT_62H) \
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__PMC_EV_ALIAS("BUS_ACCESS_NOT_SHARED", ARMV8_EVENT_63H) \
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__PMC_EV_ALIAS("BUS_ACCESS_NORMAL", ARMV8_EVENT_64H) \
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__PMC_EV_ALIAS("BUS_ACCESS_PERIPH", ARMV8_EVENT_65H) \
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__PMC_EV_ALIAS("MEM_ACCESS_LD", ARMV8_EVENT_66H) \
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__PMC_EV_ALIAS("MEM_ACCESS_LD", ARMV8_EVENT_66H) \
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__PMC_EV_ALIAS("MEM_ACCESS_ST", ARMV8_EVENT_67H) \
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__PMC_EV_ALIAS("MEM_ACCESS_ST", ARMV8_EVENT_67H) \
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__PMC_EV_ALIAS("UNALIGNED_LD_SPEC", ARMV8_EVENT_68H) \
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__PMC_EV_ALIAS("UNALIGNED_LD_SPEC", ARMV8_EVENT_68H) \
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@ -1014,6 +1010,43 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
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__PMC_EV_ALIAS("RC_LD_SPEC", ARMV8_EVENT_90H) \
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__PMC_EV_ALIAS("RC_LD_SPEC", ARMV8_EVENT_90H) \
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__PMC_EV_ALIAS("RC_ST_SPEC", ARMV8_EVENT_91H)
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__PMC_EV_ALIAS("RC_ST_SPEC", ARMV8_EVENT_91H)
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#define __PMC_EV_ALIAS_ARMV8_CORTEX_A57() \
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__PMC_EV_ALIAS_ARMV8_CORTEX_A57_A76() \
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__PMC_EV_ALIAS("BUS_ACCESS_SHARED", ARMV8_EVENT_62H) \
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__PMC_EV_ALIAS("BUS_ACCESS_NOT_SHARED", ARMV8_EVENT_63H) \
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__PMC_EV_ALIAS("BUS_ACCESS_NORMAL", ARMV8_EVENT_64H) \
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__PMC_EV_ALIAS("BUS_ACCESS_PERIPH", ARMV8_EVENT_65H)
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#define __PMC_EV_ALIAS_ARMV8_CORTEX_A76() \
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__PMC_EV_ALIAS_ARMV8_CORTEX_A57_A76() \
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__PMC_EV_ALIAS("L2D_CACHE_ALLOCATE", ARMV8_EVENT_20H) \
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__PMC_EV_ALIAS("BR_RETIRED", ARMV8_EVENT_21H) \
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__PMC_EV_ALIAS("BR_MIS_PRED_RETIRED", ARMV8_EVENT_22H) \
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__PMC_EV_ALIAS("STALL_FRONTEND", ARMV8_EVENT_23H) \
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__PMC_EV_ALIAS("STALL_BACKEND", ARMV8_EVENT_24H) \
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__PMC_EV_ALIAS("L1D_TLB", ARMV8_EVENT_25H) \
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__PMC_EV_ALIAS("L1I_TLB", ARMV8_EVENT_26H) \
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__PMC_EV_ALIAS("L3D_CACHE_ALLOCATE", ARMV8_EVENT_29H) \
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__PMC_EV_ALIAS("L3D_CACHE_REFILL", ARMV8_EVENT_2AH) \
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__PMC_EV_ALIAS("L3D_CACHE", ARMV8_EVENT_2BH) \
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__PMC_EV_ALIAS("L2D_TLB_REFILL", ARMV8_EVENT_2DH) \
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__PMC_EV_ALIAS("L2D_TLB", ARMV8_EVENT_2FH) \
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__PMC_EV_ALIAS("REMOTE_ACCESS", ARMV8_EVENT_31H) \
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__PMC_EV_ALIAS("DTLB_WALK", ARMV8_EVENT_34H) \
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__PMC_EV_ALIAS("ITLB_WALK", ARMV8_EVENT_35H) \
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__PMC_EV_ALIAS("LL_CACHE_RD", ARMV8_EVENT_36H) \
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__PMC_EV_ALIAS("LL_CACHE_MISS_RD", ARMV8_EVENT_37H) \
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__PMC_EV_ALIAS("L1D_CACHE_REFILL_INNER", ARMV8_EVENT_44H) \
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__PMC_EV_ALIAS("L1D_CACHE_REFILL_OUTER", ARMV8_EVENT_45H) \
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__PMC_EV_ALIAS("L1D_TLB_RD", ARMV8_EVENT_4EH) \
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__PMC_EV_ALIAS("L1D_TLB_WR", ARMV8_EVENT_4FH) \
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__PMC_EV_ALIAS("L2D_TLB_REFILL_RD", ARMV8_EVENT_5CH) \
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__PMC_EV_ALIAS("L2D_TLB_REFILL_WR", ARMV8_EVENT_5DH) \
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__PMC_EV_ALIAS("L2D_TLB_RD", ARMV8_EVENT_5EH) \
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__PMC_EV_ALIAS("L2D_TLB_WR", ARMV8_EVENT_5FH) \
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__PMC_EV_ALIAS("STREX_SPEC", ARMV8_EVENT_6FH) \
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__PMC_EV_ALIAS("L3_CACHE_RD", ARMV8_EVENT_A0H)
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/*
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/*
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* MIPS Events from "Programming the MIPS32 24K Core Family",
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* MIPS Events from "Programming the MIPS32 24K Core Family",
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* Document Number: MD00355 Revision 04.63 December 19, 2008
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* Document Number: MD00355 Revision 04.63 December 19, 2008
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@ -127,7 +127,8 @@ extern char pmc_cpuid[PMC_CPUID_LEN];
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__PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \
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__PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \
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__PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \
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__PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \
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__PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \
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__PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \
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__PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57")
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__PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \
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__PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76")
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enum pmc_cputype {
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enum pmc_cputype {
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#undef __PMC_CPU
|
#undef __PMC_CPU
|
||||||
|
Loading…
Reference in New Issue
Block a user