Add support for dumping the configuration of the Intel
82371FB PCI ISA IDE Xcellerator (sic) chip. The IDE function will not be done until Stefan tells me how to access it.
This commit is contained in:
Garrett Wollman
parent
c2dc2eab50
commit
db4a5c0521
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=13590
@ -1,6 +1,6 @@
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/**************************************************************************
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**
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** $Id: pcisupport.c,v 1.24 1995/12/14 09:54:11 phk Exp $
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** $Id: pcisupport.c,v 1.25 1996/01/22 22:43:48 wollman Exp $
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**
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** Device driver for DEC/INTEL PCI chipsets.
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**
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@ -78,7 +78,7 @@ struct condmsg {
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unsigned char mask;
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unsigned char value;
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char flags;
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char *text;
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const char *text;
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};
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static char*
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@ -126,9 +126,12 @@ chipset_probe (pcici_t tag, pcidi_t type)
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#ifndef PCI_QUIET
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#define M_EQ 0 /* mask and return true if equal */
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#define M_NE 1 /* mask and return true if not equal */
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#define M_TR 2 /* don't read config, always true */
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#define M_XX 0 /* end of list */
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#define M_EQ 1 /* mask and return true if equal */
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#define M_NE 2 /* mask and return true if not equal */
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#define M_TR 3 /* don't read config, always true */
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#define M_EN 4 /* mask and print "enabled" if true, "disabled" if false */
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#define M_NN 5 /* opposite sense of M_EN */
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static const struct condmsg conf82425ex[] =
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{
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@ -382,20 +385,16 @@ static const struct condmsg conf82437fx[] =
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{ 0x50, 0xe0, 0x80, M_EQ, "2" },
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{ 0x50, 0xe0, 0x00, M_EQ, "1" },
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{ 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " },
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{ 0x50, 0x08, 0x08, M_EQ, "enabled" },
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{ 0x50, 0x08, 0x00, M_EQ, "disabled" },
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{ 0x50, 0x08, 0x08, M_EN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Busting: " },
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{ 0x50, 0x04, 0x00, M_EQ, "enabled" },
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{ 0x50, 0x04, 0x04, M_EQ, "disabled" },
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{ 0x50, 0x04, 0x00, M_NN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " },
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{ 0x50, 0x02, 0x00, M_EQ, "enabled" },
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{ 0x50, 0x02, 0x02, M_EQ, "disabled" },
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{ 0x50, 0x02, 0x00, M_NN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " },
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{ 0x50, 0x01, 0x00, M_EQ, "enabled\n" },
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{ 0x50, 0x01, 0x01, M_EQ, "disabled\n" },
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{ 0x50, 0x01, 0x00, M_NN, 0 },
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/* CC -- Cache Control Regsiter */
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{ 0x00, 0x00, 0x00, M_TR, "\tCache:" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
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{ 0x52, 0xc0, 0x80, M_EQ, " 512K" },
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{ 0x52, 0xc0, 0x40, M_EQ, " 256K" },
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{ 0x52, 0xc0, 0x00, M_EQ, " NO" },
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@ -404,8 +403,7 @@ static const struct condmsg conf82437fx[] =
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{ 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
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{ 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
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{ 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
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{ 0x52, 0x01, 0x01, M_EQ, "disabled" },
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{ 0x52, 0x01, 0x00, M_EQ, "enabled" },
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{ 0x52, 0x01, 0x00, M_NN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n" },
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/* DRAMC -- DRAM Control Register */
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@ -434,32 +432,73 @@ static const struct condmsg conf82437fx[] =
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{ 0x58, 0x04, 0x04, M_EQ, "2" },
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{ 0x00, 0x00, 0x00, M_TR, " clocks\n" },
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#ifdef notdef /* XXX not very useful... */
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#define B(x) (1 << x)
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/* PAMs -- Programmable Attribute Map Registers */
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{ 0x00, 0x00, 0x00, M_TR, "\tNon-cacheable regions:" },
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{ 0x00, 0x00, 0x00, M_TR, " A0000-BFFFF" },
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{ 0x5a, B(2), 0, M_EQ, " C0000" },
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{ 0x5a, B(6), 0, M_EQ, " C4000" },
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{ 0x5b, B(2), 0, M_EQ, " C8000" },
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{ 0x5b, B(6), 0, M_EQ, " CC000" },
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{ 0x5c, B(2), 0, M_EQ, " D0000" },
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{ 0x5c, B(6), 0, M_EQ, " D4000" },
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{ 0x5d, B(2), 0, M_EQ, " D8000" },
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{ 0x5d, B(6), 0, M_EQ, " DC000" },
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{ 0x5e, B(2), 0, M_EQ, " E0000" },
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{ 0x5e, B(6), 0, M_EQ, " E4000" },
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{ 0x5f, B(2), 0, M_EQ, " E8000" },
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{ 0x5f, B(6), 0, M_EQ, " EC000" },
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{ 0x59, B(6), 0, M_EQ, " F0000" },
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/* don't bother with r-o, w-o, r-w, disabled */
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#endif
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/* end marker */
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{ 0 }
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};
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static const struct condmsg conf82371fb[] =
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{
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/* IORT -- ISA I/O Recovery Timer Register */
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{ 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " },
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{ 0x4c, 0x40, 0x00, M_EQ, "3.5" },
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{ 0x4c, 0x78, 0x48, M_EQ, "1" },
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{ 0x4c, 0x78, 0x50, M_EQ, "2" },
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{ 0x4c, 0x78, 0x58, M_EQ, "3" },
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{ 0x4c, 0x78, 0x60, M_EQ, "4" },
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{ 0x4c, 0x78, 0x68, M_EQ, "5" },
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{ 0x4c, 0x78, 0x70, M_EQ, "6" },
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{ 0x4c, 0x78, 0x78, M_EQ, "7" },
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{ 0x4c, 0x78, 0x40, M_EQ, "8" },
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{ 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " },
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{ 0x4c, 0x04, 0x00, M_EQ, "3.5" },
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{ 0x4c, 0x07, 0x05, M_EQ, "1" },
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{ 0x4c, 0x07, 0x06, M_EQ, "2" },
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{ 0x4c, 0x07, 0x07, M_EQ, "3" },
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{ 0x4c, 0x07, 0x04, M_EQ, "4" },
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{ 0x00, 0x00, 0x00, M_TR, " clocks\n" },
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/* XBCS -- X-Bus Chip Select Register */
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{ 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " },
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{ 0x4e, 0x80, 0x80, M_EN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " },
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{ 0x4e, 0x40, 0x40, M_EN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " },
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{ 0x4e, 0x20, 0x20, M_EN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " },
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{ 0x4e, 0x10, 0x10, M_EN, 0 },
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{ 0x00, 0x00, 0x00, M_TR, "\n" },
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#define PIRQ(x, n) \
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{ 0x00, 0x00, 0x00, M_TR, "\t" n " Routing: " }, \
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{ x, 0x80, 0x80, M_EQ, "disabled" }, \
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{ x, 0xc0, 0x40, M_EQ, "[shared] " }, \
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{ x, 0x8f, 0x03, M_EQ, "IRQ3" }, \
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{ x, 0x8f, 0x04, M_EQ, "IRQ4" }, \
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{ x, 0x8f, 0x05, M_EQ, "IRQ5" }, \
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{ x, 0x8f, 0x06, M_EQ, "IRQ6" }, \
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{ x, 0x8f, 0x07, M_EQ, "IRQ7" }, \
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{ x, 0x8f, 0x09, M_EQ, "IRQ9" }, \
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{ x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \
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{ x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \
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{ x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \
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{ x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \
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{ x, 0x8f, 0x0f, M_EQ, "IRQ15" }, \
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{ 0x00, 0x00, 0x00, M_TR, "\n" }
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/* Interrupt routing */
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PIRQ(0x60, "INTA"),
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PIRQ(0x61, "INTB"),
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PIRQ(0x62, "INTC"),
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PIRQ(0x63, "INTD"),
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PIRQ(0x70, "MBIRQ0"),
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PIRQ(0x71, "MBIRQ1"),
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#undef PIRQ
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/* XXX - do DMA routing, too? */
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{ 0 }
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};
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static char confread (pcici_t config_id, int port)
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{
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unsigned long portw = port & ~3;
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@ -472,22 +511,28 @@ static char confread (pcici_t config_id, int port)
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static void
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writeconfig (pcici_t config_id, const struct condmsg *tbl)
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{
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while (tbl->text) {
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int cond = 0;
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while (tbl->flags != M_XX) {
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const char *text = 0;
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if (tbl->flags == M_TR) {
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cond = 1;
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text = tbl->text;
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} else {
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unsigned char v = (unsigned char) confread(config_id, tbl->port);
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switch (tbl->flags) {
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case M_EQ:
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if ((v & tbl->mask) == tbl->value) cond = 1;
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if ((v & tbl->mask) == tbl->value) text = tbl->text;
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break;
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case M_NE:
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if ((v & tbl->mask) != tbl->value) cond = 1;
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if ((v & tbl->mask) != tbl->value) text = tbl->text;
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break;
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case M_EN:
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text = (v & tbl->mask) ? "enabled" : "disabled";
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break;
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case M_NN:
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text = (v & tbl->mask) ? "disabled" : "enabled";
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}
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}
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if (cond) printf ("%s", tbl->text);
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if (text) printf ("%s", text);
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tbl++;
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}
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}
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@ -524,6 +569,9 @@ chipset_attach (pcici_t config_id, int unit)
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case 0x122d8086:
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writeconfig (config_id, conf82437fx);
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break;
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case 0x122e8086:
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writeconfig (config_id, conf82371fb);
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break;
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};
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#endif /* PCI_QUIET */
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}
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