rtwn(4): provide register definitions for RTL8188CE calibration routines.
No functional change intended. MFC after: 4 days
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387c3f1495
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db70ff37a0
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=342673
@ -75,55 +75,58 @@ r92ce_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2],
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uint16_t rx[2])
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{
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uint32_t status;
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int offset = chain * 0x20;
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if (chain == 0) { /* IQ calibration for chain 0. */
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/* IQ calibration settings for chain 0. */
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rtwn_bb_write(sc, 0xe30, 0x10008c1f);
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rtwn_bb_write(sc, 0xe34, 0x10008c1f);
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rtwn_bb_write(sc, 0xe38, 0x82140102);
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rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f);
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rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f);
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rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102);
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if (sc->ntxchains > 1) {
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rtwn_bb_write(sc, 0xe3c, 0x28160202); /* 2T */
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rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202);
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/* IQ calibration settings for chain 1. */
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rtwn_bb_write(sc, 0xe50, 0x10008c22);
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rtwn_bb_write(sc, 0xe54, 0x10008c22);
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rtwn_bb_write(sc, 0xe58, 0x82140102);
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rtwn_bb_write(sc, 0xe5c, 0x28160202);
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rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22);
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rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22);
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rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102);
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rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202);
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} else
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rtwn_bb_write(sc, 0xe3c, 0x28160502); /* 1T */
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rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502);
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/* LO calibration settings. */
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rtwn_bb_write(sc, 0xe4c, 0x001028d1);
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rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1);
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/* We're doing LO and IQ calibration in one shot. */
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rtwn_bb_write(sc, 0xe48, 0xf9000000);
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rtwn_bb_write(sc, 0xe48, 0xf8000000);
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rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
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rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
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} else { /* IQ calibration for chain 1. */
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/* We're doing LO and IQ calibration in one shot. */
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rtwn_bb_write(sc, 0xe60, 0x00000002);
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rtwn_bb_write(sc, 0xe60, 0x00000000);
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rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2);
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rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0);
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}
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/* Give LO and IQ calibrations the time to complete. */
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rtwn_delay(sc, 1000);
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/* Read IQ calibration status. */
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status = rtwn_bb_read(sc, 0xeac);
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status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
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if (status & (1 << (28 + chain * 3)))
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return (0); /* Tx failed. */
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/* Read Tx IQ calibration results. */
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tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff;
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tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff;
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tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)),
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R92C_POWER_IQK_RESULT);
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tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)),
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R92C_POWER_IQK_RESULT);
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if (tx[0] == 0x142 || tx[1] == 0x042)
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return (0); /* Tx failed. */
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if (status & (1 << (27 + chain * 3)))
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return (1); /* Rx failed. */
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/* Read Rx IQ calibration results. */
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rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff;
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rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff;
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rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)),
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R92C_POWER_IQK_RESULT);
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rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)),
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R92C_POWER_IQK_RESULT);
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if (rx[0] == 0x132 || rx[1] == 0x036)
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return (1); /* Rx failed. */
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@ -200,18 +203,18 @@ r92ce_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2],
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if (sc->ntxchains > 1)
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rtwn_bb_write(sc, 0x0b6c, 0x00080000);
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rtwn_bb_write(sc, 0x0e28, 0x80800000);
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rtwn_bb_write(sc, 0x0e40, 0x01007c00);
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rtwn_bb_write(sc, 0x0e44, 0x01004800);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
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rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
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rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
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rtwn_bb_write(sc, 0x0b68, 0x00080000);
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for (chain = 0; chain < sc->ntxchains; chain++) {
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if (chain > 0) {
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/* Put chain 0 on standby. */
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rtwn_bb_write(sc, 0x0e28, 0x00);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
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rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
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rtwn_bb_write(sc, 0x0e28, 0x80800000);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
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/* Enable chain 1. */
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for (i = 0; i < nitems(reg_adda); i++)
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@ -257,7 +260,7 @@ r92ce_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2],
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vals->fpga0_rfifacesw1);
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rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
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rtwn_bb_write(sc, 0x0e28, 0x00);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
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rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
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if (sc->ntxchains > 1)
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rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3);
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@ -691,6 +691,7 @@
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#define R92C_FPGA1_TXINFO 0x90c
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#define R92C_CCK0_SYSTEM 0xa00
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#define R92C_CCK0_AFESETTING 0xa04
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#define R92C_CONFIG_ANT(chain) (0xb68 + (chain) * 4)
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#define R92C_OFDM0_TRXPATHENA 0xc04
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#define R92C_OFDM0_TRMUXPAR 0xc08
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#define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8)
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@ -703,6 +704,20 @@
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#define R92C_OFDM0_RXIQEXTANTA 0xca0
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#define R92C_OFDM0_TXPSEUDONOISEWGT 0xce4
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#define R92C_OFDM1_LSTF 0xd00
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#define R92C_FPGA0_IQK 0xe28
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#define R92C_TX_IQK_TONE(chain) (0xe30 + (chain) * 32)
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#define R92C_RX_IQK_TONE(chain) (0xe34 + (chain) * 32)
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#define R92C_TX_IQK_PI(chain) (0xe38 + (chain) * 32)
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#define R92C_RX_IQK_PI(chain) (0xe3c + (chain) * 32)
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#define R92C_TX_IQK 0xe40
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#define R92C_RX_IQK 0xe44
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#define R92C_IQK_AGC_PTS 0xe48
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#define R92C_IQK_AGC_RSP 0xe4c
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#define R92C_IQK_AGC_CONT 0xe60
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#define R92C_TX_POWER_IQK_BEFORE(chain) (0xe94 + (chain) * 32)
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#define R92C_TX_POWER_IQK_AFTER(chain) (0xe9c + (chain) * 32)
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#define R92C_RX_POWER_IQK_BEFORE(chain) (0xea4 + (chain) * 32)
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#define R92C_RX_POWER_IQK_AFTER(chain) (0xeac + (chain) * 32)
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/* Bits for R92C_FPGA[01]_RFMOD. */
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#define R92C_RFMOD_40MHZ 0x00000001
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@ -828,6 +843,10 @@
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#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f
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#define R92C_OFDM0_AGCCORE1_GAIN_S 0
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/* Bits for R92C_[RT]X_POWER_IQK*. */
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#define R92C_POWER_IQK_RESULT_S 16
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#define R92C_POWER_IQK_RESULT_M 0x03ff0000
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/*
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* RF (6052) registers.
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