Update the hypervisor registers
- Add more registers needed by bhyve [1] - Move EL2 registers from armreg.h to hypervisor.h - Add the register name to hypervisor.h Obtained from: https://github.com/FreeBSD-UPB/freebsd [1]
This commit is contained in:
Andrew Turner
parent
c65f571c89
commit
db724d9005
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=358703
@ -66,13 +66,6 @@
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#define UL(x) UINT64_C(x)
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/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
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#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
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#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
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#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
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#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
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#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
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/* CPACR_EL1 */
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#define CPACR_FPEN_MASK (0x3 << 20)
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#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
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@ -220,10 +213,6 @@
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/* ICC_SRE_EL1 */
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#define ICC_SRE_EL1_SRE (1U << 0)
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/* ICC_SRE_EL2 */
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#define ICC_SRE_EL2_SRE (1U << 0)
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#define ICC_SRE_EL2_EN (1U << 3)
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/* ID_AA64DFR0_EL1 */
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#define ID_AA64DFR0_EL1 MRS_REG(3, 0, 0, 5, 0)
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#define ID_AA64DFR0_DebugVer_SHIFT 0
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@ -34,19 +34,21 @@
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* e.g. specific to EL2, or controlling the hypervisor.
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*/
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/*
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* Architecture feature trap register
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*/
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/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
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#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
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#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
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#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
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#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
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#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
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/* CPTR_EL2 - Architecture feature trap register */
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#define CPTR_RES0 0x7fefc800
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#define CPTR_RES1 0x000033ff
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#define CPTR_TFP 0x00000400
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#define CPTR_TTA 0x00100000
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#define CPTR_TCPAC 0x80000000
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/*
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* Hypervisor Config Register
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*/
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/* HCR_EL2 - Hypervisor Config Register */
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#define HCR_VM 0x0000000000000001
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#define HCR_SWIO 0x0000000000000002
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#define HCR_PTW 0x0000000000000004
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@ -58,6 +60,9 @@
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#define HCR_VSE 0x0000000000000100
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#define HCR_FB 0x0000000000000200
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#define HCR_BSU_MASK 0x0000000000000c00
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#define HCR_BSU_IS 0x0000000000000400
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#define HCR_BSU_OS 0x0000000000000800
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#define HCR_BSU_FS 0x0000000000000c00
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#define HCR_DC 0x0000000000001000
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#define HCR_TWI 0x0000000000002000
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#define HCR_TWE 0x0000000000004000
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@ -69,7 +74,7 @@
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#define HCR_TIDCP 0x0000000000100000
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#define HCR_TACR 0x0000000000200000
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#define HCR_TSW 0x0000000000400000
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#define HCR_TPC 0x0000000000800000
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#define HCR_TPCP 0x0000000000800000
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#define HCR_TPU 0x0000000001000000
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#define HCR_TTLB 0x0000000002000000
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#define HCR_TVM 0x0000000004000000
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@ -92,5 +97,89 @@
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#define HCR_NV1 0x0000080000000000
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#define HCR_AT 0x0000100000000000
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#endif
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/* HPFAR_EL2 - Hypervisor IPA Fault Address Register */
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#define HPFAR_EL2_FIPA_SHIFT 4
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#define HPFAR_EL2_FIPA_MASK 0xfffffffff0
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/* ICC_SRE_EL2 */
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#define ICC_SRE_EL2_SRE (1U << 0)
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#define ICC_SRE_EL2_EN (1U << 3)
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/* SCTLR_EL2 - System Control Register */
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#define SCTLR_EL2_RES1 0x30c50830
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#define SCTLR_EL2_M_SHIFT 0
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#define SCTLR_EL2_M (0x1 << SCTLR_EL2_M_SHIFT)
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#define SCTLR_EL2_A_SHIFT 1
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#define SCTLR_EL2_A (0x1 << SCTLR_EL2_A_SHIFT)
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#define SCTLR_EL2_C_SHIFT 2
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#define SCTLR_EL2_C (0x1 << SCTLR_EL2_C_SHIFT)
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#define SCTLR_EL2_SA_SHIFT 3
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#define SCTLR_EL2_SA (0x1 << SCTLR_EL2_SA_SHIFT)
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#define SCTLR_EL2_I_SHIFT 12
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#define SCTLR_EL2_I (0x1 << SCTLR_EL2_I_SHIFT)
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#define SCTLR_EL2_WXN_SHIFT 19
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#define SCTLR_EL2_WXN (0x1 << SCTLR_EL2_WXN_SHIFT)
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#define SCTLR_EL2_EE_SHIFT 25
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#define SCTLR_EL2_EE (0x1 << SCTLR_EL2_EE_SHIFT)
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/* TCR_EL2 - Translation Control Register */
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#define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23))
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#define TCR_EL2_T0SZ_SHIFT 0
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#define TCR_EL2_T0SZ_MASK (0x3f << TCR_EL2_T0SZ_SHIFT)
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#define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT)
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/* Bits 7:6 are reserved */
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#define TCR_EL2_IRGN0_SHIFT 8
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#define TCR_EL2_IRGN0_MASK (0x3 << TCR_EL2_IRGN0_SHIFT)
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#define TCR_EL2_ORGN0_SHIFT 10
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#define TCR_EL2_ORGN0_MASK (0x3 << TCR_EL2_ORGN0_SHIFT)
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#define TCR_EL2_SH0_SHIFT 12
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#define TCR_EL2_SH0_MASK (0x3 << TCR_EL2_SH0_SHIFT)
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#define TCR_EL2_TG0_SHIFT 14
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#define TCR_EL2_TG0_MASK (0x3 << TCR_EL2_TG0_SHIFT)
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#define TCR_EL2_PS_SHIFT 16
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#define TCR_EL2_PS_32BITS (0 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_36BITS (1 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_40BITS (2 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_42BITS (3 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_44BITS (4 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_48BITS (5 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_52BITS (6 << TCR_EL2_PS_SHIFT) /* ARMv8.2-LPA */
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/* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */
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#define VMPIDR_EL2_U 0x0000000040000000
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#define VMPIDR_EL2_MT 0x0000000001000000
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#define VMPIDR_EL2_RES1 0x0000000080000000
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/* VTCR_EL2 - Virtualization Translation Control Register */
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#define VTCR_EL2_RES1 (0x1 << 31)
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#define VTCR_EL2_T0SZ_MASK 0x3f
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#define VTCR_EL2_SL0_SHIFT 6
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#define VTCR_EL2_SL0_4K_LVL2 (0x0 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_SL0_4K_LVL1 (0x1 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_SL0_4K_LVL0 (0x2 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_IRGN0_SHIFT 8
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#define VTCR_EL2_IRGN0_WBWA (0x1 << VTCR_EL2_IRGN0_SHIFT)
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#define VTCR_EL2_ORGN0_SHIFT 10
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#define VTCR_EL2_ORGN0_WBWA (0x1 << VTCR_EL2_ORGN0_SHIFT)
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#define VTCR_EL2_SH0_SHIFT 12
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#define VTCR_EL2_SH0_NS (0x0 << VTCR_EL2_SH0_SHIFT)
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#define VTCR_EL2_SH0_OS (0x2 << VTCR_EL2_SH0_SHIFT)
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#define VTCR_EL2_SH0_IS (0x3 << VTCR_EL2_SH0_SHIFT)
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#define VTCR_EL2_TG0_SHIFT 14
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#define VTCR_EL2_TG0_4K (0x0 << VTCR_EL2_TG0_SHIFT)
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#define VTCR_EL2_TG0_64K (0x1 << VTCR_EL2_TG0_SHIFT)
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#define VTCR_EL2_TG0_16K (0x2 << VTCR_EL2_TG0_SHIFT)
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#define VTCR_EL2_PS_SHIFT 16
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#define VTCR_EL2_PS_32BIT (0x0 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_36BIT (0x1 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_40BIT (0x2 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_42BIT (0x3 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_44BIT (0x4 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_48BIT (0x5 << VTCR_EL2_PS_SHIFT)
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/* VTTBR_EL2 - Virtualization Translation Table Base Register */
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#define VTTBR_VMID_MASK 0xffff000000000000
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#define VTTBR_VMID_SHIFT 48
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#define VTTBR_HOST 0x0000000000000000
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#endif /* !_MACHINE_HYPERVISOR_H_ */
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