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[bwn] add initial bwn(4) N-PHY code, ported from Linux b43.

Browse Source 
This is a GPLv2 PHY-N implementation based on the Linux b43 driver,
ported over to work in bwn(4).

I've tested this on the BCM4321 11abgn device, in 11bg and 11a modes.
The b43 PHY code only supports 11abg, no 11n, and 20MHz only wide
channels.

Yes, this is a GPLv2 driver, so it won't be included in the
default builds.

Tested:

* BCM4321 11abgn device (Apple!), 11bg and 11a STA mode.

Obtained from:	Linux b43
This commit is contained in:
Adrian Chadd 2016-05-17 07:09:24 +00:00
parent 8ef24a0d4b
commit dbf8e132e1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=300016
13 changed files with 26868 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

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sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c Normal file
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sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h Normal file
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/*
Broadcom B43 wireless driver
N-PHY core code.
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
Copyright (c) 2016 Adrian Chadd <adrian@FreeBSD.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
/*
* $FreeBSD$
*/
#ifndef __IF_BWN_PHY_N_CORE_H__
#define __IF_BWN_PHY_N_CORE_H__
struct bwn_mac;
enum b43_nphy_spur_avoid {
BWN_SPUR_AVOID_DISABLE,
BWN_SPUR_AVOID_AUTO,
BWN_SPUR_AVOID_FORCE,
};
/*
* TODO: determine whether center_freq is the primary
* channel centre frequency or the actual centre centre
* frequency (eg radio tuning.) It /looks/ like it's
* actual channel centre.
*/
struct bwn_chanspec {
uint16_t center_freq;
/* This is HT40U, HT40D, HT20, no-HT 20, etc */
bwn_chan_type_t channel_type;
};
struct bwn_phy_n_iq_comp {
int16_t a0;
int16_t b0;
int16_t a1;
int16_t b1;
};
struct bwn_phy_n_rssical_cache {
uint16_t rssical_radio_regs_2G[2];
uint16_t rssical_phy_regs_2G[12];
uint16_t rssical_radio_regs_5G[2];
uint16_t rssical_phy_regs_5G[12];
};
struct bwn_phy_n_cal_cache {
uint16_t txcal_radio_regs_2G[8];
uint16_t txcal_coeffs_2G[8];
struct bwn_phy_n_iq_comp rxcal_coeffs_2G;
uint16_t txcal_radio_regs_5G[8];
uint16_t txcal_coeffs_5G[8];
struct bwn_phy_n_iq_comp rxcal_coeffs_5G;
};
struct bwn_phy_n_txpwrindex {
int8_t index;
int8_t index_internal;
int8_t index_internal_save;
uint16_t AfectrlOverride;
uint16_t AfeCtrlDacGain;
uint16_t rad_gain;
uint8_t bbmult;
uint16_t iqcomp_a;
uint16_t iqcomp_b;
uint16_t locomp;
};
struct bwn_phy_n_pwr_ctl_info {
uint8_t idle_tssi_2g;
uint8_t idle_tssi_5g;
};
struct bwn_phy_n {
uint8_t antsel_type;
uint8_t cal_orig_pwr_idx[2];
uint8_t measure_hold;
uint8_t phyrxchain;
uint8_t hw_phyrxchain;
uint8_t hw_phytxchain;
uint8_t perical;
uint32_t deaf_count;
uint32_t rxcalparams;
bool hang_avoid;
bool mute;
uint16_t papd_epsilon_offset[2];
int32_t preamble_override;
uint32_t bb_mult_save;
bool gain_boost;
bool elna_gain_config;
bool band5g_pwrgain;
bool use_int_tx_iq_lo_cal;
bool lpf_bw_overrode_for_sample_play;
uint8_t mphase_cal_phase_id;
uint16_t mphase_txcal_cmdidx;
uint16_t mphase_txcal_numcmds;
uint16_t mphase_txcal_bestcoeffs[11];
bool txpwrctrl;
bool pwg_gain_5ghz;
uint8_t tx_pwr_idx[2];
int8_t tx_power_offset[101];
uint16_t adj_pwr_tbl[84];
uint16_t txcal_bbmult;
uint16_t txiqlocal_bestc[11];
bool txiqlocal_coeffsvalid;
struct bwn_phy_n_txpwrindex txpwrindex[2];
struct bwn_phy_n_pwr_ctl_info pwr_ctl_info[2];
struct bwn_chanspec txiqlocal_chanspec;
struct bwn_ppr tx_pwr_max_ppr;
uint16_t tx_pwr_last_recalc_freq;
int tx_pwr_last_recalc_limit;
uint8_t txrx_chain;
uint16_t tx_rx_cal_phy_saveregs[11];
uint16_t tx_rx_cal_radio_saveregs[22];
uint16_t rfctrl_intc1_save;
uint16_t rfctrl_intc2_save;
uint16_t classifier_state;
uint16_t clip_state[2];
enum b43_nphy_spur_avoid spur_avoid;
bool aband_spurwar_en;
bool gband_spurwar_en;
bool ipa2g_on;
struct bwn_chanspec iqcal_chanspec_2G;
struct bwn_chanspec rssical_chanspec_2G;
bool ipa5g_on;
struct bwn_chanspec iqcal_chanspec_5G;
struct bwn_chanspec rssical_chanspec_5G;
struct bwn_phy_n_rssical_cache rssical_cache;
struct bwn_phy_n_cal_cache cal_cache;
bool crsminpwr_adjusted;
bool noisevars_adjusted;
};
extern bwn_txpwr_result_t bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi);
extern int bwn_nphy_op_allocate(struct bwn_mac *mac);
extern void bwn_nphy_op_prepare_structs(struct bwn_mac *mac);
extern void bwn_nphy_op_free(struct bwn_mac *mac);
extern int bwn_nphy_op_init(struct bwn_mac *mac);
extern void bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, uint16_t set);
extern uint16_t bwn_nphy_op_radio_read(struct bwn_mac *mac, uint16_t reg);
extern void bwn_nphy_op_radio_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);
extern void bwn_nphy_op_software_rfkill(struct bwn_mac *mac, bool blocked);
extern void bwn_nphy_op_switch_analog(struct bwn_mac *mac, bool on);
extern int bwn_nphy_op_switch_channel(struct bwn_mac *mac, unsigned int new_channel);
extern unsigned int bwn_nphy_op_get_default_chan(struct bwn_mac *mac);
#endif /* __IF_BWN_PHY_N_CORE_H__ */

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/*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* The Broadcom Wireless LAN controller driver.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/endian.h>
#include <sys/errno.h>
#include <sys/firmware.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <net/if_var.h>
#include <net/if_arp.h>
#include <net/if_dl.h>
#include <net/if_llc.h>
#include <net/if_media.h>
#include <net/if_types.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/siba/siba_ids.h>
#include <dev/siba/sibareg.h>
#include <dev/siba/sibavar.h>
#include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_radiotap.h>
#include <net80211/ieee80211_regdomain.h>
#include <net80211/ieee80211_phy.h>
#include <net80211/ieee80211_ratectl.h>
#include <dev/bwn/if_bwnreg.h>
#include <dev/bwn/if_bwnvar.h>
#include <dev/bwn/if_bwn_debug.h>
#include <dev/bwn/if_bwn_util.h>
#include <dev/bwn/if_bwn_phy_common.h>
#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h>
#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h>
#define ppr_for_each_entry(ppr, i, entry) \
for (i = 0, entry = &(ppr)->__all_rates[i]; \
i < BWN_PPR_RATES_NUM; \
i++, entry++)
void bwn_ppr_clear(struct bwn_mac *mac, struct bwn_ppr *ppr)
{
memset(ppr, 0, sizeof(*ppr));
/* Compile-time PPR check */
CTASSERT(sizeof(struct bwn_ppr) == BWN_PPR_RATES_NUM * sizeof(uint8_t));
}
void bwn_ppr_add(struct bwn_mac *mac, struct bwn_ppr *ppr, int diff)
{
int i;
uint8_t *rate;
ppr_for_each_entry(ppr, i, rate) {
*rate = bwn_clamp_val(*rate + diff, 0, 127);
}
}
void bwn_ppr_apply_max(struct bwn_mac *mac, struct bwn_ppr *ppr, uint8_t max)
{
int i;
uint8_t *rate;
ppr_for_each_entry(ppr, i, rate) {
*rate = min(*rate, max);
}
}
void bwn_ppr_apply_min(struct bwn_mac *mac, struct bwn_ppr *ppr, uint8_t min)
{
int i;
uint8_t *rate;
ppr_for_each_entry(ppr, i, rate) {
*rate = max(*rate, min);
}
}
uint8_t bwn_ppr_get_max(struct bwn_mac *mac, struct bwn_ppr *ppr)
{
uint8_t res = 0;
int i;
uint8_t *rate;
ppr_for_each_entry(ppr, i, rate) {
res = max(*rate, res);
}
return res;
}
bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac, struct bwn_ppr *ppr,
bwn_phy_band_t band)
{
struct bwn_softc *sc = mac->mac_sc;
struct siba_sprom_core_pwr_info core_pwr_info[4];
struct bwn_ppr_rates *rates = &ppr->rates;
struct bwn_phy *phy = &mac->mac_phy;
uint8_t maxpwr, off;
uint32_t sprom_ofdm_po;
uint16_t sprom_mcs_po[8];
uint8_t extra_cdd_po, extra_stbc_po;
int i;
for (i = 0; i < 4; i++) {
bzero(&core_pwr_info[i], sizeof(core_pwr_info[i]));
if (siba_sprom_get_core_power_info(sc->sc_dev, i,
&core_pwr_info[i]) != 0) {
BWN_ERRPRINTF(mac->mac_sc,
"%s: failed to get core_pwr_info for core %d\n",
__func__,
i);
}
}
switch (band) {
case BWN_PHY_BAND_2G:
maxpwr = min(core_pwr_info[0].maxpwr_2g,
core_pwr_info[1].maxpwr_2g);
sprom_ofdm_po = siba_sprom_get_ofdm2gpo(sc->sc_dev);
siba_sprom_get_mcs2gpo(sc->sc_dev, sprom_mcs_po);
extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 0) & 0xf;
extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 0) & 0xf;
break;
case BWN_PHY_BAND_5G_LO:
maxpwr = min(core_pwr_info[0].maxpwr_5gl,
core_pwr_info[1].maxpwr_5gl);
sprom_ofdm_po = siba_sprom_get_ofdm5glpo(sc->sc_dev);
siba_sprom_get_mcs5glpo(sc->sc_dev, sprom_mcs_po);
extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 8) & 0xf;
extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 8) & 0xf;
break;
case BWN_PHY_BAND_5G_MI:
maxpwr = min(core_pwr_info[0].maxpwr_5g,
core_pwr_info[1].maxpwr_5g);
sprom_ofdm_po = siba_sprom_get_ofdm5gpo(sc->sc_dev);
siba_sprom_get_mcs5gpo(sc->sc_dev, sprom_mcs_po);
extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 4) & 0xf;
extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 4) & 0xf;
break;
case BWN_PHY_BAND_5G_HI:
maxpwr = min(core_pwr_info[0].maxpwr_5gh,
core_pwr_info[1].maxpwr_5gh);
sprom_ofdm_po = siba_sprom_get_ofdm5ghpo(sc->sc_dev);
siba_sprom_get_mcs5ghpo(sc->sc_dev, sprom_mcs_po);
extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 12) & 0xf;
extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 12) & 0xf;
break;
default:
device_printf(mac->mac_sc->sc_dev, "%s: invalid band (%d)\n",
__func__,
band);
return false;
}
if (band == BWN_BAND_2G) {
for (i = 0; i < 4; i++) {
off = ((siba_sprom_get_cck2gpo(sc->sc_dev) >> (i * 4)) & 0xf) * 2;
rates->cck[i] = maxpwr - off;
}
}
/* OFDM */
for (i = 0; i < 8; i++) {
off = ((sprom_ofdm_po >> (i * 4)) & 0xf) * 2;
rates->ofdm[i] = maxpwr - off;
}
/* MCS 20 SISO */
rates->mcs_20[0] = rates->ofdm[0];
rates->mcs_20[1] = rates->ofdm[2];
rates->mcs_20[2] = rates->ofdm[3];
rates->mcs_20[3] = rates->ofdm[4];
rates->mcs_20[4] = rates->ofdm[5];
rates->mcs_20[5] = rates->ofdm[6];
rates->mcs_20[6] = rates->ofdm[7];
rates->mcs_20[7] = rates->ofdm[7];
/* MCS 20 CDD */
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_cdd[i] = maxpwr - off;
if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_cdd[i] -= extra_cdd_po;
}
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_cdd[4 + i] = maxpwr - off;
if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_cdd[4 + i] -= extra_cdd_po;
}
/* OFDM 20 CDD */
rates->ofdm_20_cdd[0] = rates->mcs_20_cdd[0];
rates->ofdm_20_cdd[1] = rates->mcs_20_cdd[0];
rates->ofdm_20_cdd[2] = rates->mcs_20_cdd[1];
rates->ofdm_20_cdd[3] = rates->mcs_20_cdd[2];
rates->ofdm_20_cdd[4] = rates->mcs_20_cdd[3];
rates->ofdm_20_cdd[5] = rates->mcs_20_cdd[4];
rates->ofdm_20_cdd[6] = rates->mcs_20_cdd[5];
rates->ofdm_20_cdd[7] = rates->mcs_20_cdd[6];
/* MCS 20 STBC */
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_stbc[i] = maxpwr - off;
if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_stbc[i] -= extra_stbc_po;
}
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_stbc[4 + i] = maxpwr - off;
if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_stbc[4 + i] -= extra_stbc_po;
}
/* MCS 20 SDM */
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[2] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_sdm[i] = maxpwr - off;
}
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[3] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_sdm[4 + i] = maxpwr - off;
}
return true;
}

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/*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
/*
* $FreeBSD$
*/
#ifndef __IF_BWN_PHY_PPR_H__
#define __IF_BWN_PHY_PPR_H__
#define BWN_PPR_CCK_RATES_NUM 4
#define BWN_PPR_OFDM_RATES_NUM 8
#define BWN_PPR_MCS_RATES_NUM 8
#define BWN_PPR_RATES_NUM (BWN_PPR_CCK_RATES_NUM + \
BWN_PPR_OFDM_RATES_NUM * 2 + \
BWN_PPR_MCS_RATES_NUM * 4)
struct bwn_ppr_rates {
uint8_t cck[BWN_PPR_CCK_RATES_NUM];
uint8_t ofdm[BWN_PPR_OFDM_RATES_NUM];
uint8_t ofdm_20_cdd[BWN_PPR_OFDM_RATES_NUM];
uint8_t mcs_20[BWN_PPR_MCS_RATES_NUM]; /* single stream rates */
uint8_t mcs_20_cdd[BWN_PPR_MCS_RATES_NUM];
uint8_t mcs_20_stbc[BWN_PPR_MCS_RATES_NUM];
uint8_t mcs_20_sdm[BWN_PPR_MCS_RATES_NUM];
};
struct bwn_ppr {
/* All powers are in 1/4 dBm (Q5.2) */
union {
uint8_t __all_rates[BWN_PPR_RATES_NUM];
struct bwn_ppr_rates rates;
};
};
extern void bwn_ppr_clear(struct bwn_mac *mac, struct bwn_ppr *ppr);
extern void bwn_ppr_add(struct bwn_mac *mac, struct bwn_ppr *ppr, int diff);
extern void bwn_ppr_apply_max(struct bwn_mac *mac, struct bwn_ppr *ppr,
uint8_t max);
extern void bwn_ppr_apply_min(struct bwn_mac *mac, struct bwn_ppr *ppr,
uint8_t min);
extern uint8_t bwn_ppr_get_max(struct bwn_mac *mac, struct bwn_ppr *ppr);
extern bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac,
struct bwn_ppr *ppr, bwn_phy_band_t band);
#endif

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/*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
/*
* $FreeBSD$
*/
#ifndef __IF_BWN_PHY_N_REGS_H__
#define __IF_BWN_PHY_N_REGS_H__
/* N-PHY registers. */
#define BWN_NPHY_BBCFG BWN_PHY_N(0x001) /* BB config */
#define BWN_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
#define BWN_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
#define BWN_NPHY_CHANNEL BWN_PHY_N(0x005) /* Channel */
#define BWN_NPHY_TXERR BWN_PHY_N(0x007) /* TX error */
#define BWN_NPHY_BANDCTL BWN_PHY_N(0x009) /* Band control */
#define BWN_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
#define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */
#define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */
#define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */
#define BWN_NPHY_BIST_STAT0 BWN_PHY_N(0x00E) /* Built-in self test status 0 */
#define BWN_NPHY_BIST_STAT1 BWN_PHY_N(0x00F) /* Built-in self test status 1 */
#define BWN_NPHY_C1_DESPWR BWN_PHY_N(0x018) /* Core 1 desired power */
#define BWN_NPHY_C1_CCK_DESPWR BWN_PHY_N(0x019) /* Core 1 CCK desired power */
#define BWN_NPHY_C1_BCLIPBKOFF BWN_PHY_N(0x01A) /* Core 1 barely clip backoff */
#define BWN_NPHY_C1_CCK_BCLIPBKOFF BWN_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */
#define BWN_NPHY_C1_CGAINI BWN_PHY_N(0x01C) /* Core 1 compute gain info */
#define BWN_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
#define BWN_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0
#define BWN_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
#define BWN_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT 5
#define BWN_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */
#define BWN_NPHY_C1_CGAINI_GAINSTEP_SHIFT 10
#define BWN_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
#define BWN_NPHY_C1_CCK_CGAINI BWN_PHY_N(0x01D) /* Core 1 CCK compute gain info */
#define BWN_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
#define BWN_NPHY_C1_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */
#define BWN_NPHY_C1_MINMAX_GAIN BWN_PHY_N(0x01E) /* Core 1 min/max gain */
#define BWN_NPHY_C1_MINGAIN 0x00FF /* Minimum gain */
#define BWN_NPHY_C1_MINGAIN_SHIFT 0
#define BWN_NPHY_C1_MAXGAIN 0xFF00 /* Maximum gain */
#define BWN_NPHY_C1_MAXGAIN_SHIFT 8
#define BWN_NPHY_C1_CCK_MINMAX_GAIN BWN_PHY_N(0x01F) /* Core 1 CCK min/max gain */
#define BWN_NPHY_C1_CCK_MINGAIN 0x00FF /* Minimum gain */
#define BWN_NPHY_C1_CCK_MINGAIN_SHIFT 0
#define BWN_NPHY_C1_CCK_MAXGAIN 0xFF00 /* Maximum gain */
#define BWN_NPHY_C1_CCK_MAXGAIN_SHIFT 8
#define BWN_NPHY_C1_INITGAIN BWN_PHY_N(0x020) /* Core 1 initial gain code */
#define BWN_NPHY_C1_INITGAIN_EXTLNA 0x0001 /* External LNA index */
#define BWN_NPHY_C1_INITGAIN_LNA 0x0006 /* LNA index */
#define BWN_NPHY_C1_INITGAIN_LNAIDX_SHIFT 1
#define BWN_NPHY_C1_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */
#define BWN_NPHY_C1_INITGAIN_HPVGA1_SHIFT 3
#define BWN_NPHY_C1_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */
#define BWN_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
#define BWN_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
#define BWN_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
#define BWN_NPHY_REV3_C1_INITGAIN_A BWN_PHY_N(0x020)
#define BWN_NPHY_C1_CLIP1_HIGAIN BWN_PHY_N(0x021) /* Core 1 clip1 high gain code */
#define BWN_NPHY_REV3_C1_INITGAIN_B BWN_PHY_N(0x021)
#define BWN_NPHY_C1_CLIP1_MEDGAIN BWN_PHY_N(0x022) /* Core 1 clip1 medium gain code */
#define BWN_NPHY_REV3_C1_CLIP_HIGAIN_A BWN_PHY_N(0x022)
#define BWN_NPHY_C1_CLIP1_LOGAIN BWN_PHY_N(0x023) /* Core 1 clip1 low gain code */
#define BWN_NPHY_REV3_C1_CLIP_HIGAIN_B BWN_PHY_N(0x023)
#define BWN_NPHY_C1_CLIP2_GAIN BWN_PHY_N(0x024) /* Core 1 clip2 gain code */
#define BWN_NPHY_REV3_C1_CLIP_MEDGAIN_A BWN_PHY_N(0x024)
#define BWN_NPHY_C1_FILTERGAIN BWN_PHY_N(0x025) /* Core 1 filter gain */
#define BWN_NPHY_C1_LPF_QHPF_BW BWN_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
#define BWN_NPHY_C1_CLIPWBTHRES BWN_PHY_N(0x027) /* Core 1 clip wideband threshold */
#define BWN_NPHY_C1_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */
#define BWN_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT 0
#define BWN_NPHY_C1_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */
#define BWN_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT 6
#define BWN_NPHY_C1_W1THRES BWN_PHY_N(0x028) /* Core 1 W1 threshold */
#define BWN_NPHY_C1_EDTHRES BWN_PHY_N(0x029) /* Core 1 ED threshold */
#define BWN_NPHY_C1_SMSIGTHRES BWN_PHY_N(0x02A) /* Core 1 small sig threshold */
#define BWN_NPHY_C1_NBCLIPTHRES BWN_PHY_N(0x02B) /* Core 1 NB clip threshold */
#define BWN_NPHY_C1_CLIP1THRES BWN_PHY_N(0x02C) /* Core 1 clip1 threshold */
#define BWN_NPHY_C1_CLIP2THRES BWN_PHY_N(0x02D) /* Core 1 clip2 threshold */
#define BWN_NPHY_C2_DESPWR BWN_PHY_N(0x02E) /* Core 2 desired power */
#define BWN_NPHY_C2_CCK_DESPWR BWN_PHY_N(0x02F) /* Core 2 CCK desired power */
#define BWN_NPHY_C2_BCLIPBKOFF BWN_PHY_N(0x030) /* Core 2 barely clip backoff */
#define BWN_NPHY_C2_CCK_BCLIPBKOFF BWN_PHY_N(0x031) /* Core 2 CCK barely clip backoff */
#define BWN_NPHY_C2_CGAINI BWN_PHY_N(0x032) /* Core 2 compute gain info */
#define BWN_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
#define BWN_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0
#define BWN_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
#define BWN_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT 5
#define BWN_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */
#define BWN_NPHY_C2_CGAINI_GAINSTEP_SHIFT 10
#define BWN_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
#define BWN_NPHY_C2_CCK_CGAINI BWN_PHY_N(0x033) /* Core 2 CCK compute gain info */
#define BWN_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
#define BWN_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */
#define BWN_NPHY_C2_MINMAX_GAIN BWN_PHY_N(0x034) /* Core 2 min/max gain */
#define BWN_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */
#define BWN_NPHY_C2_MINGAIN_SHIFT 0
#define BWN_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */
#define BWN_NPHY_C2_MAXGAIN_SHIFT 8
#define BWN_NPHY_C2_CCK_MINMAX_GAIN BWN_PHY_N(0x035) /* Core 2 CCK min/max gain */
#define BWN_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */
#define BWN_NPHY_C2_CCK_MINGAIN_SHIFT 0
#define BWN_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */
#define BWN_NPHY_C2_CCK_MAXGAIN_SHIFT 8
#define BWN_NPHY_C2_INITGAIN BWN_PHY_N(0x036) /* Core 2 initial gain code */
#define BWN_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */
#define BWN_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */
#define BWN_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1
#define BWN_NPHY_C2_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */
#define BWN_NPHY_C2_INITGAIN_HPVGA1_SHIFT 3
#define BWN_NPHY_C2_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */
#define BWN_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
#define BWN_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
#define BWN_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
#define BWN_NPHY_REV3_C1_CLIP_MEDGAIN_B BWN_PHY_N(0x036)
#define BWN_NPHY_C2_CLIP1_HIGAIN BWN_PHY_N(0x037) /* Core 2 clip1 high gain code */
#define BWN_NPHY_REV3_C1_CLIP_LOGAIN_A BWN_PHY_N(0x037)
#define BWN_NPHY_C2_CLIP1_MEDGAIN BWN_PHY_N(0x038) /* Core 2 clip1 medium gain code */
#define BWN_NPHY_REV3_C1_CLIP_LOGAIN_B BWN_PHY_N(0x038)
#define BWN_NPHY_C2_CLIP1_LOGAIN BWN_PHY_N(0x039) /* Core 2 clip1 low gain code */
#define BWN_NPHY_REV3_C1_CLIP2_GAIN_A BWN_PHY_N(0x039)
#define BWN_NPHY_C2_CLIP2_GAIN BWN_PHY_N(0x03A) /* Core 2 clip2 gain code */
#define BWN_NPHY_REV3_C1_CLIP2_GAIN_B BWN_PHY_N(0x03A)
#define BWN_NPHY_C2_FILTERGAIN BWN_PHY_N(0x03B) /* Core 2 filter gain */
#define BWN_NPHY_C2_LPF_QHPF_BW BWN_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
#define BWN_NPHY_C2_CLIPWBTHRES BWN_PHY_N(0x03D) /* Core 2 clip wideband threshold */
#define BWN_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */
#define BWN_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0
#define BWN_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */
#define BWN_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6
#define BWN_NPHY_C2_W1THRES BWN_PHY_N(0x03E) /* Core 2 W1 threshold */
#define BWN_NPHY_C2_EDTHRES BWN_PHY_N(0x03F) /* Core 2 ED threshold */
#define BWN_NPHY_C2_SMSIGTHRES BWN_PHY_N(0x040) /* Core 2 small sig threshold */
#define BWN_NPHY_C2_NBCLIPTHRES BWN_PHY_N(0x041) /* Core 2 NB clip threshold */
#define BWN_NPHY_C2_CLIP1THRES BWN_PHY_N(0x042) /* Core 2 clip1 threshold */
#define BWN_NPHY_C2_CLIP2THRES BWN_PHY_N(0x043) /* Core 2 clip2 threshold */
#define BWN_NPHY_CRS_THRES1 BWN_PHY_N(0x044) /* CRS threshold 1 */
#define BWN_NPHY_CRS_THRES2 BWN_PHY_N(0x045) /* CRS threshold 2 */
#define BWN_NPHY_CRS_THRES3 BWN_PHY_N(0x046) /* CRS threshold 3 */
#define BWN_NPHY_CRSCTL BWN_PHY_N(0x047) /* CRS control */
#define BWN_NPHY_DCFADDR BWN_PHY_N(0x048) /* DC filter address */
#define BWN_NPHY_RXF20_NUM0 BWN_PHY_N(0x049) /* RX filter 20 numerator 0 */
#define BWN_NPHY_RXF20_NUM1 BWN_PHY_N(0x04A) /* RX filter 20 numerator 1 */
#define BWN_NPHY_RXF20_NUM2 BWN_PHY_N(0x04B) /* RX filter 20 numerator 2 */
#define BWN_NPHY_RXF20_DENOM0 BWN_PHY_N(0x04C) /* RX filter 20 denominator 0 */
#define BWN_NPHY_RXF20_DENOM1 BWN_PHY_N(0x04D) /* RX filter 20 denominator 1 */
#define BWN_NPHY_RXF20_NUM10 BWN_PHY_N(0x04E) /* RX filter 20 numerator 10 */
#define BWN_NPHY_RXF20_NUM11 BWN_PHY_N(0x04F) /* RX filter 20 numerator 11 */
#define BWN_NPHY_RXF20_NUM12 BWN_PHY_N(0x050) /* RX filter 20 numerator 12 */
#define BWN_NPHY_RXF20_DENOM10 BWN_PHY_N(0x051) /* RX filter 20 denominator 10 */
#define BWN_NPHY_RXF20_DENOM11 BWN_PHY_N(0x052) /* RX filter 20 denominator 11 */
#define BWN_NPHY_RXF40_NUM0 BWN_PHY_N(0x053) /* RX filter 40 numerator 0 */
#define BWN_NPHY_RXF40_NUM1 BWN_PHY_N(0x054) /* RX filter 40 numerator 1 */
#define BWN_NPHY_RXF40_NUM2 BWN_PHY_N(0x055) /* RX filter 40 numerator 2 */
#define BWN_NPHY_RXF40_DENOM0 BWN_PHY_N(0x056) /* RX filter 40 denominator 0 */
#define BWN_NPHY_RXF40_DENOM1 BWN_PHY_N(0x057) /* RX filter 40 denominator 1 */
#define BWN_NPHY_RXF40_NUM10 BWN_PHY_N(0x058) /* RX filter 40 numerator 10 */
#define BWN_NPHY_RXF40_NUM11 BWN_PHY_N(0x059) /* RX filter 40 numerator 11 */
#define BWN_NPHY_RXF40_NUM12 BWN_PHY_N(0x05A) /* RX filter 40 numerator 12 */
#define BWN_NPHY_RXF40_DENOM10 BWN_PHY_N(0x05B) /* RX filter 40 denominator 10 */
#define BWN_NPHY_RXF40_DENOM11 BWN_PHY_N(0x05C) /* RX filter 40 denominator 11 */
#define BWN_NPHY_PPROC_RSTLEN BWN_PHY_N(0x060) /* Packet processing reset length */
#define BWN_NPHY_INITCARR_DLEN BWN_PHY_N(0x061) /* Initial carrier detection length */
#define BWN_NPHY_CLIP1CARR_DLEN BWN_PHY_N(0x062) /* Clip1 carrier detection length */
#define BWN_NPHY_CLIP2CARR_DLEN BWN_PHY_N(0x063) /* Clip2 carrier detection length */
#define BWN_NPHY_INITGAIN_SLEN BWN_PHY_N(0x064) /* Initial gain settle length */
#define BWN_NPHY_CLIP1GAIN_SLEN BWN_PHY_N(0x065) /* Clip1 gain settle length */
#define BWN_NPHY_CLIP2GAIN_SLEN BWN_PHY_N(0x066) /* Clip2 gain settle length */
#define BWN_NPHY_PACKGAIN_SLEN BWN_PHY_N(0x067) /* Packet gain settle length */
#define BWN_NPHY_CARRSRC_TLEN BWN_PHY_N(0x068) /* Carrier search timeout length */
#define BWN_NPHY_TISRC_TLEN BWN_PHY_N(0x069) /* Timing search timeout length */
#define BWN_NPHY_ENDROP_TLEN BWN_PHY_N(0x06A) /* Energy drop timeout length */
#define BWN_NPHY_CLIP1_NBDWELL_LEN BWN_PHY_N(0x06B) /* Clip1 NB dwell length */
#define BWN_NPHY_CLIP2_NBDWELL_LEN BWN_PHY_N(0x06C) /* Clip2 NB dwell length */
#define BWN_NPHY_W1CLIP1_DWELL_LEN BWN_PHY_N(0x06D) /* W1 clip1 dwell length */
#define BWN_NPHY_W1CLIP2_DWELL_LEN BWN_PHY_N(0x06E) /* W1 clip2 dwell length */
#define BWN_NPHY_W2CLIP1_DWELL_LEN BWN_PHY_N(0x06F) /* W2 clip1 dwell length */
#define BWN_NPHY_PLOAD_CSENSE_EXTLEN BWN_PHY_N(0x070) /* Payload carrier sense extension length */
#define BWN_NPHY_EDROP_CSENSE_EXTLEN BWN_PHY_N(0x071) /* Energy drop carrier sense extension length */
#define BWN_NPHY_TABLE_ADDR BWN_PHY_N(0x072) /* Table address */
#define BWN_NPHY_TABLE_DATALO BWN_PHY_N(0x073) /* Table data low */
#define BWN_NPHY_TABLE_DATAHI BWN_PHY_N(0x074) /* Table data high */
#define BWN_NPHY_WWISE_LENIDX BWN_PHY_N(0x075) /* WWiSE length index */
#define BWN_NPHY_TGNSYNC_LENIDX BWN_PHY_N(0x076) /* TGNsync length index */
#define BWN_NPHY_TXMACIF_HOLDOFF BWN_PHY_N(0x077) /* TX MAC IF Hold off */
#define BWN_NPHY_RFCTL_CMD BWN_PHY_N(0x078) /* RF control (command) */
#define BWN_NPHY_RFCTL_CMD_START 0x0001 /* Start sequence */
#define BWN_NPHY_RFCTL_CMD_RXTX 0x0002 /* RX/TX */
#define BWN_NPHY_RFCTL_CMD_CORESEL 0x0038 /* Core select */
#define BWN_NPHY_RFCTL_CMD_CORESEL_SHIFT 3
#define BWN_NPHY_RFCTL_CMD_PORFORCE 0x0040 /* POR force */
#define BWN_NPHY_RFCTL_CMD_OEPORFORCE 0x0080 /* OE POR force */
#define BWN_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */
#define BWN_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */
#define BWN_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */
#define BWN_NPHY_RFCTL_CMD_EN 0x0800 /* Radio enabled */
#define BWN_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */
#define BWN_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12
#define BWN_NPHY_RFCTL_RSSIO1 BWN_PHY_N(0x07A) /* RF control (RSSI others 1) */
#define BWN_NPHY_RFCTL_RSSIO1_RXPD 0x0001 /* RX PD */
#define BWN_NPHY_RFCTL_RSSIO1_TXPD 0x0002 /* TX PD */
#define BWN_NPHY_RFCTL_RSSIO1_PAPD 0x0004 /* PA PD */
#define BWN_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */
#define BWN_NPHY_RFCTL_RSSIO1_LPFBW 0x00C0 /* LPF bandwidth */
#define BWN_NPHY_RFCTL_RSSIO1_HPFBWHI 0x0100 /* HPF bandwidth high */
#define BWN_NPHY_RFCTL_RSSIO1_HIQDISCO 0x0200 /* HIQ dis core */
#define BWN_NPHY_RFCTL_RXG1 BWN_PHY_N(0x07B) /* RF control (RX gain 1) */
#define BWN_NPHY_RFCTL_TXG1 BWN_PHY_N(0x07C) /* RF control (TX gain 1) */
#define BWN_NPHY_RFCTL_RSSIO2 BWN_PHY_N(0x07D) /* RF control (RSSI others 2) */
#define BWN_NPHY_RFCTL_RSSIO2_RXPD 0x0001 /* RX PD */
#define BWN_NPHY_RFCTL_RSSIO2_TXPD 0x0002 /* TX PD */
#define BWN_NPHY_RFCTL_RSSIO2_PAPD 0x0004 /* PA PD */
#define BWN_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */
#define BWN_NPHY_RFCTL_RSSIO2_LPFBW 0x00C0 /* LPF bandwidth */
#define BWN_NPHY_RFCTL_RSSIO2_HPFBWHI 0x0100 /* HPF bandwidth high */
#define BWN_NPHY_RFCTL_RSSIO2_HIQDISCO 0x0200 /* HIQ dis core */
#define BWN_NPHY_RFCTL_RXG2 BWN_PHY_N(0x07E) /* RF control (RX gain 2) */
#define BWN_NPHY_RFCTL_TXG2 BWN_PHY_N(0x07F) /* RF control (TX gain 2) */
#define BWN_NPHY_RFCTL_RSSIO3 BWN_PHY_N(0x080) /* RF control (RSSI others 3) */
#define BWN_NPHY_RFCTL_RSSIO3_RXPD 0x0001 /* RX PD */
#define BWN_NPHY_RFCTL_RSSIO3_TXPD 0x0002 /* TX PD */
#define BWN_NPHY_RFCTL_RSSIO3_PAPD 0x0004 /* PA PD */
#define BWN_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */
#define BWN_NPHY_RFCTL_RSSIO3_LPFBW 0x00C0 /* LPF bandwidth */
#define BWN_NPHY_RFCTL_RSSIO3_HPFBWHI 0x0100 /* HPF bandwidth high */
#define BWN_NPHY_RFCTL_RSSIO3_HIQDISCO 0x0200 /* HIQ dis core */
#define BWN_NPHY_RFCTL_RXG3 BWN_PHY_N(0x081) /* RF control (RX gain 3) */
#define BWN_NPHY_RFCTL_TXG3 BWN_PHY_N(0x082) /* RF control (TX gain 3) */
#define BWN_NPHY_RFCTL_RSSIO4 BWN_PHY_N(0x083) /* RF control (RSSI others 4) */
#define BWN_NPHY_RFCTL_RSSIO4_RXPD 0x0001 /* RX PD */
#define BWN_NPHY_RFCTL_RSSIO4_TXPD 0x0002 /* TX PD */
#define BWN_NPHY_RFCTL_RSSIO4_PAPD 0x0004 /* PA PD */
#define BWN_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */
#define BWN_NPHY_RFCTL_RSSIO4_LPFBW 0x00C0 /* LPF bandwidth */
#define BWN_NPHY_RFCTL_RSSIO4_HPFBWHI 0x0100 /* HPF bandwidth high */
#define BWN_NPHY_RFCTL_RSSIO4_HIQDISCO 0x0200 /* HIQ dis core */
#define BWN_NPHY_RFCTL_RXG4 BWN_PHY_N(0x084) /* RF control (RX gain 4) */
#define BWN_NPHY_RFCTL_TXG4 BWN_PHY_N(0x085) /* RF control (TX gain 4) */
#define BWN_NPHY_C1_TXIQ_COMP_OFF BWN_PHY_N(0x087) /* Core 1 TX I/Q comp offset */
#define BWN_NPHY_C2_TXIQ_COMP_OFF BWN_PHY_N(0x088) /* Core 2 TX I/Q comp offset */
#define BWN_NPHY_C1_TXCTL BWN_PHY_N(0x08B) /* Core 1 TX control */
#define BWN_NPHY_C2_TXCTL BWN_PHY_N(0x08C) /* Core 2 TX control */
#define BWN_NPHY_AFECTL_OVER1 BWN_PHY_N(0x08F) /* AFE control override 1 */
#define BWN_NPHY_SCRAM_SIGCTL BWN_PHY_N(0x090) /* Scram signal control */
#define BWN_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */
#define BWN_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0
#define BWN_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */
#define BWN_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */
#define BWN_NPHY_SCRAM_SIGCTL_START 0xFE00 /* Scram start bit */
#define BWN_NPHY_SCRAM_SIGCTL_START_SHIFT 9
#define BWN_NPHY_RFCTL_INTC1 BWN_PHY_N(0x091) /* RF control (intc 1) */
#define BWN_NPHY_RFCTL_INTC2 BWN_PHY_N(0x092) /* RF control (intc 2) */
#define BWN_NPHY_RFCTL_INTC3 BWN_PHY_N(0x093) /* RF control (intc 3) */
#define BWN_NPHY_RFCTL_INTC4 BWN_PHY_N(0x094) /* RF control (intc 4) */
#define BWN_NPHY_NRDTO_WWISE BWN_PHY_N(0x095) /* # datatones WWiSE */
#define BWN_NPHY_NRDTO_TGNSYNC BWN_PHY_N(0x096) /* # datatones TGNsync */
#define BWN_NPHY_SIGFMOD_WWISE BWN_PHY_N(0x097) /* Signal field mod WWiSE */
#define BWN_NPHY_LEG_SIGFMOD_11N BWN_PHY_N(0x098) /* Legacy signal field mod 11n */
#define BWN_NPHY_HT_SIGFMOD_11N BWN_PHY_N(0x099) /* HT signal field mod 11n */
#define BWN_NPHY_C1_RXIQ_COMPA0 BWN_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */
#define BWN_NPHY_C1_RXIQ_COMPB0 BWN_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */
#define BWN_NPHY_C2_RXIQ_COMPA1 BWN_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */
#define BWN_NPHY_C2_RXIQ_COMPB1 BWN_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */
#define BWN_NPHY_RXCTL BWN_PHY_N(0x0A0) /* RX control */
#define BWN_NPHY_RXCTL_BSELU20 0x0010 /* Band select upper 20 */
#define BWN_NPHY_RXCTL_RIFSEN 0x0080 /* RIFS enable */
#define BWN_NPHY_RFSEQMODE BWN_PHY_N(0x0A1) /* RF seq mode */
#define BWN_NPHY_RFSEQMODE_CAOVER 0x0001 /* Core active override */
#define BWN_NPHY_RFSEQMODE_TROVER 0x0002 /* Trigger override */
#define BWN_NPHY_RFSEQCA BWN_PHY_N(0x0A2) /* RF seq core active */
#define BWN_NPHY_RFSEQCA_TXEN 0x000F /* TX enable */
#define BWN_NPHY_RFSEQCA_TXEN_SHIFT 0
#define BWN_NPHY_RFSEQCA_RXEN 0x00F0 /* RX enable */
#define BWN_NPHY_RFSEQCA_RXEN_SHIFT 4
#define BWN_NPHY_RFSEQCA_TXDIS 0x0F00 /* TX disable */
#define BWN_NPHY_RFSEQCA_TXDIS_SHIFT 8
#define BWN_NPHY_RFSEQCA_RXDIS 0xF000 /* RX disable */
#define BWN_NPHY_RFSEQCA_RXDIS_SHIFT 12
#define BWN_NPHY_RFSEQTR BWN_PHY_N(0x0A3) /* RF seq trigger */
#define BWN_NPHY_RFSEQTR_RX2TX 0x0001 /* RX2TX */
#define BWN_NPHY_RFSEQTR_TX2RX 0x0002 /* TX2RX */
#define BWN_NPHY_RFSEQTR_UPGH 0x0004 /* Update gain H */
#define BWN_NPHY_RFSEQTR_UPGL 0x0008 /* Update gain L */
#define BWN_NPHY_RFSEQTR_UPGU 0x0010 /* Update gain U */
#define BWN_NPHY_RFSEQTR_RST2RX 0x0020 /* Reset to RX */
#define BWN_NPHY_RFSEQST BWN_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */
#define BWN_NPHY_AFECTL_OVER BWN_PHY_N(0x0A5) /* AFE control override */
#define BWN_NPHY_AFECTL_C1 BWN_PHY_N(0x0A6) /* AFE control core 1 */
#define BWN_NPHY_AFECTL_C2 BWN_PHY_N(0x0A7) /* AFE control core 2 */
#define BWN_NPHY_AFECTL_C3 BWN_PHY_N(0x0A8) /* AFE control core 3 */
#define BWN_NPHY_AFECTL_C4 BWN_PHY_N(0x0A9) /* AFE control core 4 */
#define BWN_NPHY_AFECTL_DACGAIN1 BWN_PHY_N(0x0AA) /* AFE control DAC gain 1 */
#define BWN_NPHY_AFECTL_DACGAIN2 BWN_PHY_N(0x0AB) /* AFE control DAC gain 2 */
#define BWN_NPHY_AFECTL_DACGAIN3 BWN_PHY_N(0x0AC) /* AFE control DAC gain 3 */
#define BWN_NPHY_AFECTL_DACGAIN4 BWN_PHY_N(0x0AD) /* AFE control DAC gain 4 */
#define BWN_NPHY_STR_ADDR1 BWN_PHY_N(0x0AE) /* STR address 1 */
#define BWN_NPHY_STR_ADDR2 BWN_PHY_N(0x0AF) /* STR address 2 */
#define BWN_NPHY_CLASSCTL BWN_PHY_N(0x0B0) /* Classifier control */
#define BWN_NPHY_CLASSCTL_CCKEN 0x0001 /* CCK enable */
#define BWN_NPHY_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */
#define BWN_NPHY_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */
#define BWN_NPHY_IQFLIP BWN_PHY_N(0x0B1) /* I/Q flip */
#define BWN_NPHY_IQFLIP_ADC1 0x0001 /* ADC1 */
#define BWN_NPHY_IQFLIP_ADC2 0x0010 /* ADC2 */
#define BWN_NPHY_SISO_SNR_THRES BWN_PHY_N(0x0B2) /* SISO SNR threshold */
#define BWN_NPHY_SIGMA_N_MULT BWN_PHY_N(0x0B3) /* Sigma N multiplier */
#define BWN_NPHY_TXMACDELAY BWN_PHY_N(0x0B4) /* TX MAC delay */
#define BWN_NPHY_TXFRAMEDELAY BWN_PHY_N(0x0B5) /* TX frame delay */
#define BWN_NPHY_MLPARM BWN_PHY_N(0x0B6) /* ML parameters */
#define BWN_NPHY_MLCTL BWN_PHY_N(0x0B7) /* ML control */
#define BWN_NPHY_WWISE_20NCYCDAT BWN_PHY_N(0x0B8) /* WWiSE 20 N cyc data */
#define BWN_NPHY_WWISE_40NCYCDAT BWN_PHY_N(0x0B9) /* WWiSE 40 N cyc data */
#define BWN_NPHY_TGNSYNC_20NCYCDAT BWN_PHY_N(0x0BA) /* TGNsync 20 N cyc data */
#define BWN_NPHY_TGNSYNC_40NCYCDAT BWN_PHY_N(0x0BB) /* TGNsync 40 N cyc data */
#define BWN_NPHY_INITSWIZP BWN_PHY_N(0x0BC) /* Initial swizzle pattern */
#define BWN_NPHY_TXTAILCNT BWN_PHY_N(0x0BD) /* TX tail count value */
#define BWN_NPHY_BPHY_CTL1 BWN_PHY_N(0x0BE) /* B PHY control 1 */
#define BWN_NPHY_BPHY_CTL2 BWN_PHY_N(0x0BF) /* B PHY control 2 */
#define BWN_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */
#define BWN_NPHY_BPHY_CTL2_LUT_SHIFT 0
#define BWN_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */
#define BWN_NPHY_BPHY_CTL2_MACDEL_SHIFT 5
#define BWN_NPHY_IQLOCAL_CMD BWN_PHY_N(0x0C0) /* I/Q LO cal command */
#define BWN_NPHY_IQLOCAL_CMD_EN 0x8000
#define BWN_NPHY_IQLOCAL_CMDNNUM BWN_PHY_N(0x0C1) /* I/Q LO cal command N num */
#define BWN_NPHY_IQLOCAL_CMDGCTL BWN_PHY_N(0x0C2) /* I/Q LO cal command G control */
#define BWN_NPHY_SAMP_CMD BWN_PHY_N(0x0C3) /* Sample command */
#define BWN_NPHY_SAMP_CMD_STOP 0x0002 /* Stop */
#define BWN_NPHY_SAMP_LOOPCNT BWN_PHY_N(0x0C4) /* Sample loop count */
#define BWN_NPHY_SAMP_WAITCNT BWN_PHY_N(0x0C5) /* Sample wait count */
#define BWN_NPHY_SAMP_DEPCNT BWN_PHY_N(0x0C6) /* Sample depth count */
#define BWN_NPHY_SAMP_STAT BWN_PHY_N(0x0C7) /* Sample status */
#define BWN_NPHY_GPIO_LOOEN BWN_PHY_N(0x0C8) /* GPIO low out enable */
#define BWN_NPHY_GPIO_HIOEN BWN_PHY_N(0x0C9) /* GPIO high out enable */
#define BWN_NPHY_GPIO_SEL BWN_PHY_N(0x0CA) /* GPIO select */
#define BWN_NPHY_GPIO_CLKCTL BWN_PHY_N(0x0CB) /* GPIO clock control */
#define BWN_NPHY_TXF_20CO_AS0 BWN_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */
#define BWN_NPHY_TXF_20CO_AS1 BWN_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */
#define BWN_NPHY_TXF_20CO_AS2 BWN_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */
#define BWN_NPHY_TXF_20CO_B32S0 BWN_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */
#define BWN_NPHY_TXF_20CO_B1S0 BWN_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */
#define BWN_NPHY_TXF_20CO_B32S1 BWN_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */
#define BWN_NPHY_TXF_20CO_B1S1 BWN_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */
#define BWN_NPHY_TXF_20CO_B32S2 BWN_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */
#define BWN_NPHY_TXF_20CO_B1S2 BWN_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */
#define BWN_NPHY_SIGFLDTOL BWN_PHY_N(0x0D5) /* Signal fld tolerance */
#define BWN_NPHY_TXSERFLD BWN_PHY_N(0x0D6) /* TX service field */
#define BWN_NPHY_AFESEQ_RX2TX_PUD BWN_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */
#define BWN_NPHY_AFESEQ_TX2RX_PUD BWN_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */
#define BWN_NPHY_TGNSYNC_SCRAMI0 BWN_PHY_N(0x0D9) /* TGNsync scram init 0 */
#define BWN_NPHY_TGNSYNC_SCRAMI1 BWN_PHY_N(0x0DA) /* TGNsync scram init 1 */
#define BWN_NPHY_INITSWIZPATTLEG BWN_PHY_N(0x0DB) /* Initial swizzle pattern leg */
#define BWN_NPHY_BPHY_CTL3 BWN_PHY_N(0x0DC) /* B PHY control 3 */
#define BWN_NPHY_BPHY_CTL3_SCALE 0x00FF /* Scale */
#define BWN_NPHY_BPHY_CTL3_SCALE_SHIFT 0
#define BWN_NPHY_BPHY_CTL3_FSC 0xFF00 /* Frame start count value */
#define BWN_NPHY_BPHY_CTL3_FSC_SHIFT 8
#define BWN_NPHY_BPHY_CTL4 BWN_PHY_N(0x0DD) /* B PHY control 4 */
#define BWN_NPHY_C1_TXBBMULT BWN_PHY_N(0x0DE) /* Core 1 TX BB multiplier */
#define BWN_NPHY_C2_TXBBMULT BWN_PHY_N(0x0DF) /* Core 2 TX BB multiplier */
#define BWN_NPHY_TXF_40CO_AS0 BWN_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */
#define BWN_NPHY_TXF_40CO_AS1 BWN_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */
#define BWN_NPHY_TXF_40CO_AS2 BWN_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */
#define BWN_NPHY_TXF_40CO_B32S0 BWN_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */
#define BWN_NPHY_TXF_40CO_B1S0 BWN_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */
#define BWN_NPHY_TXF_40CO_B32S1 BWN_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */
#define BWN_NPHY_TXF_40CO_B1S1 BWN_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */
#define BWN_NPHY_REV3_RFCTL_OVER0 BWN_PHY_N(0x0E7)
#define BWN_NPHY_TXF_40CO_B32S2 BWN_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */
#define BWN_NPHY_TXF_40CO_B1S2 BWN_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */
#define BWN_NPHY_BIST_STAT2 BWN_PHY_N(0x0EA) /* BIST status 2 */
#define BWN_NPHY_BIST_STAT3 BWN_PHY_N(0x0EB) /* BIST status 3 */
#define BWN_NPHY_RFCTL_OVER BWN_PHY_N(0x0EC) /* RF control override */
#define BWN_NPHY_REV3_RFCTL_OVER1 BWN_PHY_N(0x0EC)
#define BWN_NPHY_MIMOCFG BWN_PHY_N(0x0ED) /* MIMO config */
#define BWN_NPHY_MIMOCFG_GFMIX 0x0004 /* Greenfield or mixed mode */
#define BWN_NPHY_MIMOCFG_AUTO 0x0100 /* Greenfield/mixed mode auto */
#define BWN_NPHY_RADAR_BLNKCTL BWN_PHY_N(0x0EE) /* Radar blank control */
#define BWN_NPHY_A0RADAR_FIFOCTL BWN_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */
#define BWN_NPHY_A1RADAR_FIFOCTL BWN_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */
#define BWN_NPHY_A0RADAR_FIFODAT BWN_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */
#define BWN_NPHY_A1RADAR_FIFODAT BWN_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */
#define BWN_NPHY_RADAR_THRES0 BWN_PHY_N(0x0F3) /* Radar threshold 0 */
#define BWN_NPHY_RADAR_THRES1 BWN_PHY_N(0x0F4) /* Radar threshold 1 */
#define BWN_NPHY_RADAR_THRES0R BWN_PHY_N(0x0F5) /* Radar threshold 0R */
#define BWN_NPHY_RADAR_THRES1R BWN_PHY_N(0x0F6) /* Radar threshold 1R */
#define BWN_NPHY_CSEN_20IN40_DLEN BWN_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */
#define BWN_NPHY_RFCTL_LUT_TRSW_LO1 BWN_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */
#define BWN_NPHY_RFCTL_LUT_TRSW_UP1 BWN_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */
#define BWN_NPHY_RFCTL_LUT_TRSW_LO2 BWN_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */
#define BWN_NPHY_RFCTL_LUT_TRSW_UP2 BWN_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */
#define BWN_NPHY_RFCTL_LUT_TRSW_LO3 BWN_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */
#define BWN_NPHY_RFCTL_LUT_TRSW_UP3 BWN_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */
#define BWN_NPHY_RFCTL_LUT_TRSW_LO4 BWN_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */
#define BWN_NPHY_RFCTL_LUT_TRSW_UP4 BWN_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */
#define BWN_NPHY_RFCTL_LUT_LNAPA1 BWN_PHY_N(0x100) /* RF control LUT LNA PA 1 */
#define BWN_NPHY_RFCTL_LUT_LNAPA2 BWN_PHY_N(0x101) /* RF control LUT LNA PA 2 */
#define BWN_NPHY_RFCTL_LUT_LNAPA3 BWN_PHY_N(0x102) /* RF control LUT LNA PA 3 */
#define BWN_NPHY_RFCTL_LUT_LNAPA4 BWN_PHY_N(0x103) /* RF control LUT LNA PA 4 */
#define BWN_NPHY_TGNSYNC_CRCM0 BWN_PHY_N(0x104) /* TGNsync CRC mask 0 */
#define BWN_NPHY_TGNSYNC_CRCM1 BWN_PHY_N(0x105) /* TGNsync CRC mask 1 */
#define BWN_NPHY_TGNSYNC_CRCM2 BWN_PHY_N(0x106) /* TGNsync CRC mask 2 */
#define BWN_NPHY_TGNSYNC_CRCM3 BWN_PHY_N(0x107) /* TGNsync CRC mask 3 */
#define BWN_NPHY_TGNSYNC_CRCM4 BWN_PHY_N(0x108) /* TGNsync CRC mask 4 */
#define BWN_NPHY_CRCPOLY BWN_PHY_N(0x109) /* CRC polynomial */
#define BWN_NPHY_SIGCNT BWN_PHY_N(0x10A) /* # sig count */
#define BWN_NPHY_SIGSTARTBIT_CTL BWN_PHY_N(0x10B) /* Sig start bit control */
#define BWN_NPHY_CRCPOLY_ORDER BWN_PHY_N(0x10C) /* CRC polynomial order */
#define BWN_NPHY_RFCTL_CST0 BWN_PHY_N(0x10D) /* RF control core swap table 0 */
#define BWN_NPHY_RFCTL_CST1 BWN_PHY_N(0x10E) /* RF control core swap table 1 */
#define BWN_NPHY_RFCTL_CST2O BWN_PHY_N(0x10F) /* RF control core swap table 2 + others */
#define BWN_NPHY_BPHY_CTL5 BWN_PHY_N(0x111) /* B PHY control 5 */
#define BWN_NPHY_RFSEQ_LPFBW BWN_PHY_N(0x112) /* RF seq LPF bandwidth */
#define BWN_NPHY_TSSIBIAS1 BWN_PHY_N(0x114) /* TSSI bias val 1 */
#define BWN_NPHY_TSSIBIAS2 BWN_PHY_N(0x115) /* TSSI bias val 2 */
#define BWN_NPHY_TSSIBIAS_BIAS 0x00FF /* Bias */
#define BWN_NPHY_TSSIBIAS_BIAS_SHIFT 0
#define BWN_NPHY_TSSIBIAS_VAL 0xFF00 /* Value */
#define BWN_NPHY_TSSIBIAS_VAL_SHIFT 8
#define BWN_NPHY_ESTPWR1 BWN_PHY_N(0x118) /* Estimated power 1 */
#define BWN_NPHY_ESTPWR2 BWN_PHY_N(0x119) /* Estimated power 2 */
#define BWN_NPHY_ESTPWR_PWR 0x00FF /* Estimated power */
#define BWN_NPHY_ESTPWR_PWR_SHIFT 0
#define BWN_NPHY_ESTPWR_VALID 0x0100 /* Estimated power valid */
#define BWN_NPHY_TSSI_MAXTXFDT BWN_PHY_N(0x11C) /* TSSI max TX frame delay time */
#define BWN_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */
#define BWN_NPHY_TSSI_MAXTXFDT_VAL_SHIFT 0
#define BWN_NPHY_TSSI_MAXTDT BWN_PHY_N(0x11D) /* TSSI max TSSI delay time */
#define BWN_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */
#define BWN_NPHY_TSSI_MAXTDT_VAL_SHIFT 0
#define BWN_NPHY_ITSSI1 BWN_PHY_N(0x11E) /* TSSI idle 1 */
#define BWN_NPHY_ITSSI2 BWN_PHY_N(0x11F) /* TSSI idle 2 */
#define BWN_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */
#define BWN_NPHY_ITSSI_VAL_SHIFT 0
#define BWN_NPHY_TSSIMODE BWN_PHY_N(0x122) /* TSSI mode */
#define BWN_NPHY_TSSIMODE_EN 0x0001 /* TSSI enable */
#define BWN_NPHY_TSSIMODE_PDEN 0x0002 /* Power det enable */
#define BWN_NPHY_RXMACIFM BWN_PHY_N(0x123) /* RX Macif mode */
#define BWN_NPHY_CRSIT_COCNT_LO BWN_PHY_N(0x124) /* CRS idle time CRS-on count (low) */
#define BWN_NPHY_CRSIT_COCNT_HI BWN_PHY_N(0x125) /* CRS idle time CRS-on count (high) */
#define BWN_NPHY_CRSIT_MTCNT_LO BWN_PHY_N(0x126) /* CRS idle time measure time count (low) */
#define BWN_NPHY_CRSIT_MTCNT_HI BWN_PHY_N(0x127) /* CRS idle time measure time count (high) */
#define BWN_NPHY_SAMTWC BWN_PHY_N(0x128) /* Sample tail wait count */
#define BWN_NPHY_IQEST_CMD BWN_PHY_N(0x129) /* I/Q estimate command */
#define BWN_NPHY_IQEST_CMD_START 0x0001 /* Start */
#define BWN_NPHY_IQEST_CMD_MODE 0x0002 /* Mode */
#define BWN_NPHY_IQEST_WT BWN_PHY_N(0x12A) /* I/Q estimate wait time */
#define BWN_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */
#define BWN_NPHY_IQEST_WT_VAL_SHIFT 0
#define BWN_NPHY_IQEST_SAMCNT BWN_PHY_N(0x12B) /* I/Q estimate sample count */
#define BWN_NPHY_IQEST_IQACC_LO0 BWN_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */
#define BWN_NPHY_IQEST_IQACC_HI0 BWN_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */
#define BWN_NPHY_IQEST_IPACC_LO0 BWN_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */
#define BWN_NPHY_IQEST_IPACC_HI0 BWN_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */
#define BWN_NPHY_IQEST_QPACC_LO0 BWN_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */
#define BWN_NPHY_IQEST_QPACC_HI0 BWN_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */
#define BWN_NPHY_IQEST_IQACC_LO1 BWN_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */
#define BWN_NPHY_IQEST_IQACC_HI1 BWN_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */
#define BWN_NPHY_IQEST_IPACC_LO1 BWN_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */
#define BWN_NPHY_IQEST_IPACC_HI1 BWN_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */
#define BWN_NPHY_IQEST_QPACC_LO1 BWN_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */
#define BWN_NPHY_IQEST_QPACC_HI1 BWN_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */
#define BWN_NPHY_MIMO_CRSTXEXT BWN_PHY_N(0x13A) /* MIMO PHY CRS TX extension */
#define BWN_NPHY_PWRDET1 BWN_PHY_N(0x13B) /* Power det 1 */
#define BWN_NPHY_PWRDET2 BWN_PHY_N(0x13C) /* Power det 2 */
#define BWN_NPHY_MAXRSSI_DTIME BWN_PHY_N(0x13F) /* RSSI max RSSI delay time */
#define BWN_NPHY_PIL_DW0 BWN_PHY_N(0x141) /* Pilot data weight 0 */
#define BWN_NPHY_PIL_DW1 BWN_PHY_N(0x142) /* Pilot data weight 1 */
#define BWN_NPHY_PIL_DW2 BWN_PHY_N(0x143) /* Pilot data weight 2 */
#define BWN_NPHY_PIL_DW_BPSK 0x000F /* BPSK */
#define BWN_NPHY_PIL_DW_BPSK_SHIFT 0
#define BWN_NPHY_PIL_DW_QPSK 0x00F0 /* QPSK */
#define BWN_NPHY_PIL_DW_QPSK_SHIFT 4
#define BWN_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */
#define BWN_NPHY_PIL_DW_16QAM_SHIFT 8
#define BWN_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */
#define BWN_NPHY_PIL_DW_64QAM_SHIFT 12
#define BWN_NPHY_FMDEM_CFG BWN_PHY_N(0x144) /* FM demodulation config */
#define BWN_NPHY_PHASETR_A0 BWN_PHY_N(0x145) /* Phase track alpha 0 */
#define BWN_NPHY_PHASETR_A1 BWN_PHY_N(0x146) /* Phase track alpha 1 */
#define BWN_NPHY_PHASETR_A2 BWN_PHY_N(0x147) /* Phase track alpha 2 */
#define BWN_NPHY_PHASETR_B0 BWN_PHY_N(0x148) /* Phase track beta 0 */
#define BWN_NPHY_PHASETR_B1 BWN_PHY_N(0x149) /* Phase track beta 1 */
#define BWN_NPHY_PHASETR_B2 BWN_PHY_N(0x14A) /* Phase track beta 2 */
#define BWN_NPHY_PHASETR_CHG0 BWN_PHY_N(0x14B) /* Phase track change 0 */
#define BWN_NPHY_PHASETR_CHG1 BWN_PHY_N(0x14C) /* Phase track change 1 */
#define BWN_NPHY_PHASETW_OFF BWN_PHY_N(0x14D) /* Phase track offset */
#define BWN_NPHY_RFCTL_DBG BWN_PHY_N(0x14E) /* RF control debug */
#define BWN_NPHY_CCK_SHIFTB_REF BWN_PHY_N(0x150) /* CCK shiftbits reference var */
#define BWN_NPHY_OVER_DGAIN0 BWN_PHY_N(0x152) /* Override digital gain 0 */
#define BWN_NPHY_OVER_DGAIN1 BWN_PHY_N(0x153) /* Override digital gain 1 */
#define BWN_NPHY_OVER_DGAIN_FDGV 0x0007 /* Force digital gain value */
#define BWN_NPHY_OVER_DGAIN_FDGV_SHIFT 0
#define BWN_NPHY_OVER_DGAIN_FDGEN 0x0008 /* Force digital gain enable */
#define BWN_NPHY_OVER_DGAIN_CCKDGECV 0xFF00 /* CCK digital gain enable count value */
#define BWN_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8
#define BWN_NPHY_BIST_STAT4 BWN_PHY_N(0x156) /* BIST status 4 */
#define BWN_NPHY_RADAR_MAL BWN_PHY_N(0x157) /* Radar MA length */
#define BWN_NPHY_RADAR_SRCCTL BWN_PHY_N(0x158) /* Radar search control */
#define BWN_NPHY_VLD_DTSIG BWN_PHY_N(0x159) /* VLD data tones sig */
#define BWN_NPHY_VLD_DTDAT BWN_PHY_N(0x15A) /* VLD data tones data */
#define BWN_NPHY_C1_BPHY_RXIQCA0 BWN_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */
#define BWN_NPHY_C1_BPHY_RXIQCB0 BWN_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */
#define BWN_NPHY_C2_BPHY_RXIQCA1 BWN_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */
#define BWN_NPHY_C2_BPHY_RXIQCB1 BWN_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */
#define BWN_NPHY_FREQGAIN0 BWN_PHY_N(0x160) /* Frequency gain 0 */
#define BWN_NPHY_FREQGAIN1 BWN_PHY_N(0x161) /* Frequency gain 1 */
#define BWN_NPHY_FREQGAIN2 BWN_PHY_N(0x162) /* Frequency gain 2 */
#define BWN_NPHY_FREQGAIN3 BWN_PHY_N(0x163) /* Frequency gain 3 */
#define BWN_NPHY_FREQGAIN4 BWN_PHY_N(0x164) /* Frequency gain 4 */
#define BWN_NPHY_FREQGAIN5 BWN_PHY_N(0x165) /* Frequency gain 5 */
#define BWN_NPHY_FREQGAIN6 BWN_PHY_N(0x166) /* Frequency gain 6 */
#define BWN_NPHY_FREQGAIN7 BWN_PHY_N(0x167) /* Frequency gain 7 */
#define BWN_NPHY_FREQGAIN_BYPASS BWN_PHY_N(0x168) /* Frequency gain bypass */
#define BWN_NPHY_TRLOSS BWN_PHY_N(0x169) /* TR loss value */
#define BWN_NPHY_C1_ADCCLIP BWN_PHY_N(0x16A) /* Core 1 ADC clip */
#define BWN_NPHY_C2_ADCCLIP BWN_PHY_N(0x16B) /* Core 2 ADC clip */
#define BWN_NPHY_LTRN_OFFGAIN BWN_PHY_N(0x16F) /* LTRN offset gain */
#define BWN_NPHY_LTRN_OFF BWN_PHY_N(0x170) /* LTRN offset */
#define BWN_NPHY_NRDATAT_WWISE20SIG BWN_PHY_N(0x171) /* # data tones WWiSE 20 sig */
#define BWN_NPHY_NRDATAT_WWISE40SIG BWN_PHY_N(0x172) /* # data tones WWiSE 40 sig */
#define BWN_NPHY_NRDATAT_TGNSYNC20SIG BWN_PHY_N(0x173) /* # data tones TGNsync 20 sig */
#define BWN_NPHY_NRDATAT_TGNSYNC40SIG BWN_PHY_N(0x174) /* # data tones TGNsync 40 sig */
#define BWN_NPHY_WWISE_CRCM0 BWN_PHY_N(0x175) /* WWiSE CRC mask 0 */
#define BWN_NPHY_WWISE_CRCM1 BWN_PHY_N(0x176) /* WWiSE CRC mask 1 */
#define BWN_NPHY_WWISE_CRCM2 BWN_PHY_N(0x177) /* WWiSE CRC mask 2 */
#define BWN_NPHY_WWISE_CRCM3 BWN_PHY_N(0x178) /* WWiSE CRC mask 3 */
#define BWN_NPHY_WWISE_CRCM4 BWN_PHY_N(0x179) /* WWiSE CRC mask 4 */
#define BWN_NPHY_CHANEST_CDDSH BWN_PHY_N(0x17A) /* Channel estimate CDD shift */
#define BWN_NPHY_HTAGC_WCNT BWN_PHY_N(0x17B) /* HT ADC wait counters */
#define BWN_NPHY_SQPARM BWN_PHY_N(0x17C) /* SQ params */
#define BWN_NPHY_MCSDUP6M BWN_PHY_N(0x17D) /* MCS dup 6M */
#define BWN_NPHY_NDATAT_DUP40 BWN_PHY_N(0x17E) /* # data tones dup 40 */
#define BWN_NPHY_DUP40_TGNSYNC_CYCD BWN_PHY_N(0x17F) /* Dup40 TGNsync cycle data */
#define BWN_NPHY_DUP40_GFBL BWN_PHY_N(0x180) /* Dup40 GF format BL address */
#define BWN_NPHY_DUP40_BL BWN_PHY_N(0x181) /* Dup40 format BL address */
#define BWN_NPHY_LEGDUP_FTA BWN_PHY_N(0x182) /* Legacy dup frm table address */
#define BWN_NPHY_PACPROC_DBG BWN_PHY_N(0x183) /* Packet processing debug */
#define BWN_NPHY_PIL_CYC1 BWN_PHY_N(0x184) /* Pilot cycle counter 1 */
#define BWN_NPHY_PIL_CYC2 BWN_PHY_N(0x185) /* Pilot cycle counter 2 */
#define BWN_NPHY_TXF_20CO_S0A1 BWN_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */
#define BWN_NPHY_TXF_20CO_S0A2 BWN_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */
#define BWN_NPHY_TXF_20CO_S1A1 BWN_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */
#define BWN_NPHY_TXF_20CO_S1A2 BWN_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */
#define BWN_NPHY_TXF_20CO_S2A1 BWN_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */
#define BWN_NPHY_TXF_20CO_S2A2 BWN_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */
#define BWN_NPHY_TXF_20CO_S0B1 BWN_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */
#define BWN_NPHY_TXF_20CO_S0B2 BWN_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */
#define BWN_NPHY_TXF_20CO_S0B3 BWN_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */
#define BWN_NPHY_TXF_20CO_S1B1 BWN_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */
#define BWN_NPHY_TXF_20CO_S1B2 BWN_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */
#define BWN_NPHY_TXF_20CO_S1B3 BWN_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */
#define BWN_NPHY_TXF_20CO_S2B1 BWN_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */
#define BWN_NPHY_TXF_20CO_S2B2 BWN_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */
#define BWN_NPHY_TXF_20CO_S2B3 BWN_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */
#define BWN_NPHY_TXF_40CO_S0A1 BWN_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */
#define BWN_NPHY_TXF_40CO_S0A2 BWN_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */
#define BWN_NPHY_TXF_40CO_S1A1 BWN_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */
#define BWN_NPHY_TXF_40CO_S1A2 BWN_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */
#define BWN_NPHY_TXF_40CO_S2A1 BWN_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */
#define BWN_NPHY_TXF_40CO_S2A2 BWN_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */
#define BWN_NPHY_TXF_40CO_S0B1 BWN_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */
#define BWN_NPHY_TXF_40CO_S0B2 BWN_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */
#define BWN_NPHY_TXF_40CO_S0B3 BWN_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */
#define BWN_NPHY_TXF_40CO_S1B1 BWN_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */
#define BWN_NPHY_TXF_40CO_S1B2 BWN_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */
#define BWN_NPHY_TXF_40CO_S1B3 BWN_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */
#define BWN_NPHY_TXF_40CO_S2B1 BWN_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */
#define BWN_NPHY_TXF_40CO_S2B2 BWN_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */
#define BWN_NPHY_TXF_40CO_S2B3 BWN_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */
#define BWN_NPHY_RSSIMC_0I_RSSI_X BWN_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */
#define BWN_NPHY_RSSIMC_0I_RSSI_Y BWN_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */
#define BWN_NPHY_RSSIMC_0I_RSSI_Z BWN_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */
#define BWN_NPHY_RSSIMC_0I_TBD BWN_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */
#define BWN_NPHY_RSSIMC_0I_PWRDET BWN_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */
#define BWN_NPHY_RSSIMC_0I_TSSI BWN_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */
#define BWN_NPHY_RSSIMC_0Q_RSSI_X BWN_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */
#define BWN_NPHY_RSSIMC_0Q_RSSI_Y BWN_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */
#define BWN_NPHY_RSSIMC_0Q_RSSI_Z BWN_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */
#define BWN_NPHY_RSSIMC_0Q_TBD BWN_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */
#define BWN_NPHY_RSSIMC_0Q_PWRDET BWN_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */
#define BWN_NPHY_RSSIMC_0Q_TSSI BWN_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */
#define BWN_NPHY_RSSIMC_1I_RSSI_X BWN_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */
#define BWN_NPHY_RSSIMC_1I_RSSI_Y BWN_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */
#define BWN_NPHY_RSSIMC_1I_RSSI_Z BWN_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */
#define BWN_NPHY_RSSIMC_1I_TBD BWN_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */
#define BWN_NPHY_RSSIMC_1I_PWRDET BWN_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */
#define BWN_NPHY_RSSIMC_1I_TSSI BWN_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */
#define BWN_NPHY_RSSIMC_1Q_RSSI_X BWN_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */
#define BWN_NPHY_RSSIMC_1Q_RSSI_Y BWN_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */
#define BWN_NPHY_RSSIMC_1Q_RSSI_Z BWN_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */
#define BWN_NPHY_RSSIMC_1Q_TBD BWN_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */
#define BWN_NPHY_RSSIMC_1Q_PWRDET BWN_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */
#define BWN_NPHY_RSSIMC_1Q_TSSI BWN_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */
#define BWN_NPHY_SAMC_WCNT BWN_PHY_N(0x1BC) /* Sample collect wait counter */
#define BWN_NPHY_PTHROUGH_CNT BWN_PHY_N(0x1BD) /* Pass-through counter */
#define BWN_NPHY_LTRN_OFF_G20L BWN_PHY_N(0x1C4) /* LTRN offset gain 20L */
#define BWN_NPHY_LTRN_OFF_20L BWN_PHY_N(0x1C5) /* LTRN offset 20L */
#define BWN_NPHY_LTRN_OFF_G20U BWN_PHY_N(0x1C6) /* LTRN offset gain 20U */
#define BWN_NPHY_LTRN_OFF_20U BWN_PHY_N(0x1C7) /* LTRN offset 20U */
#define BWN_NPHY_DSSSCCK_GAINSL BWN_PHY_N(0x1C8) /* DSSS/CCK gain settle length */
#define BWN_NPHY_GPIO_LOOUT BWN_PHY_N(0x1C9) /* GPIO low out */
#define BWN_NPHY_GPIO_HIOUT BWN_PHY_N(0x1CA) /* GPIO high out */
#define BWN_NPHY_CRS_CHECK BWN_PHY_N(0x1CB) /* CRS check */
#define BWN_NPHY_ML_LOGSS_RAT BWN_PHY_N(0x1CC) /* ML/logss ratio */
#define BWN_NPHY_DUPSCALE BWN_PHY_N(0x1CD) /* Dup scale */
#define BWN_NPHY_BW1A BWN_PHY_N(0x1CE) /* BW 1A */
#define BWN_NPHY_BW2 BWN_PHY_N(0x1CF) /* BW 2 */
#define BWN_NPHY_BW3 BWN_PHY_N(0x1D0) /* BW 3 */
#define BWN_NPHY_BW4 BWN_PHY_N(0x1D1) /* BW 4 */
#define BWN_NPHY_BW5 BWN_PHY_N(0x1D2) /* BW 5 */
#define BWN_NPHY_BW6 BWN_PHY_N(0x1D3) /* BW 6 */
#define BWN_NPHY_COALEN0 BWN_PHY_N(0x1D4) /* Coarse length 0 */
#define BWN_NPHY_COALEN1 BWN_PHY_N(0x1D5) /* Coarse length 1 */
#define BWN_NPHY_CRSTHRES_1U BWN_PHY_N(0x1D6) /* CRS threshold 1 U */
#define BWN_NPHY_CRSTHRES_2U BWN_PHY_N(0x1D7) /* CRS threshold 2 U */
#define BWN_NPHY_CRSTHRES_3U BWN_PHY_N(0x1D8) /* CRS threshold 3 U */
#define BWN_NPHY_CRSCTL_U BWN_PHY_N(0x1D9) /* CRS control U */
#define BWN_NPHY_CRSTHRES_1L BWN_PHY_N(0x1DA) /* CRS threshold 1 L */
#define BWN_NPHY_CRSTHRES_2L BWN_PHY_N(0x1DB) /* CRS threshold 2 L */
#define BWN_NPHY_CRSTHRES_3L BWN_PHY_N(0x1DC) /* CRS threshold 3 L */
#define BWN_NPHY_CRSCTL_L BWN_PHY_N(0x1DD) /* CRS control L */
#define BWN_NPHY_STRA_1U BWN_PHY_N(0x1DE) /* STR address 1 U */
#define BWN_NPHY_STRA_2U BWN_PHY_N(0x1DF) /* STR address 2 U */
#define BWN_NPHY_STRA_1L BWN_PHY_N(0x1E0) /* STR address 1 L */
#define BWN_NPHY_STRA_2L BWN_PHY_N(0x1E1) /* STR address 2 L */
#define BWN_NPHY_CRSCHECK1 BWN_PHY_N(0x1E2) /* CRS check 1 */
#define BWN_NPHY_CRSCHECK2 BWN_PHY_N(0x1E3) /* CRS check 2 */
#define BWN_NPHY_CRSCHECK3 BWN_PHY_N(0x1E4) /* CRS check 3 */
#define BWN_NPHY_JMPSTP0 BWN_PHY_N(0x1E5) /* Jump step 0 */
#define BWN_NPHY_JMPSTP1 BWN_PHY_N(0x1E6) /* Jump step 1 */
#define BWN_NPHY_TXPCTL_CMD BWN_PHY_N(0x1E7) /* TX power control command */
#define BWN_NPHY_TXPCTL_CMD_INIT 0x007F /* Init */
#define BWN_NPHY_TXPCTL_CMD_INIT_SHIFT 0
#define BWN_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */
#define BWN_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */
#define BWN_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */
#define BWN_NPHY_TXPCTL_N BWN_PHY_N(0x1E8) /* TX power control N num */
#define BWN_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */
#define BWN_NPHY_TXPCTL_N_TSSID_SHIFT 0
#define BWN_NPHY_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */
#define BWN_NPHY_TXPCTL_N_NPTIL2_SHIFT 8
#define BWN_NPHY_TXPCTL_ITSSI BWN_PHY_N(0x1E9) /* TX power control idle TSSI */
#define BWN_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */
#define BWN_NPHY_TXPCTL_ITSSI_0_SHIFT 0
#define BWN_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */
#define BWN_NPHY_TXPCTL_ITSSI_1_SHIFT 8
#define BWN_NPHY_TXPCTL_ITSSI_BINF 0x8000 /* Raw TSSI offset bin format */
#define BWN_NPHY_TXPCTL_TPWR BWN_PHY_N(0x1EA) /* TX power control target power */
#define BWN_NPHY_TXPCTL_TPWR_0 0x00FF /* Power 0 */
#define BWN_NPHY_TXPCTL_TPWR_0_SHIFT 0
#define BWN_NPHY_TXPCTL_TPWR_1 0xFF00 /* Power 1 */
#define BWN_NPHY_TXPCTL_TPWR_1_SHIFT 8
#define BWN_NPHY_TXPCTL_BIDX BWN_PHY_N(0x1EB) /* TX power control base index */
#define BWN_NPHY_TXPCTL_BIDX_0 0x007F /* uC base index 0 */
#define BWN_NPHY_TXPCTL_BIDX_0_SHIFT 0
#define BWN_NPHY_TXPCTL_BIDX_1 0x7F00 /* uC base index 1 */
#define BWN_NPHY_TXPCTL_BIDX_1_SHIFT 8
#define BWN_NPHY_TXPCTL_BIDX_LOAD 0x8000 /* Load base index */
#define BWN_NPHY_TXPCTL_PIDX BWN_PHY_N(0x1EC) /* TX power control power index */
#define BWN_NPHY_TXPCTL_PIDX_0 0x007F /* uC power index 0 */
#define BWN_NPHY_TXPCTL_PIDX_0_SHIFT 0
#define BWN_NPHY_TXPCTL_PIDX_1 0x7F00 /* uC power index 1 */
#define BWN_NPHY_TXPCTL_PIDX_1_SHIFT 8
#define BWN_NPHY_C1_TXPCTL_STAT BWN_PHY_N(0x1ED) /* Core 1 TX power control status */
#define BWN_NPHY_C2_TXPCTL_STAT BWN_PHY_N(0x1EE) /* Core 2 TX power control status */
#define BWN_NPHY_TXPCTL_STAT_EST 0x00FF /* Estimated power */
#define BWN_NPHY_TXPCTL_STAT_EST_SHIFT 0
#define BWN_NPHY_TXPCTL_STAT_BIDX 0x7F00 /* Base index */
#define BWN_NPHY_TXPCTL_STAT_BIDX_SHIFT 8
#define BWN_NPHY_TXPCTL_STAT_ESTVALID 0x8000 /* Estimated power valid */
#define BWN_NPHY_SMALLSGS_LEN BWN_PHY_N(0x1EF) /* Small sig gain settle length */
#define BWN_NPHY_PHYSTAT_GAIN0 BWN_PHY_N(0x1F0) /* PHY stats gain info 0 */
#define BWN_NPHY_PHYSTAT_GAIN1 BWN_PHY_N(0x1F1) /* PHY stats gain info 1 */
#define BWN_NPHY_PHYSTAT_FREQEST BWN_PHY_N(0x1F2) /* PHY stats frequency estimate */
#define BWN_NPHY_PHYSTAT_ADVRET BWN_PHY_N(0x1F3) /* PHY stats ADV retard */
#define BWN_NPHY_PHYLB_MODE BWN_PHY_N(0x1F4) /* PHY loopback mode */
#define BWN_NPHY_TONE_MIDX20_1 BWN_PHY_N(0x1F5) /* Tone map index 20/1 */
#define BWN_NPHY_TONE_MIDX20_2 BWN_PHY_N(0x1F6) /* Tone map index 20/2 */
#define BWN_NPHY_TONE_MIDX20_3 BWN_PHY_N(0x1F7) /* Tone map index 20/3 */
#define BWN_NPHY_TONE_MIDX40_1 BWN_PHY_N(0x1F8) /* Tone map index 40/1 */
#define BWN_NPHY_TONE_MIDX40_2 BWN_PHY_N(0x1F9) /* Tone map index 40/2 */
#define BWN_NPHY_TONE_MIDX40_3 BWN_PHY_N(0x1FA) /* Tone map index 40/3 */
#define BWN_NPHY_TONE_MIDX40_4 BWN_PHY_N(0x1FB) /* Tone map index 40/4 */
#define BWN_NPHY_PILTONE_MIDX1 BWN_PHY_N(0x1FC) /* Pilot tone map index 1 */
#define BWN_NPHY_PILTONE_MIDX2 BWN_PHY_N(0x1FD) /* Pilot tone map index 2 */
#define BWN_NPHY_PILTONE_MIDX3 BWN_PHY_N(0x1FE) /* Pilot tone map index 3 */
#define BWN_NPHY_TXRIFS_FRDEL BWN_PHY_N(0x1FF) /* TX RIFS frame delay */
#define BWN_NPHY_AFESEQ_RX2TX_PUD_40M BWN_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */
#define BWN_NPHY_AFESEQ_TX2RX_PUD_40M BWN_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */
#define BWN_NPHY_AFESEQ_RX2TX_PUD_20M BWN_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */
#define BWN_NPHY_AFESEQ_TX2RX_PUD_20M BWN_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */
#define BWN_NPHY_RX_SIGCTL BWN_PHY_N(0x204) /* RX signal control */
#define BWN_NPHY_RXPIL_CYCNT0 BWN_PHY_N(0x205) /* RX pilot cycle counter 0 */
#define BWN_NPHY_RXPIL_CYCNT1 BWN_PHY_N(0x206) /* RX pilot cycle counter 1 */
#define BWN_NPHY_RXPIL_CYCNT2 BWN_PHY_N(0x207) /* RX pilot cycle counter 2 */
#define BWN_NPHY_AFESEQ_RX2TX_PUD_10M BWN_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */
#define BWN_NPHY_AFESEQ_TX2RX_PUD_10M BWN_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */
#define BWN_NPHY_DSSSCCK_CRSEXTL BWN_PHY_N(0x20A) /* DSSS/CCK CRS extension length */
#define BWN_NPHY_ML_LOGSS_RATSLOPE BWN_PHY_N(0x20B) /* ML/logss ratio slope */
#define BWN_NPHY_RIFS_SRCTL BWN_PHY_N(0x20C) /* RIFS search timeout length */
#define BWN_NPHY_TXREALFD BWN_PHY_N(0x20D) /* TX real frame delay */
#define BWN_NPHY_HPANT_SWTHRES BWN_PHY_N(0x20E) /* High power antenna switch threshold */
#define BWN_NPHY_EDCRS_ASSTHRES0 BWN_PHY_N(0x210) /* ED CRS assert threshold 0 */
#define BWN_NPHY_EDCRS_ASSTHRES1 BWN_PHY_N(0x211) /* ED CRS assert threshold 1 */
#define BWN_NPHY_EDCRS_DEASSTHRES0 BWN_PHY_N(0x212) /* ED CRS deassert threshold 0 */
#define BWN_NPHY_EDCRS_DEASSTHRES1 BWN_PHY_N(0x213) /* ED CRS deassert threshold 1 */
#define BWN_NPHY_STR_WTIME20U BWN_PHY_N(0x214) /* STR wait time 20U */
#define BWN_NPHY_STR_WTIME20L BWN_PHY_N(0x215) /* STR wait time 20L */
#define BWN_NPHY_TONE_MIDX657M BWN_PHY_N(0x216) /* Tone map index 657M */
#define BWN_NPHY_HTSIGTONES BWN_PHY_N(0x217) /* HT signal tones */
#define BWN_NPHY_RSSI1 BWN_PHY_N(0x219) /* RSSI value 1 */
#define BWN_NPHY_RSSI2 BWN_PHY_N(0x21A) /* RSSI value 2 */
#define BWN_NPHY_CHAN_ESTHANG BWN_PHY_N(0x21D) /* Channel estimate hang */
#define BWN_NPHY_FINERX2_CGC BWN_PHY_N(0x221) /* Fine RX 2 clock gate control */
#define BWN_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */
#define BWN_NPHY_TXPCTL_INIT BWN_PHY_N(0x222) /* TX power control init */
#define BWN_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
#define BWN_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
#define BWN_NPHY_ED_CRSEN BWN_PHY_N(0x223)
#define BWN_NPHY_ED_CRS40ASSERTTHRESH0 BWN_PHY_N(0x224)
#define BWN_NPHY_ED_CRS40ASSERTTHRESH1 BWN_PHY_N(0x225)
#define BWN_NPHY_ED_CRS40DEASSERTTHRESH0 BWN_PHY_N(0x226)
#define BWN_NPHY_ED_CRS40DEASSERTTHRESH1 BWN_PHY_N(0x227)
#define BWN_NPHY_ED_CRS20LASSERTTHRESH0 BWN_PHY_N(0x228)
#define BWN_NPHY_ED_CRS20LASSERTTHRESH1 BWN_PHY_N(0x229)
#define BWN_NPHY_ED_CRS20LDEASSERTTHRESH0 BWN_PHY_N(0x22A)
#define BWN_NPHY_ED_CRS20LDEASSERTTHRESH1 BWN_PHY_N(0x22B)
#define BWN_NPHY_ED_CRS20UASSERTTHRESH0 BWN_PHY_N(0x22C)
#define BWN_NPHY_ED_CRS20UASSERTTHRESH1 BWN_PHY_N(0x22D)
#define BWN_NPHY_ED_CRS20UDEASSERTTHRESH0 BWN_PHY_N(0x22E)
#define BWN_NPHY_ED_CRS20UDEASSERTTHRESH1 BWN_PHY_N(0x22F)
#define BWN_NPHY_ED_CRS BWN_PHY_N(0x230)
#define BWN_NPHY_TIMEOUTEN BWN_PHY_N(0x231)
#define BWN_NPHY_OFDMPAYDECODETIMEOUTLEN BWN_PHY_N(0x232)
#define BWN_NPHY_CCKPAYDECODETIMEOUTLEN BWN_PHY_N(0x233)
#define BWN_NPHY_NONPAYDECODETIMEOUTLEN BWN_PHY_N(0x234)
#define BWN_NPHY_TIMEOUTSTATUS BWN_PHY_N(0x235)
#define BWN_NPHY_RFCTRLCORE0GPIO0 BWN_PHY_N(0x236)
#define BWN_NPHY_RFCTRLCORE0GPIO1 BWN_PHY_N(0x237)
#define BWN_NPHY_RFCTRLCORE0GPIO2 BWN_PHY_N(0x238)
#define BWN_NPHY_RFCTRLCORE0GPIO3 BWN_PHY_N(0x239)
#define BWN_NPHY_RFCTRLCORE1GPIO0 BWN_PHY_N(0x23A)
#define BWN_NPHY_RFCTRLCORE1GPIO1 BWN_PHY_N(0x23B)
#define BWN_NPHY_RFCTRLCORE1GPIO2 BWN_PHY_N(0x23C)
#define BWN_NPHY_RFCTRLCORE1GPIO3 BWN_PHY_N(0x23D)
#define BWN_NPHY_BPHYTESTCONTROL BWN_PHY_N(0x23E)
/* REV3+ */
#define BWN_NPHY_FORCEFRONT0 BWN_PHY_N(0x23F)
#define BWN_NPHY_FORCEFRONT1 BWN_PHY_N(0x240)
#define BWN_NPHY_NORMVARHYSTTH BWN_PHY_N(0x241)
#define BWN_NPHY_TXCCKERROR BWN_PHY_N(0x242)
#define BWN_NPHY_AFESEQINITDACGAIN BWN_PHY_N(0x243)
#define BWN_NPHY_TXANTSWLUT BWN_PHY_N(0x244)
#define BWN_NPHY_CORECONFIG BWN_PHY_N(0x245)
#define BWN_NPHY_ANTENNADIVDWELLTIME BWN_PHY_N(0x246)
#define BWN_NPHY_ANTENNACCKDIVDWELLTIME BWN_PHY_N(0x247)
#define BWN_NPHY_ANTENNADIVBACKOFFGAIN BWN_PHY_N(0x248)
#define BWN_NPHY_ANTENNADIVMINGAIN BWN_PHY_N(0x249)
#define BWN_NPHY_BRDSEL_NORMVARHYSTTH BWN_PHY_N(0x24A)
#define BWN_NPHY_RXANTSWITCHCTRL BWN_PHY_N(0x24B)
#define BWN_NPHY_ENERGYDROPTIMEOUTLEN2 BWN_PHY_N(0x24C)
#define BWN_NPHY_ML_LOG_TXEVM0 BWN_PHY_N(0x250)
#define BWN_NPHY_ML_LOG_TXEVM1 BWN_PHY_N(0x251)
#define BWN_NPHY_ML_LOG_TXEVM2 BWN_PHY_N(0x252)
#define BWN_NPHY_ML_LOG_TXEVM3 BWN_PHY_N(0x253)
#define BWN_NPHY_ML_LOG_TXEVM4 BWN_PHY_N(0x254)
#define BWN_NPHY_ML_LOG_TXEVM5 BWN_PHY_N(0x255)
#define BWN_NPHY_ML_LOG_TXEVM6 BWN_PHY_N(0x256)
#define BWN_NPHY_ML_LOG_TXEVM7 BWN_PHY_N(0x257)
#define BWN_NPHY_ML_SCALE_TWEAK BWN_PHY_N(0x258)
#define BWN_NPHY_MLUA BWN_PHY_N(0x259)
#define BWN_NPHY_ZFUA BWN_PHY_N(0x25A)
#define BWN_NPHY_CHANUPSYM01 BWN_PHY_N(0x25B)
#define BWN_NPHY_CHANUPSYM2 BWN_PHY_N(0x25C)
#define BWN_NPHY_RXSTRNFILT20NUM00 BWN_PHY_N(0x25D)
#define BWN_NPHY_RXSTRNFILT20NUM01 BWN_PHY_N(0x25E)
#define BWN_NPHY_RXSTRNFILT20NUM02 BWN_PHY_N(0x25F)
#define BWN_NPHY_RXSTRNFILT20DEN00 BWN_PHY_N(0x260)
#define BWN_NPHY_RXSTRNFILT20DEN01 BWN_PHY_N(0x261)
#define BWN_NPHY_RXSTRNFILT20NUM10 BWN_PHY_N(0x262)
#define BWN_NPHY_RXSTRNFILT20NUM11 BWN_PHY_N(0x263)
#define BWN_NPHY_RXSTRNFILT20NUM12 BWN_PHY_N(0x264)
#define BWN_NPHY_RXSTRNFILT20DEN10 BWN_PHY_N(0x265)
#define BWN_NPHY_RXSTRNFILT20DEN11 BWN_PHY_N(0x266)
#define BWN_NPHY_RXSTRNFILT40NUM00 BWN_PHY_N(0x267)
#define BWN_NPHY_RXSTRNFILT40NUM01 BWN_PHY_N(0x268)
#define BWN_NPHY_RXSTRNFILT40NUM02 BWN_PHY_N(0x269)
#define BWN_NPHY_RXSTRNFILT40DEN00 BWN_PHY_N(0x26A)
#define BWN_NPHY_RXSTRNFILT40DEN01 BWN_PHY_N(0x26B)
#define BWN_NPHY_RXSTRNFILT40NUM10 BWN_PHY_N(0x26C)
#define BWN_NPHY_RXSTRNFILT40NUM11 BWN_PHY_N(0x26D)
#define BWN_NPHY_RXSTRNFILT40NUM12 BWN_PHY_N(0x26E)
#define BWN_NPHY_RXSTRNFILT40DEN10 BWN_PHY_N(0x26F)
#define BWN_NPHY_RXSTRNFILT40DEN11 BWN_PHY_N(0x270)
#define BWN_NPHY_CRSHIGHPOWTHRESHOLD1 BWN_PHY_N(0x271)
#define BWN_NPHY_CRSHIGHPOWTHRESHOLD2 BWN_PHY_N(0x272)
#define BWN_NPHY_CRSHIGHLOWPOWTHRESHOLD BWN_PHY_N(0x273)
#define BWN_NPHY_CRSHIGHPOWTHRESHOLD1L BWN_PHY_N(0x274)
#define BWN_NPHY_CRSHIGHPOWTHRESHOLD2L BWN_PHY_N(0x275)
#define BWN_NPHY_CRSHIGHLOWPOWTHRESHOLDL BWN_PHY_N(0x276)
#define BWN_NPHY_CRSHIGHPOWTHRESHOLD1U BWN_PHY_N(0x277)
#define BWN_NPHY_CRSHIGHPOWTHRESHOLD2U BWN_PHY_N(0x278)
#define BWN_NPHY_CRSHIGHLOWPOWTHRESHOLDU BWN_PHY_N(0x279)
#define BWN_NPHY_CRSACIDETECTTHRESH BWN_PHY_N(0x27A)
#define BWN_NPHY_CRSACIDETECTTHRESHL BWN_PHY_N(0x27B)
#define BWN_NPHY_CRSACIDETECTTHRESHU BWN_PHY_N(0x27C)
#define BWN_NPHY_CRSMINPOWER0 BWN_PHY_N(0x27D)
#define BWN_NPHY_CRSMINPOWER1 BWN_PHY_N(0x27E)
#define BWN_NPHY_CRSMINPOWER2 BWN_PHY_N(0x27F)
#define BWN_NPHY_CRSMINPOWERL0 BWN_PHY_N(0x280)
#define BWN_NPHY_CRSMINPOWERL1 BWN_PHY_N(0x281)
#define BWN_NPHY_CRSMINPOWERL2 BWN_PHY_N(0x282)
#define BWN_NPHY_CRSMINPOWERU0 BWN_PHY_N(0x283)
#define BWN_NPHY_CRSMINPOWERU1 BWN_PHY_N(0x284)
#define BWN_NPHY_CRSMINPOWERU2 BWN_PHY_N(0x285)
#define BWN_NPHY_STRPARAM BWN_PHY_N(0x286)
#define BWN_NPHY_STRPARAML BWN_PHY_N(0x287)
#define BWN_NPHY_STRPARAMU BWN_PHY_N(0x288)
#define BWN_NPHY_BPHYCRSMINPOWER0 BWN_PHY_N(0x289)
#define BWN_NPHY_BPHYCRSMINPOWER1 BWN_PHY_N(0x28A)
#define BWN_NPHY_BPHYCRSMINPOWER2 BWN_PHY_N(0x28B)
#define BWN_NPHY_BPHYFILTDEN0COEF BWN_PHY_N(0x28C)
#define BWN_NPHY_BPHYFILTDEN1COEF BWN_PHY_N(0x28D)
#define BWN_NPHY_BPHYFILTDEN2COEF BWN_PHY_N(0x28E)
#define BWN_NPHY_BPHYFILTNUM0COEF BWN_PHY_N(0x28F)
#define BWN_NPHY_BPHYFILTNUM1COEF BWN_PHY_N(0x290)
#define BWN_NPHY_BPHYFILTNUM2COEF BWN_PHY_N(0x291)
#define BWN_NPHY_BPHYFILTNUM01COEF2 BWN_PHY_N(0x292)
#define BWN_NPHY_BPHYFILTBYPASS BWN_PHY_N(0x293)
#define BWN_NPHY_SGILTRNOFFSET BWN_PHY_N(0x294)
#define BWN_NPHY_RADAR_T2_MIN BWN_PHY_N(0x295)
#define BWN_NPHY_TXPWRCTRLDAMPING BWN_PHY_N(0x296)
#define BWN_NPHY_PAPD_EN0 BWN_PHY_N(0x297) /* PAPD Enable0 TBD */
#define BWN_NPHY_EPS_TABLE_ADJ0 BWN_PHY_N(0x298) /* EPS Table Adj0 TBD */
#define BWN_NPHY_EPS_OVERRIDEI_0 BWN_PHY_N(0x299)
#define BWN_NPHY_EPS_OVERRIDEQ_0 BWN_PHY_N(0x29A)
#define BWN_NPHY_PAPD_EN1 BWN_PHY_N(0x29B) /* PAPD Enable1 TBD */
#define BWN_NPHY_EPS_TABLE_ADJ1 BWN_PHY_N(0x29C) /* EPS Table Adj1 TBD */
#define BWN_NPHY_EPS_OVERRIDEI_1 BWN_PHY_N(0x29D)
#define BWN_NPHY_EPS_OVERRIDEQ_1 BWN_PHY_N(0x29E)
#define BWN_NPHY_PAPD_CAL_ADDRESS BWN_PHY_N(0x29F)
#define BWN_NPHY_PAPD_CAL_YREFEPSILON BWN_PHY_N(0x2A0)
#define BWN_NPHY_PAPD_CAL_SETTLE BWN_PHY_N(0x2A1)
#define BWN_NPHY_PAPD_CAL_CORRELATE BWN_PHY_N(0x2A2)
#define BWN_NPHY_PAPD_CAL_SHIFTS0 BWN_PHY_N(0x2A3)
#define BWN_NPHY_PAPD_CAL_SHIFTS1 BWN_PHY_N(0x2A4)
#define BWN_NPHY_SAMPLE_START_ADDR BWN_PHY_N(0x2A5)
#define BWN_NPHY_RADAR_ADC_TO_DBM BWN_PHY_N(0x2A6)
#define BWN_NPHY_REV3_C2_INITGAIN_A BWN_PHY_N(0x2A7)
#define BWN_NPHY_REV3_C2_INITGAIN_B BWN_PHY_N(0x2A8)
#define BWN_NPHY_REV3_C2_CLIP_HIGAIN_A BWN_PHY_N(0x2A9)
#define BWN_NPHY_REV3_C2_CLIP_HIGAIN_B BWN_PHY_N(0x2AA)
#define BWN_NPHY_REV3_C2_CLIP_MEDGAIN_A BWN_PHY_N(0x2AB)
#define BWN_NPHY_REV3_C2_CLIP_MEDGAIN_B BWN_PHY_N(0x2AC)
#define BWN_NPHY_REV3_C2_CLIP_LOGAIN_A BWN_PHY_N(0x2AD)
#define BWN_NPHY_REV3_C2_CLIP_LOGAIN_B BWN_PHY_N(0x2AE)
#define BWN_NPHY_REV3_C2_CLIP2_GAIN_A BWN_PHY_N(0x2AF)
#define BWN_NPHY_REV3_C2_CLIP2_GAIN_B BWN_PHY_N(0x2B0)
#define BWN_NPHY_REV7_RF_CTL_MISC_REG3 BWN_PHY_N(0x340)
#define BWN_NPHY_REV7_RF_CTL_MISC_REG4 BWN_PHY_N(0x341)
#define BWN_NPHY_REV7_RF_CTL_OVER3 BWN_PHY_N(0x342)
#define BWN_NPHY_REV7_RF_CTL_OVER4 BWN_PHY_N(0x343)
#define BWN_NPHY_REV7_RF_CTL_MISC_REG5 BWN_PHY_N(0x344)
#define BWN_NPHY_REV7_RF_CTL_MISC_REG6 BWN_PHY_N(0x345)
#define BWN_NPHY_REV7_RF_CTL_OVER5 BWN_PHY_N(0x346)
#define BWN_NPHY_REV7_RF_CTL_OVER6 BWN_PHY_N(0x347)
#define BWN_PHY_B_BBCFG BWN_PHY_N_BMODE(0x001) /* BB config */
#define BWN_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */
#define BWN_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */
#define BWN_PHY_B_TEST BWN_PHY_N_BMODE(0x00A)
#endif /* __IF_BWN_PHY_N_REGS_H__ */

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/*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
/*
* $FreeBSD$
*/
#ifndef __IF_BWN_TABLES_NPHY_H__
#define __IF_BWN_TABLES_NPHY_H__
struct bwn_phy_n_sfo_cfg {
uint16_t phy_bw1a;
uint16_t phy_bw2;
uint16_t phy_bw3;
uint16_t phy_bw4;
uint16_t phy_bw5;
uint16_t phy_bw6;
};
struct bwn_mac;
struct bwn_nphy_txiqcal_ladder {
uint8_t percent;
uint8_t g_env;
};
struct bwn_nphy_rf_control_override_rev2 {
uint8_t addr0;
uint8_t addr1;
uint16_t bmask;
uint8_t shift;
};
struct bwn_nphy_rf_control_override_rev3 {
uint16_t val_mask;
uint8_t val_shift;
uint8_t en_addr0;
uint8_t val_addr0;
uint8_t en_addr1;
uint8_t val_addr1;
};
struct bwn_nphy_rf_control_override_rev7 {
uint16_t field;
uint16_t val_addr_core0;
uint16_t val_addr_core1;
uint16_t val_mask;
uint8_t val_shift;
};
struct bwn_nphy_gain_ctl_workaround_entry {
int8_t lna1_gain[4];
int8_t lna2_gain[4];
uint8_t gain_db[10];
uint8_t gain_bits[10];
uint16_t init_gain;
uint16_t rfseq_init[4];
uint16_t cliphi_gain;
uint16_t clipmd_gain;
uint16_t cliplo_gain;
uint16_t crsmin;
uint16_t crsminl;
uint16_t crsminu;
uint16_t nbclip;
uint16_t wlclip;
};
/* Get entry with workaround values for gain ctl. Does not return NULL. */
struct bwn_nphy_gain_ctl_workaround_entry *bwn_nphy_get_gain_ctl_workaround_ent(
struct bwn_mac *mac, bool ghz5, bool ext_lna);
/* The N-PHY tables. */
#define BWN_NTAB_TYPEMASK 0xF0000000
#define BWN_NTAB_8BIT 0x10000000
#define BWN_NTAB_16BIT 0x20000000
#define BWN_NTAB_32BIT 0x30000000
#define BWN_NTAB8(table, offset) (((table) << 10) | (offset) | BWN_NTAB_8BIT)
#define BWN_NTAB16(table, offset) (((table) << 10) | (offset) | BWN_NTAB_16BIT)
#define BWN_NTAB32(table, offset) (((table) << 10) | (offset) | BWN_NTAB_32BIT)
/* Static N-PHY tables */
#define BWN_NTAB_FRAMESTRUCT BWN_NTAB32(0x0A, 0x000) /* Frame Struct Table */
#define BWN_NTAB_FRAMESTRUCT_SIZE 832
#define BWN_NTAB_FRAMELT BWN_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
#define BWN_NTAB_FRAMELT_SIZE 32
#define BWN_NTAB_TMAP BWN_NTAB32(0x0C, 0x000) /* T Map Table */
#define BWN_NTAB_TMAP_SIZE 448
#define BWN_NTAB_TDTRN BWN_NTAB32(0x0E, 0x000) /* TDTRN Table */
#define BWN_NTAB_TDTRN_SIZE 704
#define BWN_NTAB_INTLEVEL BWN_NTAB32(0x0D, 0x000) /* Int Level Table */
#define BWN_NTAB_INTLEVEL_SIZE 7
#define BWN_NTAB_PILOT BWN_NTAB16(0x0B, 0x000) /* Pilot Table */
#define BWN_NTAB_PILOT_SIZE 88
#define BWN_NTAB_PILOTLT BWN_NTAB32(0x14, 0x000) /* Pilot Lookup Table */
#define BWN_NTAB_PILOTLT_SIZE 6
#define BWN_NTAB_TDI20A0 BWN_NTAB32(0x13, 0x080) /* TDI Table 20 Antenna 0 */
#define BWN_NTAB_TDI20A0_SIZE 55
#define BWN_NTAB_TDI20A1 BWN_NTAB32(0x13, 0x100) /* TDI Table 20 Antenna 1 */
#define BWN_NTAB_TDI20A1_SIZE 55
#define BWN_NTAB_TDI40A0 BWN_NTAB32(0x13, 0x280) /* TDI Table 40 Antenna 0 */
#define BWN_NTAB_TDI40A0_SIZE 110
#define BWN_NTAB_TDI40A1 BWN_NTAB32(0x13, 0x300) /* TDI Table 40 Antenna 1 */
#define BWN_NTAB_TDI40A1_SIZE 110
#define BWN_NTAB_BDI BWN_NTAB16(0x15, 0x000) /* BDI Table */
#define BWN_NTAB_BDI_SIZE 6
#define BWN_NTAB_CHANEST BWN_NTAB32(0x16, 0x000) /* Channel Estimate Table */
#define BWN_NTAB_CHANEST_SIZE 96
#define BWN_NTAB_MCS BWN_NTAB8 (0x12, 0x000) /* MCS Table */
#define BWN_NTAB_MCS_SIZE 128
/* Volatile N-PHY tables */
#define BWN_NTAB_NOISEVAR10 BWN_NTAB32(0x10, 0x000) /* Noise Var Table 10 */
#define BWN_NTAB_NOISEVAR10_SIZE 256
#define BWN_NTAB_NOISEVAR11 BWN_NTAB32(0x10, 0x080) /* Noise Var Table 11 */
#define BWN_NTAB_NOISEVAR11_SIZE 256
#define BWN_NTAB_C0_ESTPLT BWN_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
#define BWN_NTAB_C0_ESTPLT_SIZE 64
#define BWN_NTAB_C0_ADJPLT BWN_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
#define BWN_NTAB_C0_ADJPLT_SIZE 128
#define BWN_NTAB_C0_GAINCTL BWN_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
#define BWN_NTAB_C0_GAINCTL_SIZE 128
#define BWN_NTAB_C0_IQLT BWN_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
#define BWN_NTAB_C0_IQLT_SIZE 128
#define BWN_NTAB_C0_LOFEEDTH BWN_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
#define BWN_NTAB_C0_LOFEEDTH_SIZE 128
#define BWN_NTAB_C1_ESTPLT BWN_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
#define BWN_NTAB_C1_ESTPLT_SIZE 64
#define BWN_NTAB_C1_ADJPLT BWN_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
#define BWN_NTAB_C1_ADJPLT_SIZE 128
#define BWN_NTAB_C1_GAINCTL BWN_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
#define BWN_NTAB_C1_GAINCTL_SIZE 128
#define BWN_NTAB_C1_IQLT BWN_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
#define BWN_NTAB_C1_IQLT_SIZE 128
#define BWN_NTAB_C1_LOFEEDTH BWN_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
#define BWN_NTAB_C1_LOFEEDTH_SIZE 128
/* Volatile N-PHY tables, PHY revision >= 3 */
#define BWN_NTAB_ANT_SW_CTL_R3 BWN_NTAB16( 9, 0) /* antenna software control */
/* Static N-PHY tables, PHY revision >= 3 */
#define BWN_NTAB_FRAMESTRUCT_R3 BWN_NTAB32(10, 0) /* frame struct */
#define BWN_NTAB_PILOT_R3 BWN_NTAB16(11, 0) /* pilot */
#define BWN_NTAB_TMAP_R3 BWN_NTAB32(12, 0) /* TM AP */
#define BWN_NTAB_INTLEVEL_R3 BWN_NTAB32(13, 0) /* INT LV */
#define BWN_NTAB_TDTRN_R3 BWN_NTAB32(14, 0) /* TD TRN */
#define BWN_NTAB_NOISEVAR_R3 BWN_NTAB32(16, 0) /* noise variance */
#define BWN_NTAB_MCS_R3 BWN_NTAB16(18, 0) /* MCS */
#define BWN_NTAB_TDI20A0_R3 BWN_NTAB32(19, 128) /* TDI 20/0 */
#define BWN_NTAB_TDI20A1_R3 BWN_NTAB32(19, 256) /* TDI 20/1 */
#define BWN_NTAB_TDI40A0_R3 BWN_NTAB32(19, 640) /* TDI 40/0 */
#define BWN_NTAB_TDI40A1_R3 BWN_NTAB32(19, 768) /* TDI 40/1 */
#define BWN_NTAB_PILOTLT_R3 BWN_NTAB32(20, 0) /* PLT lookup */
#define BWN_NTAB_CHANEST_R3 BWN_NTAB32(22, 0) /* channel estimate */
#define BWN_NTAB_FRAMELT_R3 BWN_NTAB8(24, 0) /* frame lookup */
#define BWN_NTAB_C0_ESTPLT_R3 BWN_NTAB8(26, 0) /* estimated power lookup 0 */
#define BWN_NTAB_C0_ADJPLT_R3 BWN_NTAB8(26, 64) /* adjusted power lookup 0 */
#define BWN_NTAB_C0_GAINCTL_R3 BWN_NTAB32(26, 192) /* gain control lookup 0 */
#define BWN_NTAB_C0_IQLT_R3 BWN_NTAB32(26, 320) /* I/Q lookup 0 */
#define BWN_NTAB_C0_LOFEEDTH_R3 BWN_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */
#define BWN_NTAB_C0_PAPD_COMP_R3 BWN_NTAB16(26, 576)
#define BWN_NTAB_C1_ESTPLT_R3 BWN_NTAB8(27, 0) /* estimated power lookup 1 */
#define BWN_NTAB_C1_ADJPLT_R3 BWN_NTAB8(27, 64) /* adjusted power lookup 1 */
#define BWN_NTAB_C1_GAINCTL_R3 BWN_NTAB32(27, 192) /* gain control lookup 1 */
#define BWN_NTAB_C1_IQLT_R3 BWN_NTAB32(27, 320) /* I/Q lookup 1 */
#define BWN_NTAB_C1_LOFEEDTH_R3 BWN_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */
#define BWN_NTAB_C1_PAPD_COMP_R3 BWN_NTAB16(27, 576)
/* Static N-PHY tables, PHY revision >= 7 */
#define BWN_NTAB_TMAP_R7 BWN_NTAB32(12, 0) /* TM AP */
#define BWN_NTAB_NOISEVAR_R7 BWN_NTAB32(16, 0) /* noise variance */
#define BWN_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
#define BWN_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
#define BWN_NTAB_TX_IQLO_CAL_IQIMB_LADDER_40_SIZE 18
#define BWN_NTAB_TX_IQLO_CAL_IQIMB_LADDER_20_SIZE 18
#define BWN_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3 11
#define BWN_NTAB_TX_IQLO_CAL_STARTCOEFS 9
#define BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3 12
#define BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL 10
#define BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL 10
#define BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3 12
uint32_t bwn_ntab_read(struct bwn_mac *mac, uint32_t offset);
void bwn_ntab_read_bulk(struct bwn_mac *mac, uint32_t offset,
unsigned int nr_elements, void *_data);
void bwn_ntab_write(struct bwn_mac *mac, uint32_t offset, uint32_t value);
void bwn_ntab_write_bulk(struct bwn_mac *mac, uint32_t offset,
unsigned int nr_elements, const void *_data);
void bwn_nphy_tables_init(struct bwn_mac *mac);
const uint32_t *bwn_nphy_get_tx_gain_table(struct bwn_mac *mac);
const int16_t *bwn_ntab_get_rf_pwr_offset_table(struct bwn_mac *mac);
extern const int8_t bwn_ntab_papd_pga_gain_delta_ipa_2g[];
extern const uint16_t tbl_iqcal_gainparams[2][9][8];
extern const struct bwn_nphy_txiqcal_ladder ladder_lo[];
extern const struct bwn_nphy_txiqcal_ladder ladder_iq[];
extern const uint16_t loscale[];
extern const uint16_t tbl_tx_iqlo_cal_loft_ladder_40[];
extern const uint16_t tbl_tx_iqlo_cal_loft_ladder_20[];
extern const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_40[];
extern const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_20[];
extern const uint16_t tbl_tx_iqlo_cal_startcoefs_nphyrev3[];
extern const uint16_t tbl_tx_iqlo_cal_startcoefs[];
extern const uint16_t tbl_tx_iqlo_cal_cmds_recal_nphyrev3[];
extern const uint16_t tbl_tx_iqlo_cal_cmds_recal[];
extern const uint16_t tbl_tx_iqlo_cal_cmds_fullcal[];
extern const uint16_t tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[];
extern const int16_t tbl_tx_filter_coef_rev4[7][15];
extern const struct bwn_nphy_rf_control_override_rev2
tbl_rf_control_override_rev2[];
extern const struct bwn_nphy_rf_control_override_rev3
tbl_rf_control_override_rev3[];
const struct bwn_nphy_rf_control_override_rev7 *bwn_nphy_get_rf_ctl_over_rev7(
struct bwn_mac *mac, uint16_t field, uint8_t override);
#endif /* __IF_BWN_PHY_TABLES_N_H__ */

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/*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
/*
* $FreeBSD$
*/
#ifndef __IF_BWN_RADIO_2055_H__
#define __IF_BWN_RADIO_2055_H__
#define B2055_GEN_SPARE 0x00 /* GEN spare */
#define B2055_SP_PINPD 0x02 /* SP PIN PD */
#define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */
#define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */
#define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */
#define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */
#define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
#define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
#define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
#define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
#define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */
#define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */
#define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
#define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
#define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
#define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
#define B2055_MASTER1 0x11 /* Master control 1 */
#define B2055_MASTER2 0x12 /* Master control 2 */
#define B2055_PD_LGEN 0x13 /* PD LGEN */
#define B2055_PD_PLLTS 0x14 /* PD PLL TS */
#define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */
#define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
#define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */
#define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */
#define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */
#define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */
#define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */
#define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */
#define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */
#define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */
#define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */
#define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */
#define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */
#define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */
#define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */
#define B2055_CAL_MISC 0x24 /* CAL MISC */
#define B2055_CAL_COUT 0x25 /* CAL Counter out */
#define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */
#define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */
#define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */
#define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */
#define B2055_CAL_TS 0x2A /* CAL TS */
#define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */
#define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */
#define B2055_PADDRV 0x2D /* PAD driver */
#define B2055_XOCTL1 0x2E /* XO Control 1 */
#define B2055_XOCTL2 0x2F /* XO Control 2 */
#define B2055_XOREGUL 0x30 /* XO Regulator */
#define B2055_XOMISC 0x31 /* XO misc */
#define B2055_PLL_LFC1 0x32 /* PLL LF C1 */
#define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */
#define B2055_PLL_LFC2 0x34 /* PLL LF C2 */
#define B2055_PLL_REF 0x35 /* PLL reference */
#define B2055_PLL_LFR1 0x36 /* PLL LF R1 */
#define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */
#define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */
#define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */
#define B2055_PLL_RCAL 0x3A /* PLL RCAL */
#define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */
#define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */
#define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */
#define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */
#define B2055_RF_MMDSP 0x3F /* RF MMD spare */
#define B2055_VCO_CAL1 0x40 /* VCO cal 1 */
#define B2055_VCO_CAL2 0x41 /* VCO cal 2 */
#define B2055_VCO_CAL3 0x42 /* VCO cal 3 */
#define B2055_VCO_CAL4 0x43 /* VCO cal 4 */
#define B2055_VCO_CAL5 0x44 /* VCO cal 5 */
#define B2055_VCO_CAL6 0x45 /* VCO cal 6 */
#define B2055_VCO_CAL7 0x46 /* VCO cal 7 */
#define B2055_VCO_CAL8 0x47 /* VCO cal 8 */
#define B2055_VCO_CAL9 0x48 /* VCO cal 9 */
#define B2055_VCO_CAL10 0x49 /* VCO cal 10 */
#define B2055_VCO_CAL11 0x4A /* VCO cal 11 */
#define B2055_VCO_CAL12 0x4B /* VCO cal 12 */
#define B2055_VCO_CAL13 0x4C /* VCO cal 13 */
#define B2055_VCO_CAL14 0x4D /* VCO cal 14 */
#define B2055_VCO_CAL15 0x4E /* VCO cal 15 */
#define B2055_VCO_CAL16 0x4F /* VCO cal 16 */
#define B2055_VCO_KVCO 0x50 /* VCO KVCO */
#define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */
#define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */
#define B2055_VCO_REG 0x53 /* VCO Regulator */
#define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */
#define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */
#define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */
#define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */
#define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */
#define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */
#define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */
#define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */
#define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */
#define B2055_LGEN_DIV 0x5D /* LGEN div */
#define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */
#define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */
#define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */
#define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */
#define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */
#define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */
#define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */
#define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */
#define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */
#define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */
#define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */
#define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */
#define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */
#define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */
#define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */
#define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */
#define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */
#define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */
#define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */
#define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */
#define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */
#define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */
#define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */
#define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */
#define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */
#define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */
#define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */
#define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */
#define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */
#define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */
#define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */
#define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */
#define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */
#define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */
#define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */
#define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */
#define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */
#define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */
#define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */
#define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */
#define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */
#define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */
#define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */
#define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */
#define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */
#define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */
#define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */
#define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */
#define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */
#define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */
#define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */
#define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */
#define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */
#define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */
#define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */
#define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */
#define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */
#define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */
#define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */
#define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */
#define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */
#define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */
#define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */
#define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */
#define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */
#define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */
#define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */
#define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */
#define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */
#define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */
#define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */
#define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */
#define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */
#define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */
#define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */
#define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */
#define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */
#define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */
#define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */
#define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */
#define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */
#define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */
#define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */
#define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */
#define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */
#define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */
#define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */
#define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */
#define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */
#define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */
#define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */
#define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */
#define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */
#define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */
#define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */
#define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */
#define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */
#define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */
#define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */
#define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */
#define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */
#define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */
#define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */
#define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */
#define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */
#define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */
#define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */
#define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */
#define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */
#define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */
#define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */
struct bwn_nphy_channeltab_entry_rev2 {
/* The channel number */
uint8_t channel;
/* The channel frequency in MHz */
uint16_t freq;
/* An unknown value */
uint16_t unk2;
/* Radio register values on channelswitch */
uint8_t radio_pll_ref;
uint8_t radio_rf_pllmod0;
uint8_t radio_rf_pllmod1;
uint8_t radio_vco_captail;
uint8_t radio_vco_cal1;
uint8_t radio_vco_cal2;
uint8_t radio_pll_lfc1;
uint8_t radio_pll_lfr1;
uint8_t radio_pll_lfc2;
uint8_t radio_lgbuf_cenbuf;
uint8_t radio_lgen_tune1;
uint8_t radio_lgen_tune2;
uint8_t radio_c1_lgbuf_atune;
uint8_t radio_c1_lgbuf_gtune;
uint8_t radio_c1_rx_rfr1;
uint8_t radio_c1_tx_pgapadtn;
uint8_t radio_c1_tx_mxbgtrim;
uint8_t radio_c2_lgbuf_atune;
uint8_t radio_c2_lgbuf_gtune;
uint8_t radio_c2_rx_rfr1;
uint8_t radio_c2_tx_pgapadtn;
uint8_t radio_c2_tx_mxbgtrim;
/* PHY register values on channelswitch */
struct bwn_phy_n_sfo_cfg phy_regs;
};
/* Upload the default register value table.
* If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz
* table is uploaded. If "ignore_uploadflag" is true, we upload any value
* and ignore the "UPLOAD" flag. */
void b2055_upload_inittab(struct bwn_mac *mac,
bool ghz5, bool ignore_uploadflag);
/* Get the NPHY Channel Switch Table entry for a channel.
* Returns NULL on failure to find an entry. */
extern const struct bwn_nphy_channeltab_entry_rev2 *
bwn_nphy_get_chantabent_rev2(struct bwn_mac *mac,
uint8_t channel);
#endif /* __IF_BWN_RADIO_2055_H__ */

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/*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* The Broadcom Wireless LAN controller driver.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/endian.h>
#include <sys/errno.h>
#include <sys/firmware.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <net/if_var.h>
#include <net/if_arp.h>
#include <net/if_dl.h>
#include <net/if_llc.h>
#include <net/if_media.h>
#include <net/if_types.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/siba/siba_ids.h>
#include <dev/siba/sibareg.h>
#include <dev/siba/sibavar.h>
#include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_radiotap.h>
#include <net80211/ieee80211_regdomain.h>
#include <net80211/ieee80211_phy.h>
#include <net80211/ieee80211_ratectl.h>
#include <dev/bwn/if_bwnreg.h>
#include <dev/bwn/if_bwnvar.h>
#include <dev/bwn/if_bwn_debug.h>
#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h>
#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h>
#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h>
#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h>
#include <gnu/dev/bwn/phy_n/if_bwn_radio_2057.h>
static uint16_t r2057_rev4_init[][2] = {
{ 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 },
{ 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff },
{ 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 },
{ 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c },
{ 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 },
{ 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c },
{ 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
{ 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
{ 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
{ 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
{ 0x1AB, 0x00 }, { 0x1AC, 0x00 },
};
static uint16_t r2057_rev5_init[][2] = {
{ 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 },
{ 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 },
{ 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f },
{ 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
{ 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 },
{ 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f },
{ 0x117, 0x36 }, { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
{ 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
{ 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 },
{ 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 },
{ 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 }, { 0x1C2, 0x80 },
};
static uint16_t r2057_rev5a_init[][2] = {
{ 0x00, 0x15 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 },
{ 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 },
{ 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f },
{ 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
{ 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 },
{ 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f },
{ 0x117, 0x36 }, { 0x126, 0x20 }, { 0x14E, 0x01 }, { 0x15E, 0x00 },
{ 0x15F, 0x00 }, { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 },
{ 0x163, 0x00 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
{ 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
{ 0x1AB, 0x00 }, { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 },
{ 0x1C2, 0x80 },
};
static uint16_t r2057_rev7_init[][2] = {
{ 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 },
{ 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 },
{ 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x13 },
{ 0x66, 0xee }, { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 },
{ 0x7C, 0x14 }, { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f },
{ 0x92, 0x36 }, { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 },
{ 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x13 }, { 0xEB, 0xee },
{ 0xF3, 0x58 }, { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x14 },
{ 0x102, 0xee }, { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 },
{ 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 },
{ 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 },
{ 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 },
{ 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
{ 0x1B7, 0x05 }, { 0x1C2, 0xa0 },
};
/* TODO: Which devices should use it?
static uint16_t r2057_rev8_init[][2] = {
{ 0x00, 0x08 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 },
{ 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 },
{ 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x0f },
{ 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 }, { 0x7C, 0x0f },
{ 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
{ 0xA1, 0x20 }, { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 },
{ 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0xF3, 0x58 },
{ 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x0f }, { 0x102, 0xee },
{ 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x126, 0x20 },
{ 0x14E, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 },
{ 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 },
{ 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 },
{ 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
{ 0x1B7, 0x05 }, { 0x1C2, 0xa0 },
};
*/
/* Extracted from MMIO dump of 6.30.223.141 */
static uint16_t r2057_rev9_init[][2] = {
{ 0x27, 0x1f }, { 0x28, 0x0a }, { 0x29, 0x2f }, { 0x42, 0x1f },
{ 0x48, 0x3f }, { 0x5c, 0x41 }, { 0x63, 0x14 }, { 0x64, 0x12 },
{ 0x66, 0xff }, { 0x74, 0xa3 }, { 0x7b, 0x14 }, { 0x7c, 0x14 },
{ 0x7d, 0xee }, { 0x86, 0xc0 }, { 0xc4, 0x10 }, { 0xc9, 0x01 },
{ 0xe1, 0x41 }, { 0xe8, 0x14 }, { 0xe9, 0x12 }, { 0xeb, 0xff },
{ 0xf5, 0x0a }, { 0xf8, 0x09 }, { 0xf9, 0xa3 }, { 0x100, 0x14 },
{ 0x101, 0x10 }, { 0x102, 0xee }, { 0x10b, 0xc0 }, { 0x149, 0x10 },
{ 0x14e, 0x01 }, { 0x1b7, 0x05 }, { 0x1c2, 0xa0 },
};
/* Extracted from MMIO dump of 6.30.223.248 */
static uint16_t r2057_rev14_init[][2] = {
{ 0x011, 0xfc }, { 0x030, 0x24 }, { 0x040, 0x1c }, { 0x082, 0x08 },
{ 0x0b4, 0x44 }, { 0x0c8, 0x01 }, { 0x0c9, 0x01 }, { 0x107, 0x08 },
{ 0x14d, 0x01 }, { 0x14e, 0x01 }, { 0x1af, 0x40 }, { 0x1b0, 0x40 },
{ 0x1cc, 0x01 }, { 0x1cf, 0x10 }, { 0x1d0, 0x0f }, { 0x1d3, 0x10 },
{ 0x1d4, 0x0f },
};
#define RADIOREGS7(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
r20, r21, r22, r23, r24, r25, r26, r27) \
.radio_vcocal_countval0 = r00, \
.radio_vcocal_countval1 = r01, \
.radio_rfpll_refmaster_sparextalsize = r02, \
.radio_rfpll_loopfilter_r1 = r03, \
.radio_rfpll_loopfilter_c2 = r04, \
.radio_rfpll_loopfilter_c1 = r05, \
.radio_cp_kpd_idac = r06, \
.radio_rfpll_mmd0 = r07, \
.radio_rfpll_mmd1 = r08, \
.radio_vcobuf_tune = r09, \
.radio_logen_mx2g_tune = r10, \
.radio_logen_mx5g_tune = r11, \
.radio_logen_indbuf2g_tune = r12, \
.radio_logen_indbuf5g_tune = r13, \
.radio_txmix2g_tune_boost_pu_core0 = r14, \
.radio_pad2g_tune_pus_core0 = r15, \
.radio_pga_boost_tune_core0 = r16, \
.radio_txmix5g_boost_tune_core0 = r17, \
.radio_pad5g_tune_misc_pus_core0 = r18, \
.radio_lna2g_tune_core0 = r19, \
.radio_lna5g_tune_core0 = r20, \
.radio_txmix2g_tune_boost_pu_core1 = r21, \
.radio_pad2g_tune_pus_core1 = r22, \
.radio_pga_boost_tune_core1 = r23, \
.radio_txmix5g_boost_tune_core1 = r24, \
.radio_pad5g_tune_misc_pus_core1 = r25, \
.radio_lna2g_tune_core1 = r26, \
.radio_lna5g_tune_core1 = r27
#define RADIOREGS7_2G(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
r10, r11, r12, r13, r14, r15, r16, r17) \
.radio_vcocal_countval0 = r00, \
.radio_vcocal_countval1 = r01, \
.radio_rfpll_refmaster_sparextalsize = r02, \
.radio_rfpll_loopfilter_r1 = r03, \
.radio_rfpll_loopfilter_c2 = r04, \
.radio_rfpll_loopfilter_c1 = r05, \
.radio_cp_kpd_idac = r06, \
.radio_rfpll_mmd0 = r07, \
.radio_rfpll_mmd1 = r08, \
.radio_vcobuf_tune = r09, \
.radio_logen_mx2g_tune = r10, \
.radio_logen_indbuf2g_tune = r11, \
.radio_txmix2g_tune_boost_pu_core0 = r12, \
.radio_pad2g_tune_pus_core0 = r13, \
.radio_lna2g_tune_core0 = r14, \
.radio_txmix2g_tune_boost_pu_core1 = r15, \
.radio_pad2g_tune_pus_core1 = r16, \
.radio_lna2g_tune_core1 = r17
#define PHYREGS(r0, r1, r2, r3, r4, r5) \
.phy_regs.phy_bw1a = r0, \
.phy_regs.phy_bw2 = r1, \
.phy_regs.phy_bw3 = r2, \
.phy_regs.phy_bw4 = r3, \
.phy_regs.phy_bw5 = r4, \
.phy_regs.phy_bw6 = r5
/* Copied from brcmsmac (5.75.11): chan_info_nphyrev8_2057_rev5 */
static const struct bwn_nphy_chantabent_rev7_2g bwn_nphy_chantab_phy_rev8_radio_rev5[] = {
{
.freq = 2412,
RADIOREGS7_2G(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61,
0x03, 0xff),
PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
},
{
.freq = 2417,
RADIOREGS7_2G(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61,
0x03, 0xff),
PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
},
{
.freq = 2422,
RADIOREGS7_2G(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61,
0x03, 0xef),
PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
},
{
.freq = 2427,
RADIOREGS7_2G(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
0x09, 0x0c, 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61,
0x03, 0xdf),
PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
},
{
.freq = 2432,
RADIOREGS7_2G(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
0x09, 0x0c, 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61,
0x03, 0xcf),
PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
},
{
.freq = 2437,
RADIOREGS7_2G(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
0x09, 0x0c, 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61,
0x03, 0xbf),
PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
},
{
.freq = 2442,
RADIOREGS7_2G(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61,
0x03, 0xaf),
PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
},
{
.freq = 2447,
RADIOREGS7_2G(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61,
0x03, 0x9f),
PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
},
{
.freq = 2452,
RADIOREGS7_2G(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61,
0x03, 0x8f),
PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
},
{
.freq = 2457,
RADIOREGS7_2G(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
0x09, 0x0b, 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61,
0x03, 0x7f),
PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
},
{
.freq = 2462,
RADIOREGS7_2G(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
0x09, 0x0b, 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61,
0x03, 0x6f),
PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
},
{
.freq = 2467,
RADIOREGS7_2G(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
0x09, 0x0b, 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61,
0x03, 0x5f),
PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
},
{
.freq = 2472,
RADIOREGS7_2G(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
0x09, 0x0a, 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61,
0x03, 0x4f),
PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
},
{
.freq = 2484,
RADIOREGS7_2G(0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4,
0x09, 0x0a, 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61,
0x03, 0x3f),
PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424),
}
};
/* Extracted from MMIO dump of 6.30.223.248 */
static const struct bwn_nphy_chantabent_rev7_2g bwn_nphy_chantab_phy_rev17_radio_rev14[] = {
{
.freq = 2412,
RADIOREGS7_2G(0x48, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x6c,
0x09, 0x0d, 0x09, 0x03, 0x21, 0x53, 0xff, 0x21,
0x53, 0xff),
PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
},
{
.freq = 2417,
RADIOREGS7_2G(0x4b, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x71,
0x09, 0x0d, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21,
0x53, 0xff),
PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
},
{
.freq = 2422,
RADIOREGS7_2G(0x4e, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x76,
0x09, 0x0d, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21,
0x53, 0xff),
PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
},
{
.freq = 2427,
RADIOREGS7_2G(0x52, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x7b,
0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21,
0x53, 0xff),
PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
},
{
.freq = 2432,
RADIOREGS7_2G(0x55, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x80,
0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21,
0x53, 0xff),
PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
},
{
.freq = 2437,
RADIOREGS7_2G(0x58, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x85,
0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21,
0x53, 0xff),
PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
},
{
.freq = 2442,
RADIOREGS7_2G(0x5c, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x8a,
0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21,
0x43, 0xff),
PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
},
{
.freq = 2447,
RADIOREGS7_2G(0x5f, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x8f,
0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21,
0x43, 0xff),
PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
},
{
.freq = 2452,
RADIOREGS7_2G(0x62, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x94,
0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21,
0x43, 0xff),
PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
},
{
.freq = 2457,
RADIOREGS7_2G(0x66, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x99,
0x09, 0x0b, 0x07, 0x03, 0x21, 0x43, 0xff, 0x21,
0x43, 0xff),
PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
},
{
.freq = 2462,
RADIOREGS7_2G(0x69, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x9e,
0x09, 0x0b, 0x07, 0x03, 0x01, 0x43, 0xff, 0x01,
0x43, 0xff),
PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
},
};
/* Extracted from MMIO dump of 6.30.223.141 */
static const struct bwn_nphy_chantabent_rev7 bwn_nphy_chantab_phy_rev16_radio_rev9[] = {
{
.freq = 2412,
RADIOREGS7(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
},
{
.freq = 2417,
RADIOREGS7(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
},
{
.freq = 2422,
RADIOREGS7(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
},
{
.freq = 2427,
RADIOREGS7(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
},
{
.freq = 2432,
RADIOREGS7(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
},
{
.freq = 2437,
RADIOREGS7(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
},
{
.freq = 2442,
RADIOREGS7(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
},
{
.freq = 2447,
RADIOREGS7(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
},
{
.freq = 2452,
RADIOREGS7(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
},
{
.freq = 2457,
RADIOREGS7(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
},
{
.freq = 2462,
RADIOREGS7(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x41, 0x63,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00,
0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
},
{
.freq = 5180,
RADIOREGS7(0xbe, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x06,
0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00,
0x9f, 0x2f, 0xa3, 0x00, 0xfc, 0x00, 0x00, 0x4f,
0x3a, 0x83, 0x00, 0xfc),
PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb),
},
{
.freq = 5200,
RADIOREGS7(0xc5, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x08,
0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00,
0x7f, 0x2f, 0x83, 0x00, 0xf8, 0x00, 0x00, 0x4c,
0x4a, 0x83, 0x00, 0xf8),
PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9),
},
{
.freq = 5220,
RADIOREGS7(0xcc, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0a,
0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00,
0x6d, 0x3d, 0x83, 0x00, 0xf8, 0x00, 0x00, 0x2d,
0x2a, 0x73, 0x00, 0xf8),
PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7),
},
{
.freq = 5240,
RADIOREGS7(0xd2, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0c,
0x02, 0x0d, 0x00, 0x0d, 0x00, 0x8d, 0x00, 0x00,
0x4d, 0x1c, 0x73, 0x00, 0xf8, 0x00, 0x00, 0x4d,
0x2b, 0x73, 0x00, 0xf8),
PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5),
},
{
.freq = 5745,
RADIOREGS7(0x7b, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x7d,
0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00,
0x08, 0x03, 0x03, 0x00, 0x30, 0x00, 0x00, 0x06,
0x02, 0x03, 0x00, 0x30),
PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9),
},
{
.freq = 5765,
RADIOREGS7(0x81, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x81,
0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00,
0x06, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05,
0x02, 0x03, 0x00, 0x00),
PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8),
},
{
.freq = 5785,
RADIOREGS7(0x88, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x85,
0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00,
0x08, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05,
0x21, 0x03, 0x00, 0x00),
PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6),
},
{
.freq = 5805,
RADIOREGS7(0x8f, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x89,
0x04, 0x07, 0x00, 0x06, 0x00, 0x04, 0x00, 0x00,
0x06, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
0x00, 0x03, 0x00, 0x00),
PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4),
},
{
.freq = 5825,
RADIOREGS7(0x95, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x8d,
0x04, 0x07, 0x00, 0x05, 0x00, 0x03, 0x00, 0x00,
0x05, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
0x00, 0x03, 0x00, 0x00),
PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3),
},
};
void r2057_upload_inittabs(struct bwn_mac *mac)
{
struct bwn_phy *phy = &mac->mac_phy;
uint16_t *table = NULL;
uint16_t size, i;
switch (phy->rev) {
case 7:
table = r2057_rev4_init[0];
size = nitems(r2057_rev4_init);
break;
case 8:
if (phy->rf_rev == 5) {
table = r2057_rev5_init[0];
size = nitems(r2057_rev5_init);
} else if (phy->rf_rev == 7) {
table = r2057_rev7_init[0];
size = nitems(r2057_rev7_init);
}
break;
case 9:
if (phy->rf_rev == 5) {
table = r2057_rev5a_init[0];
size = nitems(r2057_rev5a_init);
}
break;
case 16:
if (phy->rf_rev == 9) {
table = r2057_rev9_init[0];
size = nitems(r2057_rev9_init);
}
break;
case 17:
if (phy->rf_rev == 14) {
table = r2057_rev14_init[0];
size = nitems(r2057_rev14_init);
}
break;
}
if (! table) {
device_printf(mac->mac_sc->sc_dev,
"%s: couldn't find a suitable table (phy ref=%d, rf_ref=%d)\n",
__func__,
phy->rev,
phy->rf_rev);
}
if (table) {
for (i = 0; i < size; i++, table += 2)
BWN_RF_WRITE(mac, table[0], table[1]);
}
}
void r2057_get_chantabent_rev7(struct bwn_mac *mac, uint16_t freq,
const struct bwn_nphy_chantabent_rev7 **tabent_r7,
const struct bwn_nphy_chantabent_rev7_2g **tabent_r7_2g)
{
struct bwn_phy *phy = &mac->mac_phy;
const struct bwn_nphy_chantabent_rev7 *e_r7 = NULL;
const struct bwn_nphy_chantabent_rev7_2g *e_r7_2g = NULL;
unsigned int len, i;
*tabent_r7 = NULL;
*tabent_r7_2g = NULL;
switch (phy->rev) {
case 8:
if (phy->rf_rev == 5) {
e_r7_2g = bwn_nphy_chantab_phy_rev8_radio_rev5;
len = nitems(bwn_nphy_chantab_phy_rev8_radio_rev5);
}
break;
case 16:
if (phy->rf_rev == 9) {
e_r7 = bwn_nphy_chantab_phy_rev16_radio_rev9;
len = nitems(bwn_nphy_chantab_phy_rev16_radio_rev9);
}
break;
case 17:
if (phy->rf_rev == 14) {
e_r7_2g = bwn_nphy_chantab_phy_rev17_radio_rev14;
len = nitems(bwn_nphy_chantab_phy_rev17_radio_rev14);
}
break;
default:
break;
}
if (e_r7) {
for (i = 0; i < len; i++, e_r7++) {
if (e_r7->freq == freq) {
*tabent_r7 = e_r7;
return;
}
}
} else if (e_r7_2g) {
for (i = 0; i < len; i++, e_r7_2g++) {
if (e_r7_2g->freq == freq) {
*tabent_r7_2g = e_r7_2g;
return;
}
}
} else {
device_printf(mac->mac_sc->sc_dev,
"%s: couldn't find a suitable chantab\n",
__func__);
}
}

531
sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.h Normal file
View File

@ -0,0 +1,531 @@
/*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
/*
* $FreeBSD$
*/
#ifndef __IF_BWN_RADIO_2057_H__
#define __IF_BWN_RADIO_2057_H__
#define R2057_DACBUF_VINCM_CORE0 0x000
#define R2057_IDCODE 0x001
#define R2057_RCCAL_MASTER 0x002
#define R2057_RCCAL_CAP_SIZE 0x003
#define R2057_RCAL_CONFIG 0x004
#define R2057_GPAIO_CONFIG 0x005
#define R2057_GPAIO_SEL1 0x006
#define R2057_GPAIO_SEL0 0x007
#define R2057_CLPO_CONFIG 0x008
#define R2057_BANDGAP_CONFIG 0x009
#define R2057_BANDGAP_RCAL_TRIM 0x00a
#define R2057_AFEREG_CONFIG 0x00b
#define R2057_TEMPSENSE_CONFIG 0x00c
#define R2057_XTAL_CONFIG1 0x00d
#define R2057_XTAL_ICORE_SIZE 0x00e
#define R2057_XTAL_BUF_SIZE 0x00f
#define R2057_XTAL_PULLCAP_SIZE 0x010
#define R2057_RFPLL_MASTER 0x011
#define R2057_VCOMONITOR_VTH_L 0x012
#define R2057_VCOMONITOR_VTH_H 0x013
#define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x014
#define R2057_VCO_VARCSIZE_IDAC 0x015
#define R2057_VCOCAL_COUNTVAL0 0x016
#define R2057_VCOCAL_COUNTVAL1 0x017
#define R2057_VCOCAL_INTCLK_COUNT 0x018
#define R2057_VCOCAL_MASTER 0x019
#define R2057_VCOCAL_NUMCAPCHANGE 0x01a
#define R2057_VCOCAL_WINSIZE 0x01b
#define R2057_VCOCAL_DELAY_AFTER_REFRESH 0x01c
#define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x01d
#define R2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x01e
#define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x01f
#define R2057_VCO_FORCECAPEN_FORCECAP1 0x020
#define R2057_VCO_FORCECAP0 0x021
#define R2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x022
#define R2057_RFPLL_PFD_RESET_PW 0x023
#define R2057_RFPLL_LOOPFILTER_R2 0x024
#define R2057_RFPLL_LOOPFILTER_R1 0x025
#define R2057_RFPLL_LOOPFILTER_C3 0x026
#define R2057_RFPLL_LOOPFILTER_C2 0x027
#define R2057_RFPLL_LOOPFILTER_C1 0x028
#define R2057_CP_KPD_IDAC 0x029
#define R2057_RFPLL_IDACS 0x02a
#define R2057_RFPLL_MISC_EN 0x02b
#define R2057_RFPLL_MMD0 0x02c
#define R2057_RFPLL_MMD1 0x02d
#define R2057_RFPLL_MISC_CAL_RESETN 0x02e
#define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x02f
#define R2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x030
#define R2057_VCOCAL_READCAP0 0x031
#define R2057_VCOCAL_READCAP1 0x032
#define R2057_VCOCAL_STATUS 0x033
#define R2057_LOGEN_PUS 0x034
#define R2057_LOGEN_PTAT_RESETS 0x035
#define R2057_VCOBUF_IDACS 0x036
#define R2057_VCOBUF_TUNE 0x037
#define R2057_CMOSBUF_TX2GQ_IDACS 0x038
#define R2057_CMOSBUF_TX2GI_IDACS 0x039
#define R2057_CMOSBUF_TX5GQ_IDACS 0x03a
#define R2057_CMOSBUF_TX5GI_IDACS 0x03b
#define R2057_CMOSBUF_RX2GQ_IDACS 0x03c
#define R2057_CMOSBUF_RX2GI_IDACS 0x03d
#define R2057_CMOSBUF_RX5GQ_IDACS 0x03e
#define R2057_CMOSBUF_RX5GI_IDACS 0x03f
#define R2057_LOGEN_MX2G_IDACS 0x040
#define R2057_LOGEN_MX2G_TUNE 0x041
#define R2057_LOGEN_MX5G_IDACS 0x042
#define R2057_LOGEN_MX5G_TUNE 0x043
#define R2057_LOGEN_MX5G_RCCR 0x044
#define R2057_LOGEN_INDBUF2G_IDAC 0x045
#define R2057_LOGEN_INDBUF2G_IBOOST 0x046
#define R2057_LOGEN_INDBUF2G_TUNE 0x047
#define R2057_LOGEN_INDBUF5G_IDAC 0x048
#define R2057_LOGEN_INDBUF5G_IBOOST 0x049
#define R2057_LOGEN_INDBUF5G_TUNE 0x04a
#define R2057_CMOSBUF_TX_RCCR 0x04b
#define R2057_CMOSBUF_RX_RCCR 0x04c
#define R2057_LOGEN_SEL_PKDET 0x04d
#define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e
/* MISC core 0 */
#define R2057_RXTXBIAS_CONFIG_CORE0 0x04f
#define R2057_TXGM_TXRF_PUS_CORE0 0x050
#define R2057_TXGM_IDAC_BLEED_CORE0 0x051
#define R2057_TXGM_GAIN_CORE0 0x056
#define R2057_TXGM2G_PKDET_PUS_CORE0 0x057
#define R2057_PAD2G_PTATS_CORE0 0x058
#define R2057_PAD2G_IDACS_CORE0 0x059
#define R2057_PAD2G_BOOST_PU_CORE0 0x05a
#define R2057_PAD2G_CASCV_GAIN_CORE0 0x05b
#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x05c
#define R2057_TXMIX2G_LODC_CORE0 0x05d
#define R2057_PAD2G_TUNE_PUS_CORE0 0x05e
#define R2057_IPA2G_GAIN_CORE0 0x05f
#define R2057_TSSI2G_SPARE1_CORE0 0x060
#define R2057_TSSI2G_SPARE2_CORE0 0x061
#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x062
#define R2057_IPA2G_IMAIN_CORE0 0x063
#define R2057_IPA2G_CASCONV_CORE0 0x064
#define R2057_IPA2G_CASCOFFV_CORE0 0x065
#define R2057_IPA2G_BIAS_FILTER_CORE0 0x066
#define R2057_TX5G_PKDET_CORE0 0x069
#define R2057_PGA_PTAT_TXGM5G_PU_CORE0 0x06a
#define R2057_PAD5G_PTATS1_CORE0 0x06b
#define R2057_PAD5G_CLASS_PTATS2_CORE0 0x06c
#define R2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x06d
#define R2057_PAD5G_CASCV_IMAIN_CORE0 0x06e
#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x06f
#define R2057_PGA_BOOST_TUNE_CORE0 0x070
#define R2057_PGA_GAIN_CORE0 0x071
#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x072
#define R2057_TXMIX5G_BOOST_TUNE_CORE0 0x073
#define R2057_PAD5G_TUNE_MISC_PUS_CORE0 0x074
#define R2057_IPA5G_IAUX_CORE0 0x075
#define R2057_IPA5G_GAIN_CORE0 0x076
#define R2057_TSSI5G_SPARE1_CORE0 0x077
#define R2057_TSSI5G_SPARE2_CORE0 0x078
#define R2057_IPA5G_CASCOFFV_PU_CORE0 0x079
#define R2057_IPA5G_PTAT_CORE0 0x07a
#define R2057_IPA5G_IMAIN_CORE0 0x07b
#define R2057_IPA5G_CASCONV_CORE0 0x07c
#define R2057_IPA5G_BIAS_FILTER_CORE0 0x07d
#define R2057_PAD_BIAS_FILTER_BWS_CORE0 0x080
#define R2057_TR2G_CONFIG1_CORE0_NU 0x081
#define R2057_TR2G_CONFIG2_CORE0_NU 0x082
#define R2057_LNA5G_RFEN_CORE0 0x083
#define R2057_TR5G_CONFIG2_CORE0_NU 0x084
#define R2057_RXRFBIAS_IBOOST_PU_CORE0 0x085
#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x086
#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x087
#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x088
#define R2057_RXMIX_CMFBITAIL_PU_CORE0 0x089
#define R2057_LNA2_IMAIN_PTAT_PU_CORE0 0x08a
#define R2057_LNA2_IAUX_PTAT_CORE0 0x08b
#define R2057_LNA1_IMAIN_PTAT_PU_CORE0 0x08c
#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x08d
#define R2057_RXRFBIAS_BANDSEL_CORE0 0x08e
#define R2057_TIA_CONFIG_CORE0 0x08f
#define R2057_TIA_IQGAIN_CORE0 0x090
#define R2057_TIA_IBIAS2_CORE0 0x091
#define R2057_TIA_IBIAS1_CORE0 0x092
#define R2057_TIA_SPARE_Q_CORE0 0x093
#define R2057_TIA_SPARE_I_CORE0 0x094
#define R2057_RXMIX2G_PUS_CORE0 0x095
#define R2057_RXMIX2G_VCMREFS_CORE0 0x096
#define R2057_RXMIX2G_LODC_QI_CORE0 0x097
#define R2057_W12G_BW_LNA2G_PUS_CORE0 0x098
#define R2057_LNA2G_GAIN_CORE0 0x099
#define R2057_LNA2G_TUNE_CORE0 0x09a
#define R2057_RXMIX5G_PUS_CORE0 0x09b
#define R2057_RXMIX5G_VCMREFS_CORE0 0x09c
#define R2057_RXMIX5G_LODC_QI_CORE0 0x09d
#define R2057_W15G_BW_LNA5G_PUS_CORE0 0x09e
#define R2057_LNA5G_GAIN_CORE0 0x09f
#define R2057_LNA5G_TUNE_CORE0 0x0a0
#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0x0a1
#define R2057_RXBB_BIAS_MASTER_CORE0 0x0a2
#define R2057_RXBB_VGABUF_IDACS_CORE0 0x0a3
#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0x0a4
#define R2057_TXBUF_VINCM_CORE0 0x0a5
#define R2057_TXBUF_IDACS_CORE0 0x0a6
#define R2057_LPF_RESP_RXBUF_BW_CORE0 0x0a7
#define R2057_RXBB_CC_CORE0 0x0a8
#define R2057_RXBB_SPARE3_CORE0 0x0a9
#define R2057_RXBB_RCCAL_HPC_CORE0 0x0aa
#define R2057_LPF_IDACS_CORE0 0x0ab
#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0x0ac
#define R2057_TXBUF_GAIN_CORE0 0x0ad
#define R2057_AFELOOPBACK_AACI_RESP_CORE0 0x0ae
#define R2057_RXBUF_DEGEN_CORE0 0x0af
#define R2057_RXBB_SPARE2_CORE0 0x0b0
#define R2057_RXBB_SPARE1_CORE0 0x0b1
#define R2057_RSSI_MASTER_CORE0 0x0b2
#define R2057_W2_MASTER_CORE0 0x0b3
#define R2057_NB_MASTER_CORE0 0x0b4
#define R2057_W2_IDACS0_Q_CORE0 0x0b5
#define R2057_W2_IDACS1_Q_CORE0 0x0b6
#define R2057_W2_IDACS0_I_CORE0 0x0b7
#define R2057_W2_IDACS1_I_CORE0 0x0b8
#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0x0b9
#define R2057_NB_IDACS_Q_CORE0 0x0ba
#define R2057_NB_IDACS_I_CORE0 0x0bb
#define R2057_BACKUP4_CORE0 0x0c1
#define R2057_BACKUP3_CORE0 0x0c2
#define R2057_BACKUP2_CORE0 0x0c3
#define R2057_BACKUP1_CORE0 0x0c4
#define R2057_SPARE16_CORE0 0x0c5
#define R2057_SPARE15_CORE0 0x0c6
#define R2057_SPARE14_CORE0 0x0c7
#define R2057_SPARE13_CORE0 0x0c8
#define R2057_SPARE12_CORE0 0x0c9
#define R2057_SPARE11_CORE0 0x0ca
#define R2057_TX2G_BIAS_RESETS_CORE0 0x0cb
#define R2057_TX5G_BIAS_RESETS_CORE0 0x0cc
#define R2057_IQTEST_SEL_PU 0x0cd
#define R2057_XTAL_CONFIG2 0x0ce
#define R2057_BUFS_MISC_LPFBW_CORE0 0x0cf
#define R2057_TXLPF_RCCAL_CORE0 0x0d0
#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1
#define R2057_LPF_GAIN_CORE0 0x0d2
#define R2057_DACBUF_IDACS_BW_CORE0 0x0d3
/* MISC core 1 */
#define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4
#define R2057_TXGM_TXRF_PUS_CORE1 0x0d5
#define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6
#define R2057_TXGM_GAIN_CORE1 0x0db
#define R2057_TXGM2G_PKDET_PUS_CORE1 0x0dc
#define R2057_PAD2G_PTATS_CORE1 0x0dd
#define R2057_PAD2G_IDACS_CORE1 0x0de
#define R2057_PAD2G_BOOST_PU_CORE1 0x0df
#define R2057_PAD2G_CASCV_GAIN_CORE1 0x0e0
#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0x0e1
#define R2057_TXMIX2G_LODC_CORE1 0x0e2
#define R2057_PAD2G_TUNE_PUS_CORE1 0x0e3
#define R2057_IPA2G_GAIN_CORE1 0x0e4
#define R2057_TSSI2G_SPARE1_CORE1 0x0e5
#define R2057_TSSI2G_SPARE2_CORE1 0x0e6
#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0x0e7
#define R2057_IPA2G_IMAIN_CORE1 0x0e8
#define R2057_IPA2G_CASCONV_CORE1 0x0e9
#define R2057_IPA2G_CASCOFFV_CORE1 0x0ea
#define R2057_IPA2G_BIAS_FILTER_CORE1 0x0eb
#define R2057_TX5G_PKDET_CORE1 0x0ee
#define R2057_PGA_PTAT_TXGM5G_PU_CORE1 0x0ef
#define R2057_PAD5G_PTATS1_CORE1 0x0f0
#define R2057_PAD5G_CLASS_PTATS2_CORE1 0x0f1
#define R2057_PGA_BOOSTPTAT_IMAIN_CORE1 0x0f2
#define R2057_PAD5G_CASCV_IMAIN_CORE1 0x0f3
#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0x0f4
#define R2057_PGA_BOOST_TUNE_CORE1 0x0f5
#define R2057_PGA_GAIN_CORE1 0x0f6
#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0x0f7
#define R2057_TXMIX5G_BOOST_TUNE_CORE1 0x0f8
#define R2057_PAD5G_TUNE_MISC_PUS_CORE1 0x0f9
#define R2057_IPA5G_IAUX_CORE1 0x0fa
#define R2057_IPA5G_GAIN_CORE1 0x0fb
#define R2057_TSSI5G_SPARE1_CORE1 0x0fc
#define R2057_TSSI5G_SPARE2_CORE1 0x0fd
#define R2057_IPA5G_CASCOFFV_PU_CORE1 0x0fe
#define R2057_IPA5G_PTAT_CORE1 0x0ff
#define R2057_IPA5G_IMAIN_CORE1 0x100
#define R2057_IPA5G_CASCONV_CORE1 0x101
#define R2057_IPA5G_BIAS_FILTER_CORE1 0x102
#define R2057_PAD_BIAS_FILTER_BWS_CORE1 0x105
#define R2057_TR2G_CONFIG1_CORE1_NU 0x106
#define R2057_TR2G_CONFIG2_CORE1_NU 0x107
#define R2057_LNA5G_RFEN_CORE1 0x108
#define R2057_TR5G_CONFIG2_CORE1_NU 0x109
#define R2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a
#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b
#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c
#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d
#define R2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e
#define R2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f
#define R2057_LNA2_IAUX_PTAT_CORE1 0x110
#define R2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111
#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112
#define R2057_RXRFBIAS_BANDSEL_CORE1 0x113
#define R2057_TIA_CONFIG_CORE1 0x114
#define R2057_TIA_IQGAIN_CORE1 0x115
#define R2057_TIA_IBIAS2_CORE1 0x116
#define R2057_TIA_IBIAS1_CORE1 0x117
#define R2057_TIA_SPARE_Q_CORE1 0x118
#define R2057_TIA_SPARE_I_CORE1 0x119
#define R2057_RXMIX2G_PUS_CORE1 0x11a
#define R2057_RXMIX2G_VCMREFS_CORE1 0x11b
#define R2057_RXMIX2G_LODC_QI_CORE1 0x11c
#define R2057_W12G_BW_LNA2G_PUS_CORE1 0x11d
#define R2057_LNA2G_GAIN_CORE1 0x11e
#define R2057_LNA2G_TUNE_CORE1 0x11f
#define R2057_RXMIX5G_PUS_CORE1 0x120
#define R2057_RXMIX5G_VCMREFS_CORE1 0x121
#define R2057_RXMIX5G_LODC_QI_CORE1 0x122
#define R2057_W15G_BW_LNA5G_PUS_CORE1 0x123
#define R2057_LNA5G_GAIN_CORE1 0x124
#define R2057_LNA5G_TUNE_CORE1 0x125
#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126
#define R2057_RXBB_BIAS_MASTER_CORE1 0x127
#define R2057_RXBB_VGABUF_IDACS_CORE1 0x128
#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129
#define R2057_TXBUF_VINCM_CORE1 0x12a
#define R2057_TXBUF_IDACS_CORE1 0x12b
#define R2057_LPF_RESP_RXBUF_BW_CORE1 0x12c
#define R2057_RXBB_CC_CORE1 0x12d
#define R2057_RXBB_SPARE3_CORE1 0x12e
#define R2057_RXBB_RCCAL_HPC_CORE1 0x12f
#define R2057_LPF_IDACS_CORE1 0x130
#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131
#define R2057_TXBUF_GAIN_CORE1 0x132
#define R2057_AFELOOPBACK_AACI_RESP_CORE1 0x133
#define R2057_RXBUF_DEGEN_CORE1 0x134
#define R2057_RXBB_SPARE2_CORE1 0x135
#define R2057_RXBB_SPARE1_CORE1 0x136
#define R2057_RSSI_MASTER_CORE1 0x137
#define R2057_W2_MASTER_CORE1 0x138
#define R2057_NB_MASTER_CORE1 0x139
#define R2057_W2_IDACS0_Q_CORE1 0x13a
#define R2057_W2_IDACS1_Q_CORE1 0x13b
#define R2057_W2_IDACS0_I_CORE1 0x13c
#define R2057_W2_IDACS1_I_CORE1 0x13d
#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e
#define R2057_NB_IDACS_Q_CORE1 0x13f
#define R2057_NB_IDACS_I_CORE1 0x140
#define R2057_BACKUP4_CORE1 0x146
#define R2057_BACKUP3_CORE1 0x147
#define R2057_BACKUP2_CORE1 0x148
#define R2057_BACKUP1_CORE1 0x149
#define R2057_SPARE16_CORE1 0x14a
#define R2057_SPARE15_CORE1 0x14b
#define R2057_SPARE14_CORE1 0x14c
#define R2057_SPARE13_CORE1 0x14d
#define R2057_SPARE12_CORE1 0x14e
#define R2057_SPARE11_CORE1 0x14f
#define R2057_TX2G_BIAS_RESETS_CORE1 0x150
#define R2057_TX5G_BIAS_RESETS_CORE1 0x151
#define R2057_SPARE8_CORE1 0x152
#define R2057_SPARE7_CORE1 0x153
#define R2057_BUFS_MISC_LPFBW_CORE1 0x154
#define R2057_TXLPF_RCCAL_CORE1 0x155
#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156
#define R2057_LPF_GAIN_CORE1 0x157
#define R2057_DACBUF_IDACS_BW_CORE1 0x158
#define R2057_DACBUF_VINCM_CORE1 0x159
#define R2057_RCCAL_START_R1_Q1_P1 0x15a
#define R2057_RCCAL_X1 0x15b
#define R2057_RCCAL_TRC0 0x15c
#define R2057_RCCAL_TRC1 0x15d
#define R2057_RCCAL_DONE_OSCCAP 0x15e
#define R2057_RCCAL_N0_0 0x15f
#define R2057_RCCAL_N0_1 0x160
#define R2057_RCCAL_N1_0 0x161
#define R2057_RCCAL_N1_1 0x162
#define R2057_RCAL_STATUS 0x163
#define R2057_XTALPUOVR_PINCTRL 0x164
#define R2057_OVR_REG0 0x165
#define R2057_OVR_REG1 0x166
#define R2057_OVR_REG2 0x167
#define R2057_OVR_REG3 0x168
#define R2057_OVR_REG4 0x169
#define R2057_RCCAL_SCAP_VAL 0x16a
#define R2057_RCCAL_BCAP_VAL 0x16b
#define R2057_RCCAL_HPC_VAL 0x16c
#define R2057_RCCAL_OVERRIDES 0x16d
/* TX core 0 */
#define R2057_TX0_IQCAL_GAIN_BW 0x170
#define R2057_TX0_LOFT_FINE_I 0x171
#define R2057_TX0_LOFT_FINE_Q 0x172
#define R2057_TX0_LOFT_COARSE_I 0x173
#define R2057_TX0_LOFT_COARSE_Q 0x174
#define R2057_TX0_TX_SSI_MASTER 0x175
#define R2057_TX0_IQCAL_VCM_HG 0x176
#define R2057_TX0_IQCAL_IDAC 0x177
#define R2057_TX0_TSSI_VCM 0x178
#define R2057_TX0_TX_SSI_MUX 0x179
#define R2057_TX0_TSSIA 0x17a
#define R2057_TX0_TSSIG 0x17b
#define R2057_TX0_TSSI_MISC1 0x17c
#define R2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d
#define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e
#define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f
#define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180
/* TX core 1 */
#define R2057_TX1_IQCAL_GAIN_BW 0x190
#define R2057_TX1_LOFT_FINE_I 0x191
#define R2057_TX1_LOFT_FINE_Q 0x192
#define R2057_TX1_LOFT_COARSE_I 0x193
#define R2057_TX1_LOFT_COARSE_Q 0x194
#define R2057_TX1_TX_SSI_MASTER 0x195
#define R2057_TX1_IQCAL_VCM_HG 0x196
#define R2057_TX1_IQCAL_IDAC 0x197
#define R2057_TX1_TSSI_VCM 0x198
#define R2057_TX1_TX_SSI_MUX 0x199
#define R2057_TX1_TSSIA 0x19a
#define R2057_TX1_TSSIG 0x19b
#define R2057_TX1_TSSI_MISC1 0x19c
#define R2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d
#define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e
#define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f
#define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0
#define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1
#define R2057_AFE_SET_VCM_I_CORE0 0x1a2
#define R2057_AFE_SET_VCM_Q_CORE0 0x1a3
#define R2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4
#define R2057_AFE_STATUS_VCM_I_CORE0 0x1a5
#define R2057_AFE_STATUS_VCM_Q_CORE0 0x1a6
#define R2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7
#define R2057_AFE_SET_VCM_I_CORE1 0x1a8
#define R2057_AFE_SET_VCM_Q_CORE1 0x1a9
#define R2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa
#define R2057_AFE_STATUS_VCM_I_CORE1 0x1ab
#define R2057_AFE_STATUS_VCM_Q_CORE1 0x1ac
#define R2057v7_DACBUF_VINCM_CORE0 0x1ad
#define R2057v7_RCCAL_MASTER 0x1ae
#define R2057v7_TR2G_CONFIG3_CORE0_NU 0x1af
#define R2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0
#define R2057v7_LOGEN_PUS1 0x1b1
#define R2057v7_OVR_REG5 0x1b2
#define R2057v7_OVR_REG6 0x1b3
#define R2057v7_OVR_REG7 0x1b4
#define R2057v7_OVR_REG8 0x1b5
#define R2057v7_OVR_REG9 0x1b6
#define R2057v7_OVR_REG10 0x1b7
#define R2057v7_OVR_REG11 0x1b8
#define R2057v7_OVR_REG12 0x1b9
#define R2057v7_OVR_REG13 0x1ba
#define R2057v7_OVR_REG14 0x1bb
#define R2057v7_OVR_REG15 0x1bc
#define R2057v7_OVR_REG16 0x1bd
#define R2057v7_OVR_REG1 0x1be
#define R2057v7_OVR_REG18 0x1bf
#define R2057v7_OVR_REG19 0x1c0
#define R2057v7_OVR_REG20 0x1c1
#define R2057v7_OVR_REG21 0x1c2
#define R2057v7_OVR_REG2 0x1c3
#define R2057v7_OVR_REG23 0x1c4
#define R2057v7_OVR_REG24 0x1c5
#define R2057v7_OVR_REG25 0x1c6
#define R2057v7_OVR_REG26 0x1c7
#define R2057v7_OVR_REG27 0x1c8
#define R2057v7_OVR_REG28 0x1c9
#define R2057v7_IQTEST_SEL_PU2 0x1ca
#define R2057_VCM_MASK 0x7
struct bwn_nphy_chantabent_rev7 {
/* The channel frequency in MHz */
uint16_t freq;
/* Radio regs values on channelswitch */
uint8_t radio_vcocal_countval0;
uint8_t radio_vcocal_countval1;
uint8_t radio_rfpll_refmaster_sparextalsize;
uint8_t radio_rfpll_loopfilter_r1;
uint8_t radio_rfpll_loopfilter_c2;
uint8_t radio_rfpll_loopfilter_c1;
uint8_t radio_cp_kpd_idac;
uint8_t radio_rfpll_mmd0;
uint8_t radio_rfpll_mmd1;
uint8_t radio_vcobuf_tune;
uint8_t radio_logen_mx2g_tune;
uint8_t radio_logen_mx5g_tune;
uint8_t radio_logen_indbuf2g_tune;
uint8_t radio_logen_indbuf5g_tune;
uint8_t radio_txmix2g_tune_boost_pu_core0;
uint8_t radio_pad2g_tune_pus_core0;
uint8_t radio_pga_boost_tune_core0;
uint8_t radio_txmix5g_boost_tune_core0;
uint8_t radio_pad5g_tune_misc_pus_core0;
uint8_t radio_lna2g_tune_core0;
uint8_t radio_lna5g_tune_core0;
uint8_t radio_txmix2g_tune_boost_pu_core1;
uint8_t radio_pad2g_tune_pus_core1;
uint8_t radio_pga_boost_tune_core1;
uint8_t radio_txmix5g_boost_tune_core1;
uint8_t radio_pad5g_tune_misc_pus_core1;
uint8_t radio_lna2g_tune_core1;
uint8_t radio_lna5g_tune_core1;
/* PHY res values on channelswitch */
struct bwn_phy_n_sfo_cfg phy_regs;
};
struct bwn_nphy_chantabent_rev7_2g {
/* The channel frequency in MHz */
uint16_t freq;
/* Radio regs values on channelswitch */
uint8_t radio_vcocal_countval0;
uint8_t radio_vcocal_countval1;
uint8_t radio_rfpll_refmaster_sparextalsize;
uint8_t radio_rfpll_loopfilter_r1;
uint8_t radio_rfpll_loopfilter_c2;
uint8_t radio_rfpll_loopfilter_c1;
uint8_t radio_cp_kpd_idac;
uint8_t radio_rfpll_mmd0;
uint8_t radio_rfpll_mmd1;
uint8_t radio_vcobuf_tune;
uint8_t radio_logen_mx2g_tune;
uint8_t radio_logen_indbuf2g_tune;
uint8_t radio_txmix2g_tune_boost_pu_core0;
uint8_t radio_pad2g_tune_pus_core0;
uint8_t radio_lna2g_tune_core0;
uint8_t radio_txmix2g_tune_boost_pu_core1;
uint8_t radio_pad2g_tune_pus_core1;
uint8_t radio_lna2g_tune_core1;
/* PHY regs values on channelswitch */
struct bwn_phy_n_sfo_cfg phy_regs;
};
void r2057_upload_inittabs(struct bwn_mac *mac);
void r2057_get_chantabent_rev7(struct bwn_mac *mac, uint16_t freq,
const struct bwn_nphy_chantabent_rev7 **tabent_r7,
const struct bwn_nphy_chantabent_rev7_2g **tabent_r7_2g);
#endif /* IF_BWN_RADIO_2057_H_ */