Initial import of Ralink/Mediatek MIPS SoC support #4
UART drivers. - uart_dev_mtk.[ch] are the old-style Mediatek/Ralink-specific UART driver as also found in sys/mips/rt305x/uart_dev_rt305x.c, with minor improvements and FDT attachment enabled for the appropriate SoCs. - uart_dev_mtk_ns8250.c is the new-style ns16550a-compatible UART driver found in newer Mediatek SoCs. It uses the uart_dev_ns8250.c driver indirectly and is basically just a wrapper around it and only overrides its probe method. The reason I am not using the uart_dev_ns8250.c driver directly is because I have some code that does UART clock detection before initializing the UART, so that we don't need to hard-code the UART clock frequency in the dts files for each board. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5840
This commit is contained in:
parent
e56e179d55
commit
dc0996af4e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=297669
552
sys/mips/mediatek/uart_dev_mtk.c
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552
sys/mips/mediatek/uart_dev_mtk.c
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@ -0,0 +1,552 @@
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/* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
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/*-
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* Copyright (c) 2013, Alexander A. Mityaev <sansan@adm.ua>
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* Copyright (c) 2010 Aleksandr Rybalko.
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* Copyright (c) 2007 Oleksandr Tymoshenko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <sys/sysctl.h>
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#include <sys/kernel.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_cpu_fdt.h>
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#include <dev/uart/uart_bus.h>
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#include <mips/mediatek/uart_dev_mtk.h>
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#include <mips/mediatek/mtk_soc.h>
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#include <mips/mediatek/mtk_sysctl.h>
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#include "uart_if.h"
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/* Set some reference clock value. Real value will be taken from FDT */
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#define DEFAULT_RCLK (120 * 1000 * 1000)
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/*
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* Low-level UART interface.
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*/
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static int mtk_uart_probe(struct uart_bas *bas);
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static void mtk_uart_init(struct uart_bas *bas, int, int, int, int);
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static void mtk_uart_term(struct uart_bas *bas);
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static void mtk_uart_putc(struct uart_bas *bas, int);
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static int mtk_uart_rxready(struct uart_bas *bas);
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static int mtk_uart_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_mtk_ops = {
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.probe = mtk_uart_probe,
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.init = mtk_uart_init,
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.term = mtk_uart_term,
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.putc = mtk_uart_putc,
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.rxready = mtk_uart_rxready,
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.getc = mtk_uart_getc,
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};
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static int uart_output = 1;
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TUNABLE_INT("kern.uart_output", &uart_output);
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SYSCTL_INT(_kern, OID_AUTO, uart_output, CTLFLAG_RW,
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&uart_output, 0, "UART output enabled.");
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static int
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mtk_uart_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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mtk_uart_init(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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/* CLKDIV = 384000000/ 3/ 16/ br */
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/* for 384MHz CLKDIV = 8000000 / baudrate; */
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switch (databits) {
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case 5:
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databits = UART_LCR_5B;
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break;
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case 6:
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databits = UART_LCR_6B;
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break;
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case 7:
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databits = UART_LCR_7B;
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break;
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case 8:
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databits = UART_LCR_8B;
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break;
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default:
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/* Unsupported */
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return;
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}
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switch (parity) {
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case UART_PARITY_EVEN: parity = (UART_LCR_PEN|UART_LCR_EVEN); break;
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case UART_PARITY_ODD: parity = (UART_LCR_PEN); break;
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case UART_PARITY_NONE: parity = 0; break;
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/* Unsupported */
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default: return;
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}
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if (bas->rclk && baudrate) {
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uart_setreg(bas, UART_CDDL_REG, bas->rclk/16/baudrate);
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uart_barrier(bas);
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}
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uart_setreg(bas, UART_LCR_REG, databits |
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(stopbits==1?0:UART_LCR_STB_15) |
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parity);
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uart_barrier(bas);
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}
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static void
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mtk_uart_term(struct uart_bas *bas)
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{
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uart_setreg(bas, UART_MCR_REG, 0);
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uart_barrier(bas);
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}
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static void
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mtk_uart_putc(struct uart_bas *bas, int c)
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{
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char chr;
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if (!uart_output) return;
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chr = c;
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while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
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uart_setreg(bas, UART_TX_REG, c);
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uart_barrier(bas);
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while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
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}
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static int
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mtk_uart_rxready(struct uart_bas *bas)
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{
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if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)
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return (1);
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return (0);
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}
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static int
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mtk_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {
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uart_unlock(hwmtx);
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DELAY(10);
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uart_lock(hwmtx);
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}
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c = uart_getreg(bas, UART_RX_REG);
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uart_unlock(hwmtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct uart_mtk_softc {
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struct uart_softc base;
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uint8_t ier_mask;
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uint8_t ier;
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};
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static int mtk_uart_bus_attach(struct uart_softc *);
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static int mtk_uart_bus_detach(struct uart_softc *);
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static int mtk_uart_bus_flush(struct uart_softc *, int);
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static int mtk_uart_bus_getsig(struct uart_softc *);
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static int mtk_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int mtk_uart_bus_ipend(struct uart_softc *);
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static int mtk_uart_bus_param(struct uart_softc *, int, int, int, int);
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static int mtk_uart_bus_probe(struct uart_softc *);
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static int mtk_uart_bus_receive(struct uart_softc *);
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static int mtk_uart_bus_setsig(struct uart_softc *, int);
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static int mtk_uart_bus_transmit(struct uart_softc *);
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static void mtk_uart_bus_grab(struct uart_softc *);
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static void mtk_uart_bus_ungrab(struct uart_softc *);
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static kobj_method_t uart_mtk_methods[] = {
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KOBJMETHOD(uart_attach, mtk_uart_bus_attach),
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KOBJMETHOD(uart_detach, mtk_uart_bus_detach),
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KOBJMETHOD(uart_flush, mtk_uart_bus_flush),
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KOBJMETHOD(uart_getsig, mtk_uart_bus_getsig),
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KOBJMETHOD(uart_ioctl, mtk_uart_bus_ioctl),
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KOBJMETHOD(uart_ipend, mtk_uart_bus_ipend),
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KOBJMETHOD(uart_param, mtk_uart_bus_param),
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KOBJMETHOD(uart_probe, mtk_uart_bus_probe),
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KOBJMETHOD(uart_receive, mtk_uart_bus_receive),
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KOBJMETHOD(uart_setsig, mtk_uart_bus_setsig),
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KOBJMETHOD(uart_transmit, mtk_uart_bus_transmit),
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KOBJMETHOD(uart_grab, mtk_uart_bus_grab),
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KOBJMETHOD(uart_ungrab, mtk_uart_bus_ungrab),
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{ 0, 0 }
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};
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struct uart_class uart_mtk_class = {
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"uart_mtk",
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uart_mtk_methods,
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sizeof(struct uart_mtk_softc),
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.uc_ops = &uart_mtk_ops,
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.uc_range = 1, /* use hinted range */
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.uc_rclk = 0
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};
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static struct ofw_compat_data compat_data[] = {
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{ "ralink,rt2880-uart", (uintptr_t)&uart_mtk_class },
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{ "ralink,rt3050-uart", (uintptr_t)&uart_mtk_class },
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{ "ralink,rt3352-uart", (uintptr_t)&uart_mtk_class },
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{ "ralink,rt3883-uart", (uintptr_t)&uart_mtk_class },
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{ "ralink,rt5350-uart", (uintptr_t)&uart_mtk_class },
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{ "ralink,mt7620a-uart", (uintptr_t)&uart_mtk_class },
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{ NULL, (uintptr_t)NULL },
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};
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UART_FDT_CLASS_AND_DEVICE(compat_data);
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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/*
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* Disable TX interrupt. uart should be locked
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*/
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static __inline void
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mtk_uart_disable_txintr(struct uart_softc *sc)
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{
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struct uart_bas *bas = &sc->sc_bas;
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uint8_t cr;
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cr = uart_getreg(bas, UART_IER_REG);
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cr &= ~UART_IER_ETBEI;
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uart_setreg(bas, UART_IER_REG, cr);
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uart_barrier(bas);
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}
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/*
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* Enable TX interrupt. uart should be locked
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*/
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static __inline void
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mtk_uart_enable_txintr(struct uart_softc *sc)
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{
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struct uart_bas *bas = &sc->sc_bas;
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uint8_t cr;
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cr = uart_getreg(bas, UART_IER_REG);
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cr |= UART_IER_ETBEI;
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uart_setreg(bas, UART_IER_REG, cr);
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uart_barrier(bas);
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}
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static int
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mtk_uart_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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struct uart_devinfo *di;
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struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
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bas = &sc->sc_bas;
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if (!bas->rclk) {
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bas->rclk = mtk_soc_get_uartclk();
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}
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if (sc->sc_sysdev != NULL) {
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di = sc->sc_sysdev;
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mtk_uart_init(bas, di->baudrate, di->databits, di->stopbits,
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di->parity);
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} else {
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mtk_uart_init(bas, 57600, 8, 1, 0);
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}
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sc->sc_rxfifosz = 16;
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sc->sc_txfifosz = 16;
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(void)mtk_uart_bus_getsig(sc);
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/* Enable FIFO */
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uart_setreg(bas, UART_FCR_REG,
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uart_getreg(bas, UART_FCR_REG) |
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UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
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uart_barrier(bas);
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/* Enable interrupts */
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usc->ier_mask = 0xf0;
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uart_setreg(bas, UART_IER_REG,
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UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
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uart_barrier(bas);
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return (0);
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}
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static int
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mtk_uart_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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mtk_uart_bus_flush(struct uart_softc *sc, int what)
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{
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struct uart_bas *bas = &sc->sc_bas;
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uint32_t fcr = uart_getreg(bas, UART_FCR_REG);
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if (what & UART_FLUSH_TRANSMITTER) {
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uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
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uart_barrier(bas);
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}
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if (what & UART_FLUSH_RECEIVER) {
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uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST);
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uart_barrier(bas);
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}
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uart_setreg(bas, UART_FCR_REG, fcr);
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uart_barrier(bas);
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return (0);
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}
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static int
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mtk_uart_bus_getsig(struct uart_softc *sc)
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{
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uint32_t new, old, sig;
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uint8_t bes;
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return(0);
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do {
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old = sc->sc_hwsig;
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sig = old;
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uart_lock(sc->sc_hwmtx);
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bes = uart_getreg(&sc->sc_bas, UART_MSR_REG);
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uart_unlock(sc->sc_hwmtx);
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/* XXX: chip can show delta */
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SIGCHG(bes & UART_MSR_CTS, sig, SER_CTS, SER_DCTS);
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SIGCHG(bes & UART_MSR_DCD, sig, SER_DCD, SER_DDCD);
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SIGCHG(bes & UART_MSR_DSR, sig, SER_DSR, SER_DDSR);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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}
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static int
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mtk_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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int baudrate, divisor, error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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/* TODO: Send BREAK */
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break;
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case UART_IOCTL_BAUD:
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divisor = uart_getreg(bas, UART_CDDL_REG);
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baudrate = bas->rclk / (divisor * 16);
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*(int*)data = baudrate;
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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mtk_uart_bus_ipend(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ipend;
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uint8_t iir, lsr, msr;
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// breakpoint();
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bas = &sc->sc_bas;
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ipend = 0;
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uart_lock(sc->sc_hwmtx);
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iir = uart_getreg(&sc->sc_bas, UART_IIR_REG);
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lsr = uart_getreg(&sc->sc_bas, UART_LSR_REG);
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uart_setreg(&sc->sc_bas, UART_LSR_REG, lsr);
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msr = uart_getreg(&sc->sc_bas, UART_MSR_REG);
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uart_setreg(&sc->sc_bas, UART_MSR_REG, msr);
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if (iir & UART_IIR_INTP) {
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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switch ((iir >> 1) & 0x07) {
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case UART_IIR_ID_THRE:
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ipend |= SER_INT_TXIDLE;
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break;
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case UART_IIR_ID_DR2:
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mtk_uart_bus_flush(sc, UART_FLUSH_RECEIVER);
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/* passthrough */
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case UART_IIR_ID_DR:
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ipend |= SER_INT_RXREADY;
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break;
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case UART_IIR_ID_MST:
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case UART_IIR_ID_LINESTATUS:
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ipend |= SER_INT_SIGCHG;
|
||||
if (lsr & UART_LSR_BI)
|
||||
ipend |= SER_INT_BREAK;
|
||||
if (lsr & UART_LSR_OE)
|
||||
ipend |= SER_INT_OVERRUN;
|
||||
break;
|
||||
default:
|
||||
/* XXX: maybe return error here */
|
||||
break;
|
||||
}
|
||||
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
|
||||
return (ipend);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
||||
int stopbits, int parity)
|
||||
{
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
mtk_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_uart_bus_probe(struct uart_softc *sc)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = mtk_uart_probe(&sc->sc_bas);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
device_set_desc(sc->sc_dev, "MTK UART Controller");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_uart_bus_receive(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_bas *bas;
|
||||
int xc;
|
||||
uint8_t lsr;
|
||||
|
||||
bas = &sc->sc_bas;
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
lsr = uart_getreg(bas, UART_LSR_REG);
|
||||
while ((lsr & UART_LSR_DR)) {
|
||||
if (uart_rx_full(sc)) {
|
||||
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
||||
break;
|
||||
}
|
||||
xc = 0;
|
||||
xc = uart_getreg(bas, UART_RX_REG);
|
||||
if (lsr & UART_LSR_FE)
|
||||
xc |= UART_STAT_FRAMERR;
|
||||
if (lsr & UART_LSR_PE)
|
||||
xc |= UART_STAT_PARERR;
|
||||
if (lsr & UART_LSR_OE)
|
||||
xc |= UART_STAT_OVERRUN;
|
||||
uart_barrier(bas);
|
||||
uart_rx_put(sc, xc);
|
||||
lsr = uart_getreg(bas, UART_LSR_REG);
|
||||
}
|
||||
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_uart_bus_setsig(struct uart_softc *sc, int sig)
|
||||
{
|
||||
/* TODO: implement (?) */
|
||||
return (sig);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_uart_bus_transmit(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_bas *bas = &sc->sc_bas;
|
||||
int i;
|
||||
|
||||
if (!uart_output) return (0);
|
||||
|
||||
bas = &sc->sc_bas;
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
while ((uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE) == 0);
|
||||
mtk_uart_enable_txintr(sc);
|
||||
for (i = 0; i < sc->sc_txdatasz; i++) {
|
||||
uart_setreg(bas, UART_TX_REG, sc->sc_txbuf[i]);
|
||||
uart_barrier(bas);
|
||||
}
|
||||
sc->sc_txbusy = 1;
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
mtk_uart_bus_grab(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_bas *bas = &sc->sc_bas;
|
||||
struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
|
||||
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
usc->ier = uart_getreg(bas, UART_IER_REG);
|
||||
uart_setreg(bas, UART_IER_REG, usc->ier & usc->ier_mask);
|
||||
uart_barrier(bas);
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
}
|
||||
|
||||
void
|
||||
mtk_uart_bus_ungrab(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
|
||||
struct uart_bas *bas = &sc->sc_bas;
|
||||
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
uart_setreg(bas, UART_IER_REG, usc->ier);
|
||||
uart_barrier(bas);
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
}
|
126
sys/mips/mediatek/uart_dev_mtk.h
Normal file
126
sys/mips/mediatek/uart_dev_mtk.h
Normal file
@ -0,0 +1,126 @@
|
||||
/*-
|
||||
* Copyright (c) 2010 Aleksandr Rybalko.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
* 3. The names of the authors may not be used to endorse or promote
|
||||
* products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
|
||||
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
|
||||
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef _MTKUART_H
|
||||
#define _MTKUART_H
|
||||
|
||||
#undef uart_getreg
|
||||
#undef uart_setreg
|
||||
#define uart_getreg(bas, reg) \
|
||||
bus_space_read_4((bas)->bst, (bas)->bsh, reg)
|
||||
#define uart_setreg(bas, reg, value) \
|
||||
bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
|
||||
|
||||
/* UART registers */
|
||||
#define UART_RX_REG 0x00
|
||||
#define UART_TX_REG 0x04
|
||||
|
||||
#define UART_IER_REG 0x08
|
||||
#define UART_IER_EDSSI (1<<3) /* Only full UART */
|
||||
#define UART_IER_ELSI (1<<2)
|
||||
#define UART_IER_ETBEI (1<<1)
|
||||
#define UART_IER_ERBFI (1<<0)
|
||||
|
||||
#define UART_IIR_REG 0x0c
|
||||
#define UART_IIR_RXFIFO (1<<7)
|
||||
#define UART_IIR_TXFIFO (1<<6)
|
||||
#define UART_IIR_ID_MST 0
|
||||
#define UART_IIR_ID_THRE 1
|
||||
#define UART_IIR_ID_DR 2
|
||||
#define UART_IIR_ID_LINESTATUS 3
|
||||
#define UART_IIR_ID_DR2 6
|
||||
#define UART_IIR_ID_SHIFT 1
|
||||
#define UART_IIR_ID_MASK 0x0000000e
|
||||
#define UART_IIR_INTP (1<<0)
|
||||
|
||||
#define UART_FCR_REG 0x10
|
||||
#define UART_FCR_RXTGR_1 (0<<6)
|
||||
#define UART_FCR_RXTGR_4 (1<<6)
|
||||
#define UART_FCR_RXTGR_8 (2<<6)
|
||||
#define UART_FCR_RXTGR_12 (3<<6)
|
||||
#define UART_FCR_TXTGR_1 (0<<4)
|
||||
#define UART_FCR_TXTGR_4 (1<<4)
|
||||
#define UART_FCR_TXTGR_8 (2<<4)
|
||||
#define UART_FCR_TXTGR_12 (3<<4)
|
||||
#define UART_FCR_DMA (1<<3)
|
||||
#define UART_FCR_TXRST (1<<2)
|
||||
#define UART_FCR_RXRST (1<<1)
|
||||
#define UART_FCR_FIFOEN (1<<0)
|
||||
|
||||
#define UART_LCR_REG 0x14
|
||||
#define UART_LCR_DLAB (1<<7)
|
||||
#define UART_LCR_BRK (1<<6)
|
||||
#define UART_LCR_FPAR (1<<5)
|
||||
#define UART_LCR_EVEN (1<<4)
|
||||
#define UART_LCR_PEN (1<<3)
|
||||
#define UART_LCR_STB_15 (1<<2)
|
||||
#define UART_LCR_5B 0
|
||||
#define UART_LCR_6B 1
|
||||
#define UART_LCR_7B 2
|
||||
#define UART_LCR_8B 3
|
||||
|
||||
#define UART_MCR_REG 0x18
|
||||
#define UART_MCR_LOOP (1<<4)
|
||||
#define UART_MCR_OUT2_L (1<<3) /* Only full UART */
|
||||
#define UART_MCR_OUT1_L (1<<2) /* Only full UART */
|
||||
#define UART_MCR_RTS_L (1<<1) /* Only full UART */
|
||||
#define UART_MCR_DTR_L (1<<0) /* Only full UART */
|
||||
|
||||
#define UART_LSR_REG 0x1c
|
||||
#define UART_LSR_ERINF (1<<7)
|
||||
#define UART_LSR_TEMT (1<<6)
|
||||
#define UART_LSR_THRE (1<<5)
|
||||
#define UART_LSR_BI (1<<4)
|
||||
#define UART_LSR_FE (1<<3)
|
||||
#define UART_LSR_PE (1<<2)
|
||||
#define UART_LSR_OE (1<<1)
|
||||
#define UART_LSR_DR (1<<0)
|
||||
|
||||
#define UART_MSR_REG 0x20 /* Only full UART */
|
||||
#define UART_MSR_DCD (1<<7) /* Only full UART */
|
||||
#define UART_MSR_RI (1<<6) /* Only full UART */
|
||||
#define UART_MSR_DSR (1<<5) /* Only full UART */
|
||||
#define UART_MSR_CTS (1<<4) /* Only full UART */
|
||||
#define UART_MSR_DDCD (1<<3) /* Only full UART */
|
||||
#define UART_MSR_TERI (1<<2) /* Only full UART */
|
||||
#define UART_MSR_DDSR (1<<1) /* Only full UART */
|
||||
#define UART_MSR_DCTS (1<<0) /* Only full UART */
|
||||
|
||||
#define UART_CDDL_REG 0x28
|
||||
#define UART_CDDLL_REG 0x2c
|
||||
#define UART_CDDLH_REG 0x30
|
||||
|
||||
#define UART_IFCTL_REG 0x34
|
||||
#define UART_IFCTL_IFCTL (1<<0)
|
||||
|
||||
int uart_cnattach(void);
|
||||
#endif /* _MTKUART_H */
|
113
sys/mips/mediatek/uart_dev_mtk_ns8250.c
Normal file
113
sys/mips/mediatek/uart_dev_mtk_ns8250.c
Normal file
@ -0,0 +1,113 @@
|
||||
/*-
|
||||
* Copyright (c) 2013 Ian Lepore
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "opt_platform.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/sysctl.h>
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <mips/mediatek/mtk_soc.h>
|
||||
#include <mips/mediatek/mtk_sysctl.h>
|
||||
|
||||
#include <dev/fdt/fdt_common.h>
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include <dev/uart/uart.h>
|
||||
#include <dev/uart/uart_cpu.h>
|
||||
#include <dev/uart/uart_cpu_fdt.h>
|
||||
#include <dev/uart/uart_bus.h>
|
||||
#include <dev/uart/uart_dev_ns8250.h>
|
||||
|
||||
#include "uart_if.h"
|
||||
|
||||
/*
|
||||
* High-level UART interface.
|
||||
*/
|
||||
static struct uart_class uart_mtk_ns8250_class;
|
||||
static int mtk_ns8250_bus_probe(struct uart_softc *);
|
||||
|
||||
static kobj_method_t mtk_ns8250_methods[] = {
|
||||
KOBJMETHOD(uart_probe, mtk_ns8250_bus_probe),
|
||||
|
||||
KOBJMETHOD(uart_attach, ns8250_bus_attach),
|
||||
KOBJMETHOD(uart_detach, ns8250_bus_detach),
|
||||
KOBJMETHOD(uart_flush, ns8250_bus_flush),
|
||||
KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
|
||||
KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
|
||||
KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
|
||||
KOBJMETHOD(uart_param, ns8250_bus_param),
|
||||
KOBJMETHOD(uart_receive, ns8250_bus_receive),
|
||||
KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
|
||||
KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
|
||||
KOBJMETHOD_END
|
||||
};
|
||||
|
||||
static struct uart_class uart_mtk_ns8250_class = {
|
||||
"mtk8250",
|
||||
mtk_ns8250_methods,
|
||||
sizeof(struct ns8250_softc),
|
||||
.uc_ops = &uart_ns8250_ops,
|
||||
.uc_range = 1, /* use hinted range */
|
||||
.uc_rclk = 0,
|
||||
.uc_rshift = 2
|
||||
};
|
||||
|
||||
static struct ofw_compat_data compat_data[] = {
|
||||
{ "mtk,ns16550a", (uintptr_t)&uart_mtk_ns8250_class },
|
||||
{ "ns16550a", (uintptr_t)&uart_mtk_ns8250_class },
|
||||
{ NULL, (uintptr_t)NULL },
|
||||
};
|
||||
UART_FDT_CLASS_AND_DEVICE(compat_data);
|
||||
|
||||
static int
|
||||
mtk_ns8250_bus_probe(struct uart_softc *sc)
|
||||
{
|
||||
int status;
|
||||
|
||||
if (!ofw_bus_status_okay(sc->sc_dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (ofw_bus_search_compatible(sc->sc_dev, compat_data)->ocd_data ==
|
||||
(uintptr_t)NULL)
|
||||
return (ENXIO);
|
||||
|
||||
sc->sc_bas.rclk = mtk_soc_get_uartclk();
|
||||
|
||||
status = ns8250_bus_probe(sc);
|
||||
if (status == 0)
|
||||
device_set_desc(sc->sc_dev, "MTK UART Controller (ns16550a)");
|
||||
|
||||
return (status);
|
||||
}
|
Loading…
Reference in New Issue
Block a user