Merge the Cavium Octeon SDK 2.3.0 Simple Executive code and update FreeBSD to

make use of it where possible.

This primarily brings in support for newer hardware, and FreeBSD is not yet
able to support the abundance of IRQs on new hardware and many features in the
Ethernet driver.

Because of the changes to IRQs in the Simple Executive, we have to maintain our
own list of Octeon IRQs now, which probably can be pared-down and be specific
to the CIU interrupt unit soon, and when other interrupt mechanisms are added
they can maintain their own definitions.

Remove unmasking of interrupts from within the UART device now that the
function used is no longer present in the Simple Executive.  The unmasking
seems to have been gratuitous as this is more properly handled by the buses
above the UART device, and seems to work on that basis.

sys/contrib/octeon-sdk/README.txt

@@ -0,0 +1,43 @@
+Readme for the OCTEON Executive Library
+
+
+The OCTEON Executive Library provides runtime support and hardware 
+abstraction for the OCTEON processor.  The executive is composed of the 
+libcvmx.a library as well as header files that provide  
+functionality with inline functions.
+
+
+Usage:
+
+The libcvmx.a library is built for every application as part of the
+application build. (Please refer to the 'related pages' section of the 
+HTML documentation for more information on the build system.)  
+Applications using the executive should include the header files from
+$OCTEON_ROOT/target/include and link against the library that is built in 
+the local obj directory. Each file using the executive 
+should include the following two header files in order:
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+
+The cvmx-config.h file contains configuration information for the 
+executive and is generated by the cvmx-config script from an 
+'executive-config.h' file. A sample version of this file is provided 
+in the executive directory as 'executive-config.h.template'.  
+
+Copy this file to 'executive-config.h' into the 'config' subdirectory 
+of the application directory and customize as required by the application. 
+Applications that don't use any simple executive functionality can omit 
+the cvmx-config.h header file. Please refer to the examples for a 
+demonstration of where to put the executive-config.h file and for an
+example of generated cvmx-config.h.
+
+For file specific information please see the documentation within the 
+source files or the HTML documentation provided in docs/html/index.html.
+The HTML documentation is automatically generated by Doxygen from the 
+source files.
+
+
+
+==========================================================================
+Please see the release notes for version specific information.

sys/contrib/octeon-sdk/cvmip.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,11 +46,11 @@
 /**
  * @file
  *
- * Cavium Networks Internet Protocol (IP)
+ * Cavium Inc. Internet Protocol (IP)
  *
  * Definitions for the Internet Protocol (IP) support.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-abi.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -39,21 +39,25 @@
 
 
 
-
-
-
-
 /**
  * @file
  *
  * This file defines macros for use in determining the current calling ABI.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
 */
 
 #ifndef __CVMX_ABI_H__
 #define __CVMX_ABI_H__
 
+#if defined(__FreeBSD__) && defined(_KERNEL)
+#include <machine/endian.h>
+#else
+#ifndef __U_BOOT__
+#include <endian.h>
+#endif
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -87,6 +91,20 @@ extern "C" {
     #endif
 #endif
 
+/* For compatibility with Linux definitions... */
+#if __BYTE_ORDER == __BIG_ENDIAN
+# ifndef __BIG_ENDIAN_BITFIELD
+#  define __BIG_ENDIAN_BITFIELD
+# endif
+#else
+# ifndef __LITTLE_ENDIAN_BITFIELD
+#  define __LITTLE_ENDIAN_BITFIELD
+# endif
+#endif
+#if defined(__BIG_ENDIAN_BITFIELD) && defined(__LITTLE_ENDIAN_BITFIELD)
+# error Cannot define both __BIG_ENDIAN_BITFIELD and __LITTLE_ENDIAN_BITFIELD
+#endif
+
 #ifdef	__cplusplus
 }
 #endif

sys/contrib/octeon-sdk/cvmx-access-native.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -183,12 +183,6 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
         cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
 
 #ifdef CVMX_BUILD_FOR_UBOOT
-#if !CONFIG_OCTEON_UBOOT_TLB
-    if (physical_address >= 0x80000000)
-        return NULL;
-    else
-        return CASTPTR(void, (physical_address & 0x7FFFFFFF));
-#endif
 
     /* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
     ** which can have a physical address above the 32 bit address space.  1-1 mappings are used
@@ -251,8 +245,9 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
         2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
     if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
         return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
-    else if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && (physical_address >= 0x410000000ull) &&
-                                                       (physical_address < 0x420000000ull))
+    else if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+              && (physical_address >= 0x410000000ull)
+              && (physical_address < 0x420000000ull))
         return CASTPTR(void, physical_address - 0x400000000ull);
     else
         return CASTPTR(void, physical_address);

sys/contrib/octeon-sdk/cvmx-access.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-address.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,10 @@
 #ifndef __CVMX_ADDRESS_H__
 #define __CVMX_ADDRESS_H__
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-abi.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -233,6 +237,7 @@ typedef union {
 #define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
 #define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
 #define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
+#define CVMX_OCT_DID_TAG_TAG5       CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL)
 #define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
 #define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
 #define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
@@ -245,6 +250,14 @@ typedef union {
 #define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
 #define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
 
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef CVMX_ABI_N32
+#define UNMAPPED_PTR(x) ( (1U << 31) | x )
+#else
+#define UNMAPPED_PTR(x) ( (1ULL << 63) | x )
+#endif
+#endif
+
 #ifdef	__cplusplus
 }
 #endif

sys/contrib/octeon-sdk/cvmx-app-hotplug.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,9 +48,12 @@
 
 #include "cvmx-app-hotplug.h"
 #include "cvmx-spinlock.h"
+#include "cvmx-debug.h"
 
 //#define DEBUG 1
 
+static cvmx_app_hotplug_global_t *hotplug_global_ptr = 0;
+
 #ifndef CVMX_BUILD_FOR_LINUX_USER
 
 static CVMX_SHARED cvmx_spinlock_t cvmx_app_hotplug_sync_lock = { CVMX_SPINLOCK_UNLOCKED_VAL };
@@ -61,6 +64,11 @@ static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32],
 static void __cvmx_app_hotplug_sync(void);
 static void __cvmx_app_hotplug_reset(void);
 
+/* Declaring this array here is a compile time check to ensure that the
+   size of  cvmx_app_hotplug_info_t is 1024. If the size is not 1024
+   the size of the array will be -1 and this results in a compilation
+   error */
+char __hotplug_info_check[(sizeof(cvmx_app_hotplug_info_t) == 1024) ? 1 : -1];
 /**
  * This routine registers an application for hotplug. It installs a handler for
  * any incoming shutdown request. It also registers a callback routine from the
@@ -90,7 +98,7 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
     cvmx_app_hotplug_info_ptr->shutdown_callback = CAST64(fn);
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n", 
+    printf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n", 
                   cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid);
 #endif
 
@@ -100,7 +108,82 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
 }
 
 /**
- * Activate the current application core for receiving hotplug shutdown requests. 
+ * This routine deprecates the the cvmx_app_hotplug_register method. This
+ * registers application for hotplug and the application will have CPU
+ * hotplug callbacks. Various callbacks are specified in cb.
+ * cvmx_app_hotplug_callbacks_t documents the callbacks
+ *
+ * This routine only needs to be called once per application.
+ *
+ * @param cb      Callback routine from the application.
+ * @param arg     Argument to the application callback routins
+ * @param app_shutdown   When set to 1 the application will invoke core_shutdown
+                         on each core. When set to 0 core shutdown will be
+                         called invoked automatically after invoking the
+                         application callback.
+ * @return        Return index of app on success, -1 on failure
+ *
+ */
+int cvmx_app_hotplug_register_cb(cvmx_app_hotplug_callbacks_t *cb, void* arg,
+                                 int app_shutdown)
+{
+    cvmx_app_hotplug_info_t *app_info;
+
+    /* Find the list of applications launched by bootoct utility. */
+    app_info = cvmx_app_hotplug_get_info(cvmx_sysinfo_get()->core_mask);
+    cvmx_app_hotplug_info_ptr = app_info;
+    if (!app_info)
+    {
+        /* Application not launched by bootoct? */
+        printf("ERROR: cmvx_app_hotplug_register() failed\n");
+        return -1;
+    }
+    /* Register the callback */
+    app_info->data = CAST64(arg);
+    app_info->shutdown_callback  = CAST64(cb->shutdown_callback);
+    app_info->cores_added_callback = CAST64(cb->cores_added_callback);
+    app_info->cores_removed_callback = CAST64(cb->cores_removed_callback);
+    app_info->unplug_callback = CAST64(cb->unplug_core_callback);
+    app_info->hotplug_start = CAST64(cb->hotplug_start);
+    app_info->app_shutdown = app_shutdown;
+#ifdef DEBUG
+    printf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n",
+           app_info->coremask, app_info->valid);
+#endif
+
+    cvmx_interrupt_register(CVMX_IRQ_MBOX0, __cvmx_app_hotplug_shutdown, NULL);
+    return 0;
+
+}
+
+void cvmx_app_hotplug_remove_self_from_core_mask(void)
+{
+    int core = cvmx_get_core_num();
+    uint32_t core_mask = 1ull << core;
+
+    cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
+    cvmx_app_hotplug_info_ptr->coremask = cvmx_app_hotplug_info_ptr->coremask & ~core_mask ;
+    cvmx_app_hotplug_info_ptr->hotplug_activated_coremask =
+        cvmx_app_hotplug_info_ptr->hotplug_activated_coremask & ~core_mask ;
+    cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
+}
+
+
+
+/**
+*  Returns 1 if the running core is being unplugged, else it returns 0.
+*/
+int is_core_being_unplugged(void)
+{
+    if (cvmx_app_hotplug_info_ptr->unplug_cores &
+        (1ull << cvmx_get_core_num()))
+        return 1;
+    return 0;
+}
+
+
+/**
+ * Activate the current application core for receiving hotplug shutdown requests.
  *
  * This routine makes sure that each core belonging to the application is enabled 
  * to receive the shutdown notification and also provides a barrier sync to make
@@ -108,25 +191,41 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
  */
 int cvmx_app_hotplug_activate(void)
 {
-    /* Make sure all application cores are activating */
-    __cvmx_app_hotplug_sync();
+    uint64_t cnt = 0;
+    uint64_t cnt_interval = 10000000;
 
+    while (!cvmx_app_hotplug_info_ptr) 
+    {
+        cnt++;
+        if ((cnt % cnt_interval) == 0)
+            printf("waiting for cnt=%lld\n", (unsigned long long)cnt);
+    }
+
+    if (cvmx_app_hotplug_info_ptr->hplugged_cores & (1ull << cvmx_get_core_num()))
+    {
+#ifdef DEBUG
+        printf("core=%d : is being hotplugged \n", cvmx_get_core_num());
+#endif
+        cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+        sys_info_ptr->core_mask |= 1ull << cvmx_get_core_num();
+    }
+    else
+    {
+        __cvmx_app_hotplug_sync();
+    }
     cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
-
     if (!cvmx_app_hotplug_info_ptr)
     {
         cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
         printf("ERROR: This application is not registered for hotplug\n");
-	return -1;
+        return -1;
     }
-
     /* Enable the interrupt before we mark the core as activated */
     cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
-
-    cvmx_app_hotplug_info_ptr->hotplug_activated_coremask |= (1<<cvmx_get_core_num());
+    cvmx_app_hotplug_info_ptr->hotplug_activated_coremask |= (1ull<<cvmx_get_core_num());
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_app_hotplug_activate(): coremask 0x%x valid %d sizeof %d\n", 
+    printf("cvmx_app_hotplug_activate(): coremask 0x%x valid %d sizeof %d\n", 
                  cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid, 
                  sizeof(*cvmx_app_hotplug_info_ptr));
 #endif
@@ -180,75 +279,196 @@ void cvmx_app_hotplug_shutdown_enable(void)
     cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
 }
 
+/**
+*  Request shutdown of the currently running core. Should be
+*  called by the application when it has been registered with
+*  app_shutdown option set to 1.
+*/
+void cvmx_app_hotplug_core_shutdown(void)
+{
+    uint32_t flags;
+    if (cvmx_app_hotplug_info_ptr->shutdown_cores)
+    {
+        cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+       __cvmx_app_hotplug_sync();
+        if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+        {
+            bzero(cvmx_app_hotplug_info_ptr,
+                  sizeof(*cvmx_app_hotplug_info_ptr));
+            #ifdef DEBUG
+            printf("__cvmx_app_hotplug_shutdown(): setting shutdown done! \n");
+            #endif
+            cvmx_app_hotplug_info_ptr->shutdown_done = 1;
+        }
+        /* Tell the debugger that this application is finishing.  */
+        cvmx_debug_finish ();
+        flags = cvmx_interrupt_disable_save();
+        __cvmx_app_hotplug_sync();
+        /* Reset the core */
+        __cvmx_app_hotplug_reset();
+    }
+    else
+    {
+        cvmx_sysinfo_remove_self_from_core_mask();
+        cvmx_app_hotplug_remove_self_from_core_mask();
+        flags = cvmx_interrupt_disable_save();
+        __cvmx_app_hotplug_reset();
+    }
+}
+
 /*
- * ISR for the incoming shutdown request interrupt. 
+ * ISR for the incoming shutdown request interrupt.
  */
-static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32], void *user_arg)
+static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32],
+                                        void *user_arg)
 {
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
-    uint32_t flags;
+    uint64_t mbox;
+    cvmx_app_hotplug_info_t *ai = cvmx_app_hotplug_info_ptr;
+    int dbg = 0;
 
+#ifdef DEBUG
+    dbg = 1;
+#endif
     cvmx_interrupt_mask_irq(CVMX_IRQ_MBOX0);
 
+    mbox = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()));
     /* Clear the interrupt */
-    cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 1);
+    cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), mbox);
 
     /* Make sure the write above completes */
     cvmx_read_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()));
 
+
     if (!cvmx_app_hotplug_info_ptr)
     {
         printf("ERROR: Application is not registered for hotplug!\n");
         return;
     }
 
-    if (cvmx_app_hotplug_info_ptr->hotplug_activated_coremask != sys_info_ptr->core_mask)
+    if (ai->hotplug_activated_coremask != sys_info_ptr->core_mask)
     {
-        printf("ERROR: Shutdown requested when not all app cores have activated hotplug\n"
-	       "Application coremask: 0x%x Hotplug coremask: 0x%x\n", (unsigned int)sys_info_ptr->core_mask, 
-	       (unsigned int)cvmx_app_hotplug_info_ptr->hotplug_activated_coremask);
-	return;
+        printf("ERROR: Shutdown requested when not all app cores have "
+               "activated hotplug\n" "Application coremask: 0x%x Hotplug "
+               "coremask: 0x%x\n", (unsigned int)sys_info_ptr->core_mask,
+               (unsigned int)ai->hotplug_activated_coremask);
+        return;
     }
 
-    /* Call the application's own callback function */
-    ((void(*)(void*))(long)cvmx_app_hotplug_info_ptr->shutdown_callback)(CASTPTR(void *, cvmx_app_hotplug_info_ptr->data));
-
-    __cvmx_app_hotplug_sync();
-
-    if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+    if (mbox & 1ull)
     {
-        bzero(cvmx_app_hotplug_info_ptr, sizeof(*cvmx_app_hotplug_info_ptr));
-#ifdef DEBUG
-        cvmx_dprintf("__cvmx_app_hotplug_shutdown(): setting shutdown done! \n");
-#endif
-        cvmx_app_hotplug_info_ptr->shutdown_done = 1;
+        int core = cvmx_get_core_num();
+        if (dbg)
+            printf("Shutting down application .\n");
+        /* Call the application's own callback function */
+        if (ai->shutdown_callback)
+        {
+            ((void(*)(void*))(long)ai->shutdown_callback)(CASTPTR(void *, ai->data));
+        }
+        else
+        {
+            printf("ERROR : Shutdown callback has not been registered\n");
+        }
+        if (!ai->app_shutdown)
+        {
+            if (dbg) 
+                printf("%s : core = %d Invoking app shutdown\n", __FUNCTION__, core);
+            cvmx_app_hotplug_core_shutdown();
+        }
+    }
+    else if (mbox & 2ull)
+    {
+        int core = cvmx_get_core_num();
+        int unplug = is_core_being_unplugged();
+        if (dbg) printf("%s : core=%d Unplug event \n", __FUNCTION__, core);
+
+        if (unplug)
+        {
+            /* Call the application's own callback function */
+            if (ai->unplug_callback)
+            {
+                if (dbg) printf("%s : core=%d Calling unplug callback\n",
+                                __FUNCTION__, core);
+                ((void(*)(void*))(long)ai->unplug_callback)(CASTPTR(void *,
+                                                           ai->data));
+            }
+            if (!ai->app_shutdown)
+            {
+                if (dbg) printf("%s : core = %d Invoking app shutdown\n",
+                                __FUNCTION__, core);
+                cvmx_app_hotplug_core_shutdown();
+            }
+        }
+        else
+        {
+            if (ai->cores_removed_callback)
+            {
+                if (dbg) printf("%s : core=%d Calling cores removed callback\n",
+                                __FUNCTION__, core);
+                ((void(*)(uint32_t, void*))(long)ai->cores_removed_callback)
+                    (ai->unplug_cores, CASTPTR(void *, ai->data));
+            }
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+        }
+    }
+    else if (mbox & 4ull)
+    {
+        int core = cvmx_get_core_num();
+        if (dbg) printf("%s : core=%d Add cores event \n", __FUNCTION__, core);
+
+        if (ai->cores_added_callback)
+        {
+            if (dbg) printf("%s : core=%d Calling cores added callback\n",
+                            __FUNCTION__, core);
+            ((void(*)(uint32_t, void*))(long)ai->cores_added_callback)
+                (ai->hplugged_cores, CASTPTR(void *, ai->data));
+        }
+        cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+    }
+    else
+    {
+        printf("ERROR: unexpected mbox=%llx\n", (unsigned long long)mbox);
     }
 
-    flags = cvmx_interrupt_disable_save();
-
-    __cvmx_app_hotplug_sync();
-
-    /* Reset the core */
-    __cvmx_app_hotplug_reset();
 }
 
-/*
- * Reset the core. We just jump back to the reset vector for now. 
- */
 void __cvmx_app_hotplug_reset(void)
 {
-    /* Code from SecondaryCoreLoop from bootloader, sleep until we recieve
-       a NMI. */
-    __asm__ volatile (
-        ".set noreorder      \n"
-	"\tsync               \n"
-	"\tnop               \n"
-        "1:\twait            \n"
-        "\tb 1b              \n"
-	"\tnop               \n"             
-	".set reorder        \n"
-	:: 
-    );
+#define IDLE_CORE_BLOCK_NAME    "idle-core-loop"
+#define HPLUG_MAKE_XKPHYS(x)       ((1ULL << 63) | (x))
+    uint64_t reset_addr;
+    const cvmx_bootmem_named_block_desc_t *block_desc;
+
+    block_desc = cvmx_bootmem_find_named_block(IDLE_CORE_BLOCK_NAME);
+    if (!block_desc) {
+        cvmx_dprintf("Named block(%s) is not created\n", IDLE_CORE_BLOCK_NAME);
+        /* loop here, should not happen */
+        __asm__ volatile (
+                          ".set noreorder      \n"
+                          "\tsync               \n"
+                          "\tnop               \n"
+                          "1:\twait            \n"
+                          "\tb 1b              \n"
+                          "\tnop               \n"
+                          ".set reorder        \n"
+                          ::
+                          );
+    }
+
+    reset_addr = HPLUG_MAKE_XKPHYS(block_desc->base_addr);
+    asm volatile ("       .set push                \n"
+                  "       .set mips64              \n"
+                  "       .set noreorder           \n"
+                  "       move  $2, %[addr]        \n"
+                  "       jr    $2                 \n"
+                  "       nop                      \n"
+                  "       .set pop "
+                  :: [addr] "r"(reset_addr)
+                  : "$2");
+
+    /*Should never reach here*/
+    while (1) ;
+
 }
 
 /* 
@@ -268,34 +488,47 @@ static void __cvmx_app_hotplug_sync(void)
     cvmx_spinlock_unlock(&cvmx_app_hotplug_sync_lock);
 
     while (sync_coremask != sys_info_ptr->core_mask);
+
+    cvmx_spinlock_lock(&cvmx_app_hotplug_sync_lock);
+    sync_coremask = 0;
+    cvmx_spinlock_unlock(&cvmx_app_hotplug_sync_lock);
+
+
 }
 
 #endif /* CVMX_BUILD_FOR_LINUX_USER */
 
 /**
- * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the 
- * application running on the given coremask. 
- *
- * @param coremask     Coremask of application. 
- * @return             Returns hotplug info struct on success, NULL on failure
- *
- */
-cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
+*  Returns 1 if the running core is being hotplugged, else it returns 0.
+*/
+int is_core_being_hot_plugged(void)
+{
+
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+    if (!cvmx_app_hotplug_info_ptr) return 0;
+    if (cvmx_app_hotplug_info_ptr->hplugged_cores &
+        (1ull << cvmx_get_core_num()))
+        return 1;
+    return 0;
+#else
+    return 0;
+#endif
+}
+
+static cvmx_app_hotplug_global_t *cvmx_app_get_hotplug_global_ptr(void)
 {
     const struct cvmx_bootmem_named_block_desc *block_desc;
-    cvmx_app_hotplug_info_t *hip;
     cvmx_app_hotplug_global_t *hgp;
-    int i;
+
+    if(hotplug_global_ptr != 0) return hotplug_global_ptr;
 
     block_desc = cvmx_bootmem_find_named_block(CVMX_APP_HOTPLUG_INFO_REGION_NAME);
-
     if (!block_desc)
     {
         printf("ERROR: Hotplug info region is not setup\n");
         return NULL;
     }
     else
-
 #ifdef CVMX_BUILD_FOR_LINUX_USER
     {
         size_t pg_sz = sysconf(_SC_PAGESIZE), size;
@@ -314,7 +547,8 @@ cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
          */
         size = CVMX_APP_HOTPLUG_INFO_REGION_SIZE + pg_sz-1;
         offset = block_desc->base_addr & ~(pg_sz-1);
-        if ((vaddr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset)) == MAP_FAILED) 
+        if ((vaddr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset)) 
+	    == MAP_FAILED) 
         {
             perror("mmap");
             return NULL;
@@ -323,34 +557,142 @@ cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
         hgp = (cvmx_app_hotplug_global_t *)(vaddr + ( block_desc->base_addr & (pg_sz-1)));
     }
 #else
-    hgp = cvmx_phys_to_ptr(block_desc->base_addr);
+    hgp = CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, block_desc->base_addr));
 #endif
+    hotplug_global_ptr = hgp;
+    return hgp;
 
-    hip = hgp->hotplug_info_array;
+}
+
+/**
+ * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the 
+ * application running on the given coremask. 
+ *
+ * @param coremask     Coremask of application. 
+ * @return             Returns hotplug info struct on success, NULL on failure
+ *
+ */
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
+{
+    cvmx_app_hotplug_info_t *hip;
+    cvmx_app_hotplug_global_t *hgp;
+    int i;
+    int dbg = 0;
 
 #ifdef DEBUG
-    cvmx_dprintf("cvmx_app_hotplug_get_info(): hotplug_info phy addr 0x%llx ptr %p\n", 
-                  block_desc->base_addr, hgp);
+    dbg = 1;
 #endif
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    if (!hgp) return NULL;
+    hip = hgp->hotplug_info_array;
 
     /* Look for the current app's info */
-
     for (i=0; i<CVMX_APP_HOTPLUG_MAX_APPS; i++)
     {
         if (hip[i].coremask == coremask)
-	{
-#ifdef DEBUG
-	    cvmx_dprintf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x valid %d\n", 
-	                 i, hip[i].coremask, hip[i].valid);
-#endif
-
-	    return &hip[i];
-	}
+        {
+	    if (dbg)
+                printf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x, valid %d\n", i, (unsigned int)hip[i].coremask, (unsigned int)hip[i].valid);
+            return &hip[i];
+        }
     }
-
     return NULL;
 }
 
+/**
+ * Return the hotplug application index structure for the application running on the 
+ * given coremask. 
+ *
+ * @param coremask     Coremask of application. 
+ * @return             Returns hotplug application index on success. -1 on failure
+ *                     
+ */
+int cvmx_app_hotplug_get_index(uint32_t coremask)
+{
+    cvmx_app_hotplug_info_t *hip;
+    cvmx_app_hotplug_global_t *hgp;
+    int i;
+    int dbg = 0;
+
+#ifdef DEBUG
+    dbg = 1;
+#endif
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    if (!hgp) return -1;
+    hip = hgp->hotplug_info_array;
+
+    /* Look for the current app's info */
+    for (i=0; i<CVMX_APP_HOTPLUG_MAX_APPS; i++)
+    {
+        if (hip[i].coremask == coremask)
+        {
+	    if (dbg)
+                printf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x valid %d\n", i, (unsigned int)hip[i].coremask, (unsigned int)hip[i].valid);
+	    return i;
+        }
+    }
+    return -1;
+}
+
+void print_hot_plug_info(cvmx_app_hotplug_info_t* hpinfo)
+{
+    printf("name=%s coremask=%08x hotplugged coremask=%08x valid=%d\n", hpinfo->app_name,
+           (unsigned int)hpinfo->coremask, (unsigned int)hpinfo->hotplug_activated_coremask, (unsigned int)hpinfo->valid);
+}
+
+/**
+ * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the 
+ * application with the specified index.
+ *
+ * @param index        index of application. 
+ * @return             Returns hotplug info struct on success, NULL on failure
+ *
+ */
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info_at_index(int index)
+{
+    cvmx_app_hotplug_info_t *hip;
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    if (!hgp) return NULL;
+    hip = hgp->hotplug_info_array;
+
+#ifdef DEBUG
+    printf("cvmx_app_hotplug_get_info(): hotplug_info phy addr 0x%llx ptr %p\n", 
+                  block_desc->base_addr, hgp);
+#endif
+    if (index < CVMX_APP_HOTPLUG_MAX_APPS)
+    {
+        if (hip[index].valid) 
+        {
+            //print_hot_plug_info( &hip[index] );
+            return &hip[index];
+        }
+    }
+    return NULL;
+}
+
+/**
+ * Determines if SE application at the index specified is hotpluggable.
+ *
+ * @param index        index of application.
+ * @return             Returns -1  on error.
+ *                     0 -> The application is not hotpluggable
+ *                     1 -> The application is hotpluggable
+*/
+int is_app_hotpluggable(int index)
+{
+    cvmx_app_hotplug_info_t *ai;
+
+    if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+    {
+        printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+        return -1;
+    }
+    if (ai->hotplug_activated_coremask) return 1;
+    return 0;
+}
+
 /**
  * This routine sends a shutdown request to a running target application. 
  *
@@ -371,7 +713,7 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
         printf("\nERROR: Failed to get hotplug info for coremask: 0x%x\n", (unsigned int)coremask);
         return -1;
     }
-
+    hotplug_info_ptr->shutdown_cores = coremask;
     if (!hotplug_info_ptr->shutdown_callback)
     {
         printf("\nERROR: Target application has not registered for hotplug!\n");
@@ -386,8 +728,8 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
 
     /* Send IPIs to all application cores to request shutdown */
     for (i=0; i<CVMX_MAX_CORES; i++) {
-    	if (coremask & (1<<i))
-		cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 1);
+            if (coremask & (1ull<<i))
+                cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 1);
     }
 
     if (wait)
@@ -400,3 +742,144 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
 
     return 0;
 }
+
+
+
+/**
+ * This routine invokes the invoked the cores_added callbacks.
+ */
+int cvmx_app_hotplug_call_add_cores_callback(int index)
+{
+    cvmx_app_hotplug_info_t *ai;
+    int i;
+    if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+    {
+        printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+        return -1;
+    }
+   /* Send IPIs to all application cores to request add_cores callback*/
+    for (i=0; i<CVMX_MAX_CORES; i++) {
+            if (ai->coremask & (1ull<<i))
+                cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 4);
+    }
+    return 0;
+}
+
+/**
+ * This routine sends a request to a running target application
+ * to unplug a specified set cores
+ * @param index        is the index of the target application
+ * @param coremask     Coremask of the cores to be unplugged from the app.
+ * @param wait         1 - Wait for shutdown completion
+ *                     0 - Do not wait
+ * @return             0 on success, -1 on error
+ *
+ */ 
+int cvmx_app_hotplug_unplug_cores(int index, uint32_t coremask, int wait) 
+{
+    cvmx_app_hotplug_info_t *ai;
+    int i;
+
+    if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+    {
+        printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+        return -1;
+    }
+    ai->unplug_cores = coremask;
+#if 0
+    if (!ai->shutdown_callback)
+    {
+        printf("\nERROR: Target application has not registered for hotplug!\n");
+        return -1;
+    }
+#endif
+    if ( (ai->coremask | coremask ) != ai->coremask)
+    {
+        printf("\nERROR: Not all cores requested are a part of the app "
+               "r=%08x:%08x\n", (unsigned int)coremask, (unsigned int)ai->coremask);
+        return -1;
+    }
+    if (ai->coremask == coremask)
+    {
+        printf("\nERROR: Trying to remove all cores in app. "
+               "r=%08x:%08x\n", (unsigned int)coremask, (unsigned int)ai->coremask);
+        return -1;
+    }
+    /* Send IPIs to all application cores to request unplug/remove_cores
+       callback */
+    for (i=0; i<CVMX_MAX_CORES; i++) {
+            if (ai->coremask & (1ull<<i))
+                cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 2);
+    }
+
+#if 0
+    if (wait)
+    {
+        while (!ai->shutdown_done);    
+
+        /* Clean up the hotplug info region for this application */
+        bzero(ai, sizeof(*ai));
+    }
+#endif
+    return 0;
+}
+
+/**
+ * Returns 1 if any app is currently being currently booted , hotplugged or
+ * shutdown. Only one app can be under a boot, hotplug or shutdown condition.
+ * Before booting an app this methods should be used to check whether boot or
+ * shutdown activity is in progress and proceed with the boot or shutdown only
+ * when there is no other activity.
+ *
+ */
+int is_app_under_boot_or_shutdown(void)
+{
+    int ret=0;
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+    if (hgp->app_under_boot || hgp->app_under_shutdown) ret=1;
+    cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+    return ret;
+
+}
+
+/**
+ * Sets or clear the app_under_boot value. This when set signifies that an app
+ * is being currently booted or hotplugged with a new core.
+ *
+ *
+ * @param val     sets the app_under_boot to the specified value. This should be
+ *                set to 1 while app any is being booted and cleared after the
+ *                application has booted up.
+ *
+ */
+void set_app_unber_boot(int val)
+{
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+    hgp->app_under_boot = val;
+    cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+}
+
+/**
+ * Sets or clear the app_under_shutdown value. This when set signifies that an
+ * app is being currently shutdown or some cores of an app are being shutdown.
+ *
+ * @param val     sets the app_under_shutdown to the specified value. This
+ *                should be set to 1 while any app is being shutdown and cleared
+ *                after the shutdown of the app is complete.
+ *
+ */
+void set_app_under_shutdown(int val)
+{
+    cvmx_app_hotplug_global_t *hgp;
+
+    hgp = cvmx_app_get_hotplug_global_ptr();
+    cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+    hgp->app_under_shutdown = val;
+    cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+}

sys/contrib/octeon-sdk/cvmx-app-hotplug.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,47 +48,99 @@
 #ifndef __CVMX_APP_HOTPLUG_H__
 #define __CVMX_APP_HOTPLUG_H__
 
-#ifdef	__cplusplus
+#ifdef    __cplusplus
 extern "C" {
 #endif
 
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-spinlock.h>
 #else
 #include "cvmx.h"
 #include "cvmx-coremask.h"
 #include "cvmx-interrupt.h"
 #include "cvmx-bootmem.h"
+#include "cvmx-spinlock.h"
 #endif
 
 #define CVMX_APP_HOTPLUG_MAX_APPS 32
 #define CVMX_APP_HOTPLUG_MAX_APPNAME_LEN 256
 
+/**
+* hotplug_start          is the entry  point for hot plugged cores.
+* cores_added_callback   is callback which in invoked when new cores are added
+*                        to the application. This is invoked on all the old core
+*                        that existed before the current set of cores were
+*                        added.
+* cores_removed_callback is callback which in invoked when cores are removed
+*                        an application. This is invoked on  all the cores that
+*                        exist after the set of cores being requesed are
+*                        removed.
+* shutdown_done_callback before the application is shutdown this callback is
+*                        invoked on all the cores that are part of the app.
+* unplug_callback        before the cores are unplugged this callback is invoked
+*                        only on the cores that are being unlpuuged.
+*/
+typedef struct cvmx_app_hotplug_callbacks
+{
+    void (*hotplug_start)(void *ptr);
+    void (*cores_added_callback) (uint32_t  ,void *ptr);
+    void (*cores_removed_callback) (uint32_t,void *ptr);
+    void (*shutdown_callback) (void *ptr);
+    void (*unplug_core_callback) (void *ptr);
+} cvmx_app_hotplug_callbacks_t;
+
+/* The size of this struct should be a fixed size of 1024 bytes.
+   Additional members should be added towards the end of the
+   strcuture by adjusting the size of padding */
 typedef struct cvmx_app_hotplug_info
 {
-   char app_name[CVMX_APP_HOTPLUG_MAX_APPNAME_LEN];
-   uint32_t coremask;
-   uint32_t volatile hotplug_activated_coremask;
-   int32_t  valid;
-   int32_t volatile shutdown_done;
-   uint64_t shutdown_callback;
-   uint64_t data;
+    char app_name[CVMX_APP_HOTPLUG_MAX_APPNAME_LEN];
+    uint32_t coremask;
+    uint32_t volatile hotplug_activated_coremask;
+    int32_t  valid;
+    int32_t volatile shutdown_done;
+    uint64_t shutdown_callback;
+    uint64_t unplug_callback;
+    uint64_t cores_added_callback;
+    uint64_t cores_removed_callback;
+    uint64_t hotplug_start;
+    uint64_t data;
+    uint32_t volatile hplugged_cores;
+    uint32_t shutdown_cores;
+    uint32_t app_shutdown;
+    uint32_t unplug_cores;
+    uint32_t padding[172];
 } cvmx_app_hotplug_info_t;
 
 struct cvmx_app_hotplug_global
 {
    uint32_t avail_coremask;
    cvmx_app_hotplug_info_t hotplug_info_array[CVMX_APP_HOTPLUG_MAX_APPS];
+   uint32_t version;
+   cvmx_spinlock_t hotplug_global_lock;
+   int app_under_boot;
+   int app_under_shutdown;
 };
-
 typedef struct cvmx_app_hotplug_global cvmx_app_hotplug_global_t;
 
+int is_core_being_hot_plugged(void);
+int is_app_being_booted_or_shutdown(void);
+void set_app_unber_boot(int val);
+void set_app_under_shutdown(int val);
 int cvmx_app_hotplug_shutdown_request(uint32_t, int);
+int cvmx_app_hotplug_unplug_cores(int index, uint32_t coremask, int wait);
 cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t);
+int cvmx_app_hotplug_get_index(uint32_t coremask);
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info_at_index(int index);
+int is_app_hotpluggable(int index);
+int cvmx_app_hotplug_call_add_cores_callback(int index);
 #ifndef CVMX_BUILD_FOR_LINUX_USER
 int cvmx_app_hotplug_register(void(*)(void*), void*);
+int cvmx_app_hotplug_register_cb(cvmx_app_hotplug_callbacks_t *, void*, int);
 int cvmx_app_hotplug_activate(void);
+void cvmx_app_hotplug_core_shutdown(void);
 void cvmx_app_hotplug_shutdown_disable(void);
 void cvmx_app_hotplug_shutdown_enable(void);
 #endif
@@ -96,7 +148,7 @@ void cvmx_app_hotplug_shutdown_enable(void);
 #define CVMX_APP_HOTPLUG_INFO_REGION_SIZE  sizeof(cvmx_app_hotplug_global_t)
 #define CVMX_APP_HOTPLUG_INFO_REGION_NAME  "cvmx-app-hotplug-block"
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 }
 #endif
 

sys/contrib/octeon-sdk/cvmx-app-init-linux.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -61,7 +61,7 @@
  * -# Most hardware can only be initialized once. Unless you're very careful,
  *      this also means you Linux application can only run once.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70129 $<hr>
  *
  */
 #define _GNU_SOURCE
@@ -88,6 +88,7 @@
 #include "cvmx-coremask.h"
 #include "cvmx-spinlock.h"
 #include "cvmx-bootmem.h"
+#include "cvmx-helper-cfg.h"
 
 int octeon_model_version_check(uint32_t chip_id);
 
@@ -326,7 +327,6 @@ int main(int argc, const char *argv[])
     int firstcore = 0;
 
     cvmx_linux_enable_xkphys_access(0);
-
     cvmx_sysinfo_linux_userspace_initialize();
 
     if (sizeof(void*) == 4)
@@ -349,6 +349,10 @@ int main(int argc, const char *argv[])
     /* Check to make sure the Chip version matches the configured version */
     octeon_model_version_check(cvmx_get_proc_id());
 
+    /* Initialize configuration to set bpid, pkind, pko_port for all the 
+       available ports connected. */
+    __cvmx_helper_cfg_init();
+
     /* Get the list of logical cpus we should run on */
     if (sched_getaffinity(0, sizeof(cpumask), (cpu_set_t*)&cpumask))
     {
@@ -362,7 +366,7 @@ int main(int argc, const char *argv[])
 
     /* Get the lowest logical cpu */
     firstcore = ffsl(cpumask) - 1;
-    cpumask ^= (1<<(firstcore));
+    cpumask ^= (1ull<<(firstcore));
     while (1)
     {
         if (cpumask == 0)
@@ -373,9 +377,9 @@ int main(int argc, const char *argv[])
         }
         cpu = ffsl(cpumask) - 1;
         /* Turn off the bit for this CPU number. We've counted him */
-        cpumask ^= (1<<cpu);
+        cpumask ^= (1ull<<cpu);
         /* Increment the number of CPUs running this app */
-         cvmx_atomic_add32(&pending_fork, 1);
+        cvmx_atomic_add32(&pending_fork, 1);
         /* Flush all IO streams before the fork. Otherwise any buffered
            data in the C library will be duplicated. This results in
            duplicate output from a single print */
@@ -406,7 +410,9 @@ int main(int argc, const char *argv[])
     system_info->core_mask |= 1<<cvmx_get_core_num();
     cvmx_atomic_add32(&pending_fork, -1);
     if (cvmx_atomic_get32(&pending_fork) == 0)
+    {
         cvmx_dprintf("Active coremask = 0x%x\n", system_info->core_mask);
+    }
     if (firstcpu)
         system_info->init_core = cvmx_get_core_num();
     cvmx_spinlock_unlock(&mask_lock);

sys/contrib/octeon-sdk/cvmx-app-init.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include "executive-config.h"
 #include "cvmx-config.h"
 #include "cvmx.h"
 #include "cvmx-spinlock.h"
@@ -60,8 +61,12 @@
 #include "cvmx-ebt3000.h"
 #include "cvmx-sim-magic.h"
 #include "cvmx-debug.h"
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-
+#include "cvmx-qlm.h"
+#include "cvmx-scratch.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-helper-jtag.h"
+#include <octeon_mem_map.h>
+#include "libfdt.h"
 int cvmx_debug_uart = -1;
 
 /**
@@ -184,6 +189,20 @@ static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx
                (int)cvmx_bootinfo_ptr->major_version, (int)cvmx_bootinfo_ptr->minor_version);
         exit(-1);
     }
+    if ((cvmx_bootinfo_ptr->minor_version >= 3) && (cvmx_bootinfo_ptr->fdt_addr != 0))
+    {
+        sys_info_ptr->fdt_addr = UNMAPPED_PTR(cvmx_bootinfo_ptr->fdt_addr);
+        if (fdt_check_header((const void *)sys_info_ptr->fdt_addr))
+        {
+            printf("ERROR : Corrupt Device Tree.\n");
+            exit(-1);
+        }
+        printf("Using device tree\n");
+    }
+    else
+    {
+        sys_info_ptr->fdt_addr = 0;
+    }
 }
 
 
@@ -211,18 +230,18 @@ static void process_break_interrupt(int irq_number, uint64_t registers[32], void
         {
             register uint64_t tmp;
 
-	    /* Wait for an another Control-C if right now we have no
-	       access to the console.  After this point we hold the
-	       lock and use a different lock to synchronize between
-	       the memfile dumps from different cores.  As a
-	       consequence regular printfs *don't* work after this
-	       point! */
-	    if (__octeon_uart_trylock () == 1)
-		return;
+            /* Wait for an another Control-C if right now we have no
+               access to the console.  After this point we hold the
+               lock and use a different lock to synchronize between
+               the memfile dumps from different cores.  As a
+               consequence regular printfs *don't* work after this
+               point! */
+            if (__octeon_uart_trylock () == 1)
+                return;
 
             /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
-	       set the MCD0 to be not masked by this core so we know
-	       the signal is received by someone */
+               set the MCD0 to be not masked by this core so we know
+               the signal is received by someone */
             asm volatile (
                 "dmfc0 %0, $22\n"
                 "ori   %0, %0, 0x1110\n"
@@ -270,6 +289,7 @@ char octeon_rev_signature[] =
     "Compiled for Octeon processor id: "OMS;
 #endif
 
+#define OCTEON_BL_FLAG_HPLUG_CORES (1 << 6)
 void __cvmx_app_init(uint64_t app_desc_addr)
 {
     /* App descriptor used by bootloader */
@@ -279,8 +299,16 @@ void __cvmx_app_init(uint64_t app_desc_addr)
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
     int breakflag = 0;
 
+    //printf("coremask=%08x flags=%08x \n", app_desc_ptr->core_mask, app_desc_ptr->flags);
     if (cvmx_coremask_first_core(app_desc_ptr->core_mask))
     {
+        /* Intialize the bootmem allocator with the descriptor that was provided by
+        * the bootloader
+        * IMPORTANT:  All printfs must happen after this since PCI console uses named
+        * blocks.
+        */
+        cvmx_bootmem_init(CASTPTR(cvmx_bootinfo_t, app_desc_ptr->cvmx_desc_vaddr)->phy_mem_desc_addr);
+
         /* do once per application setup  */
         if (app_desc_ptr->desc_version < 6)
         {
@@ -297,8 +325,34 @@ void __cvmx_app_init(uint64_t app_desc_addr)
             process_boot_desc_ver_6(app_desc_ptr,sys_info_ptr);
 
         }
+
+        /*
+         * set up the feature map and config.
+         */
+        octeon_feature_init();
+
+        __cvmx_helper_cfg_init();
     }
-    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+    /* The flags varibale get copied over at some places and tracing the origins
+       found that
+       ** In octeon_setup_boot_desc_block
+         . cvmx_bootinfo_array[core].flags is initialized and the various bits are set
+         . cvmx_bootinfo_array[core].flags gets copied to  boot_desc[core].flags
+         . Then boot_desc then get copied over to the end of the application heap and
+            boot_info_block_array[core].boot_descr_addr is set to point to the boot_desc
+            in heap.
+       ** In start_app boot_vect->boot_info_addr->boot_desc_addr is referenced and passed on
+       to octeon_setup_crt0_tlb() and this puts it into r16
+       ** In ctr0.S of the toolchain r16 is picked up and passed on as a parameter to
+       __cvmx_app_init
+
+       Note : boot_vect->boot_info_addr points to  boot_info_block_array[core] and this
+       pointer is setup in octeon_setup_boot_vector()
+    */
+
+    if (!(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+        cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+
 
     breakflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_BREAK;
 
@@ -311,20 +365,12 @@ void __cvmx_app_init(uint64_t app_desc_addr)
         /* Make sure we can properly run on this chip */
         octeon_model_version_check(chip_id);
     }
-
     cvmx_interrupt_initialize();
-
     if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
     {
         int break_uart = 0;
         unsigned int i;
 
-        /* Intialize the bootmem allocator with the descriptor that was provided by
-         * the bootloader
-         * IMPORTANT:  All printfs must happen after this since PCI console uses named
-         * blocks.
-         */
-        cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
         if (breakflag && cvmx_debug_booted())
         {
             printf("ERROR: Using debug and break together in not supported.\n");
@@ -350,8 +396,8 @@ void __cvmx_app_init(uint64_t app_desc_addr)
             cvmx_uart_enable_intr(break_uart, process_break_interrupt);
         }
     }
-
-    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+    if ( !(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+         cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
 
     /* Clear BEV now that we have installed exception handlers. */
     uint64_t tmp;
@@ -375,13 +421,13 @@ void __cvmx_app_init(uint64_t app_desc_addr)
         "dmtc0 %0, $22, 0\n" : "=r" (tmp));
 
     CVMX_SYNC;
-
     /* Now intialize the debug exception handler as BEV is cleared. */
-    if (!breakflag)
+    if ((!breakflag) && (!(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES)))
         cvmx_debug_init();
 
     /* Synchronise all cores at this point */
-    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+     if ( !(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+         cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
 
 }
 
@@ -396,11 +442,11 @@ int cvmx_user_app_init(void)
 
     /* Put message on LED display */
     if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
-      ebt3000_str_write("CVMX    ");
+        ebt3000_str_write("CVMX    ");
 
     /* Check BIST results for COP0 registers, some values only meaningful in pass 2 */
     CVMX_MF_CACHE_ERR(bist_val);
-    mask = (1ULL<<32) | (1ULL<<33) | (1ULL<<34) | (1ULL<<35) | (1ULL<<36);
+    mask = (0x3fULL<<32); // Icache;BHT;AES;HSH/GFM;LRU;register file
     bist_val &= mask;
     if (bist_val)
     {
@@ -429,6 +475,17 @@ int cvmx_user_app_init(void)
     }
     CVMX_MT_CVM_MEM_CTL(tmp);
 
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
+    {
+        /* Clear the lines of scratch memory configured, for
+        ** 63XX pass 2 errata Core-15169. */
+        uint64_t addr;
+        unsigned  num_lines;
+        CVMX_MF_CVM_MEM_CTL(tmp);
+        num_lines = tmp & 0x3f;
+        for (addr = 0; addr < CVMX_CACHE_LINE_SIZE * num_lines; addr += 8)
+            cvmx_scratch_write64(addr, 0);
+    }
 
 #if CVMX_USE_1_TO_1_TLB_MAPPINGS
 
@@ -475,7 +532,7 @@ int cvmx_user_app_init(void)
                 printf("ERROR adding 1-1 TLB mapping for address 0x%llx\n", (unsigned long long)base_addr);
                 /* Exit from here, as expected memory mappings aren't set
                    up if this fails */
-		exit(-1);
+                exit(-1);
             }
         }
     }
@@ -507,6 +564,10 @@ int cvmx_user_app_init(void)
     cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
     cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
 
+    /* Initialize QLM and JTAG settings. Also apply any erratas. */
+    if (cvmx_coremask_first_core(cvmx_sysinfo_get()->core_mask))
+        cvmx_qlm_init();
+
     return(0);
 }
 
@@ -516,7 +577,7 @@ void __cvmx_app_exit(void)
 
     if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
     {
-	CVMX_BREAK;
+        CVMX_BREAK;
     }
     /* Hang forever, until more appropriate stand alone simple executive
        exit() is implemented */

sys/contrib/octeon-sdk/cvmx-app-init.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,7 +46,7 @@
  * @file
  * Header file for simple executive application initialization.  This defines
  * part of the ABI between the bootloader and the application.
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70327 $<hr>
  *
  */
 
@@ -62,7 +62,7 @@ extern "C" {
 ** from the bootloader to the application.  This is versioned so that applications
 ** can properly handle multiple bootloader versions. */
 #define CVMX_BOOTINFO_MAJ_VER 1
-#define CVMX_BOOTINFO_MIN_VER 2
+#define CVMX_BOOTINFO_MIN_VER 3
 
 
 #if (CVMX_BOOTINFO_MAJ_VER == 1)
@@ -76,6 +76,7 @@ extern "C" {
 ** to 0.
 */
 struct cvmx_bootinfo {
+#ifdef __BIG_ENDIAN_BITFIELD
     uint32_t major_version;
     uint32_t minor_version;
 
@@ -120,8 +121,70 @@ struct cvmx_bootinfo {
     uint32_t config_flags;  /**< flags indicating various configuration options.  These flags supercede
                             ** the 'flags' variable and should be used instead if available */
 #endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+    uint64_t fdt_addr;  /**< Address of the OF Flattened Device Tree structure describing the board. */
+#endif
+#else /* __BIG_ENDIAN */
+	/*
+	 * Little-Endian: When the CPU mode is switched to
+	 * little-endian, the view of the structure has some of the
+	 * fields swapped.
+	 */
+	uint32_t minor_version;
+	uint32_t major_version;
 
+	uint64_t stack_top;
+	uint64_t heap_base;
+	uint64_t heap_end;
+	uint64_t desc_vaddr;
 
+	uint32_t stack_size;
+	uint32_t exception_base_addr;
+
+	uint32_t core_mask;
+	uint32_t flags;
+
+	uint32_t phy_mem_desc_addr;
+	uint32_t dram_size;
+
+	uint32_t eclock_hz;
+	uint32_t debugger_flags_base_addr;
+
+	uint32_t reserved0;
+	uint32_t dclock_hz;
+
+	uint8_t reserved3;
+	uint8_t reserved2;
+	uint16_t reserved1;
+	uint8_t board_rev_minor;
+	uint8_t board_rev_major;
+	uint16_t board_type;
+
+	union cvmx_bootinfo_scramble {
+		/* Must byteswap these four words so that...*/
+		uint64_t s[4];
+		/* ... this strucure has the proper data arrangement. */
+		struct {
+			char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+			uint8_t mac_addr_base[6];
+			uint8_t mac_addr_count;
+			uint8_t pad[5];
+		} le;
+	} scramble1;
+
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+	uint64_t compact_flash_common_base_addr;
+	uint64_t compact_flash_attribute_base_addr;
+	uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+	uint32_t config_flags;
+	uint32_t dfa_ref_clock_hz;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+	uint64_t fdt_addr;
+#endif
+#endif
 };
 
 typedef struct cvmx_bootinfo cvmx_bootinfo_t;
@@ -145,7 +208,7 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_EBT3000        =  2,
     CVMX_BOARD_TYPE_KODAMA         =  3,
     CVMX_BOARD_TYPE_NIAGARA        =  4,	/* Obsolete, no longer supported */
-    CVMX_BOARD_TYPE_NAC38          =  5,	/* formerly NAO38 */
+    CVMX_BOARD_TYPE_NAC38          =  5,	/* Obsolete, no longer supported */
     CVMX_BOARD_TYPE_THUNDER        =  6,
     CVMX_BOARD_TYPE_TRANTOR        =  7,	/* Obsolete, no longer supported */
     CVMX_BOARD_TYPE_EBH3000        =  8,
@@ -178,7 +241,18 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_LANAI2_G       = 35,
     CVMX_BOARD_TYPE_EBT5810        = 36,
     CVMX_BOARD_TYPE_NIC10E         = 37,
+    CVMX_BOARD_TYPE_EP6300C        = 38,
+    CVMX_BOARD_TYPE_EBB6800        = 39,
+    CVMX_BOARD_TYPE_NIC4E          = 40,
+    CVMX_BOARD_TYPE_NIC2E          = 41,
+    CVMX_BOARD_TYPE_EBB6600        = 42,
+    CVMX_BOARD_TYPE_REDWING        = 43,
+    CVMX_BOARD_TYPE_NIC68_4        = 44,
+    CVMX_BOARD_TYPE_NIC10E_66      = 45,
+    CVMX_BOARD_TYPE_EBB6100        = 46,
+    CVMX_BOARD_TYPE_EVB7100        = 47,
     CVMX_BOARD_TYPE_MAX,
+    /* NOTE:  256-257 are being used by a customer. */
 
     /* The range from CVMX_BOARD_TYPE_MAX to CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved
     ** for future SDK use. */
@@ -239,7 +313,7 @@ enum cvmx_board_types_enum {
     CVMX_BOARD_TYPE_MODULE_EBB5600_QLM1 = 30008,
     CVMX_BOARD_TYPE_MODULE_EBB5600_QLM2 = 30009,
     CVMX_BOARD_TYPE_MODULE_EBB5600_QLM3 = 30010,
-    CVMX_BOARD_TYPE_MODULE_MAX          = 31000,
+    CVMX_BOARD_TYPE_MODULE_MAX          = 31000
 
     /* The remaining range is reserved for future use. */
 };
@@ -247,7 +321,7 @@ enum cvmx_chip_types_enum {
     CVMX_CHIP_TYPE_NULL = 0,
     CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
     CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
-    CVMX_CHIP_TYPE_MAX,
+    CVMX_CHIP_TYPE_MAX
 };
 
 /* Compatability alias for NAC38 name change, planned to be removed from SDK 1.7 */
@@ -297,6 +371,16 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
+	ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6100)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EVB7100)
         ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
 
         /* Customer boards listed here */

sys/contrib/octeon-sdk/cvmx-asm.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,13 +48,15 @@
  *
  * This is file defines ASM primitives for the executive.
 
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
 #ifndef __CVMX_ASM_H__
 #define __CVMX_ASM_H__
 
+#define CVMX_MAX_CORES  (32)
+
 #define COP0_INDEX	$0,0	/* TLB read/write index */
 #define COP0_RANDOM	$1,0	/* TLB random index */
 #define COP0_ENTRYLO0	$2,0	/* TLB entryLo0 */
@@ -111,8 +113,6 @@
    things under !__ASSEMBLER__.  */
 #ifndef __ASSEMBLER__
 
-#include "octeon-model.h"
-
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -121,10 +121,9 @@ extern "C" {
 #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
 #define CVMX_TMP_STR2(x) #x
 
-#if !OCTEON_IS_COMMON_BINARY()
- #if CVMX_COMPILED_FOR(OCTEON_CN63XX)
-   #define CVMX_CAVIUM_OCTEON2
- #endif
+/* Since sync is required for Octeon2. */
+#ifdef _MIPS_ARCH_OCTEON2
+#define CVMX_CAVIUM_OCTEON2   1
 #endif
 
 /* other useful stuff */
@@ -139,9 +138,7 @@ extern "C" {
 #endif /* CVMX_CAVIUM_OCTEON2 */
 
 #ifdef __OCTEON__
-    #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory")
-    #define CVMX_SYNCIOALL asm volatile ("nop")   /* Deprecated, will be removed in future release */
     /* We actually use two syncw instructions in a row when we need a write
         memory barrier. This is because the CN3XXX series of Octeons have
         errata Core-401. This can cause a single syncw to not enforce
@@ -187,9 +184,7 @@ extern "C" {
 #endif
 #else /* !__OCTEON__ */
     /* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */
-    #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory")
-    #define CVMX_SYNCIOALL asm volatile ("nop")   /* Deprecated, will be removed in future release */
     #define CVMX_SYNCW asm volatile ("sync" : : :"memory")
     #define CVMX_SYNCWS CVMX_SYNCW
     #define CVMX_SYNCS  CVMX_SYNC

sys/contrib/octeon-sdk/cvmx-asx0-defs.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_ASX0_TYPEDEFS_H__
-#define __CVMX_ASX0_TYPEDEFS_H__
+#ifndef __CVMX_ASX0_DEFS_H__
+#define __CVMX_ASX0_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
@@ -81,12 +81,10 @@ static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
  * ASX_DBG_DATA_DRV
  *
  */
-union cvmx_asx0_dbg_data_drv
-{
+union cvmx_asx0_dbg_data_drv {
 	uint64_t u64;
-	struct cvmx_asx0_dbg_data_drv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asx0_dbg_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t pctl                         : 5;  /**< These bits control the driving strength of the dbg
                                                          interface. */
@@ -98,9 +96,8 @@ union cvmx_asx0_dbg_data_drv
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
-	struct cvmx_asx0_dbg_data_drv_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asx0_dbg_data_drv_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< These bits control the driving strength of the dbg
                                                          interface. */
@@ -124,12 +121,10 @@ typedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t;
  * ASX_DBG_DATA_ENABLE
  *
  */
-union cvmx_asx0_dbg_data_enable
-{
+union cvmx_asx0_dbg_data_enable {
 	uint64_t u64;
-	struct cvmx_asx0_dbg_data_enable_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asx0_dbg_data_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t en                           : 1;  /**< A 1->0 transistion, turns the dbg interface OFF. */
 #else

sys/contrib/octeon-sdk/cvmx-asxx-defs.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_ASXX_TYPEDEFS_H__
-#define __CVMX_ASXX_TYPEDEFS_H__
+#ifndef __CVMX_ASXX_DEFS_H__
+#define __CVMX_ASXX_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
@@ -395,12 +395,10 @@ static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
  * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
  *
  */
-union cvmx_asxx_gmii_rx_clk_set
-{
+union cvmx_asxx_gmii_rx_clk_set {
 	uint64_t u64;
-	struct cvmx_asxx_gmii_rx_clk_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_gmii_rx_clk_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the RXCLK (GMII receive clk)
                                                          delay line.  The intrinsic delay can range from
@@ -422,12 +420,10 @@ typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
  * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
  *
  */
-union cvmx_asxx_gmii_rx_dat_set
-{
+union cvmx_asxx_gmii_rx_dat_set {
 	uint64_t u64;
-	struct cvmx_asxx_gmii_rx_dat_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_gmii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the RXD (GMII receive data)
                                                          delay lines.  The intrinsic delay can range from
@@ -449,12 +445,10 @@ typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
  * ASX_INT_EN = Interrupt Enable
  *
  */
-union cvmx_asxx_int_en
-{
+union cvmx_asxx_int_en {
 	uint64_t u64;
-	struct cvmx_asxx_int_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t txpsh                        : 4;  /**< TX FIFO overflow on RMGII port */
 	uint64_t txpop                        : 4;  /**< TX FIFO underflow on RMGII port */
@@ -466,9 +460,8 @@ union cvmx_asxx_int_en
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_asxx_int_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t txpsh                        : 3;  /**< TX FIFO overflow on RMGII port */
 	uint64_t reserved_7_7                 : 1;
@@ -499,12 +492,10 @@ typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
  * ASX_INT_REG = Interrupt Register
  *
  */
-union cvmx_asxx_int_reg
-{
+union cvmx_asxx_int_reg {
 	uint64_t u64;
-	struct cvmx_asxx_int_reg_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t txpsh                        : 4;  /**< TX FIFO overflow on RMGII port */
 	uint64_t txpop                        : 4;  /**< TX FIFO underflow on RMGII port */
@@ -516,9 +507,8 @@ union cvmx_asxx_int_reg
 	uint64_t reserved_12_63               : 52;
 #endif
 	} s;
-	struct cvmx_asxx_int_reg_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_11_63               : 53;
 	uint64_t txpsh                        : 3;  /**< TX FIFO overflow on RMGII port */
 	uint64_t reserved_7_7                 : 1;
@@ -549,12 +539,10 @@ typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
  * ASX_MII_RX_DAT_SET = GMII Clock delay setting
  *
  */
-union cvmx_asxx_mii_rx_dat_set
-{
+union cvmx_asxx_mii_rx_dat_set {
 	uint64_t u64;
-	struct cvmx_asxx_mii_rx_dat_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_mii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the RXD (MII receive data)
                                                          delay lines.  The intrinsic delay can range from
@@ -575,12 +563,10 @@ typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
  * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
  *
  */
-union cvmx_asxx_prt_loop
-{
+union cvmx_asxx_prt_loop {
 	uint64_t u64;
-	struct cvmx_asxx_prt_loop_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_prt_loop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t ext_loop                     : 4;  /**< External Loopback Enable
                                                          0 = No Loopback (TX FIFO is filled by RMGII)
@@ -602,9 +588,8 @@ union cvmx_asxx_prt_loop
 	uint64_t reserved_8_63                : 56;
 #endif
 	} s;
-	struct cvmx_asxx_prt_loop_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_prt_loop_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_7_63                : 57;
 	uint64_t ext_loop                     : 3;  /**< External Loopback Enable
                                                          0 = No Loopback (TX FIFO is filled by RMGII)
@@ -646,12 +631,10 @@ typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
  * ASX_RLD_BYPASS
  *
  */
-union cvmx_asxx_rld_bypass
-{
+union cvmx_asxx_rld_bypass {
 	uint64_t u64;
-	struct cvmx_asxx_rld_bypass_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_bypass_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t bypass                       : 1;  /**< When set, the rld_dll setting is bypassed with
                                                          ASX_RLD_BYPASS_SETTING */
@@ -673,12 +656,10 @@ typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
  * ASX_RLD_BYPASS_SETTING
  *
  */
-union cvmx_asxx_rld_bypass_setting
-{
+union cvmx_asxx_rld_bypass_setting {
 	uint64_t u64;
-	struct cvmx_asxx_rld_bypass_setting_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_bypass_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< The rld_dll setting bypass value */
 #else
@@ -699,12 +680,10 @@ typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
  * ASX_RLD_COMP
  *
  */
-union cvmx_asxx_rld_comp
-{
+union cvmx_asxx_rld_comp {
 	uint64_t u64;
-	struct cvmx_asxx_rld_comp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t pctl                         : 5;  /**< PCTL Compensation Value
                                                          These bits reflect the computed compensation
@@ -717,9 +696,8 @@ union cvmx_asxx_rld_comp
 	uint64_t reserved_9_63                : 55;
 #endif
 	} s;
-	struct cvmx_asxx_rld_comp_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_comp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< These bits reflect the computed compensation
                                                          values from the built-in compensation circuit. */
@@ -743,12 +721,10 @@ typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
  * ASX_RLD_DATA_DRV
  *
  */
-union cvmx_asxx_rld_data_drv
-{
+union cvmx_asxx_rld_data_drv {
 	uint64_t u64;
-	struct cvmx_asxx_rld_data_drv_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< These bits specify a driving strength (positive
                                                          integer) for the RLD I/Os when the built-in
@@ -775,12 +751,10 @@ typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
  * ASX_RLD_FCRAM_MODE
  *
  */
-union cvmx_asxx_rld_fcram_mode
-{
+union cvmx_asxx_rld_fcram_mode {
 	uint64_t u64;
-	struct cvmx_asxx_rld_fcram_mode_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_fcram_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t mode                         : 1;  /**< Memory Mode
                                                          - 0: RLDRAM
@@ -801,12 +775,10 @@ typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
  * ASX_RLD_NCTL_STRONG
  *
  */
-union cvmx_asxx_rld_nctl_strong
-{
+union cvmx_asxx_rld_nctl_strong {
 	uint64_t u64;
-	struct cvmx_asxx_rld_nctl_strong_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_nctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t nctl                         : 5;  /**< Duke's drive control */
 #else
@@ -827,12 +799,10 @@ typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
  * ASX_RLD_NCTL_WEAK
  *
  */
-union cvmx_asxx_rld_nctl_weak
-{
+union cvmx_asxx_rld_nctl_weak {
 	uint64_t u64;
-	struct cvmx_asxx_rld_nctl_weak_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_nctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t nctl                         : 5;  /**< UNUSED (not needed for CN58XX) */
 #else
@@ -853,12 +823,10 @@ typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
  * ASX_RLD_PCTL_STRONG
  *
  */
-union cvmx_asxx_rld_pctl_strong
-{
+union cvmx_asxx_rld_pctl_strong {
 	uint64_t u64;
-	struct cvmx_asxx_rld_pctl_strong_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_pctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t pctl                         : 5;  /**< Duke's drive control */
 #else
@@ -879,12 +847,10 @@ typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
  * ASX_RLD_PCTL_WEAK
  *
  */
-union cvmx_asxx_rld_pctl_weak
-{
+union cvmx_asxx_rld_pctl_weak {
 	uint64_t u64;
-	struct cvmx_asxx_rld_pctl_weak_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_pctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t pctl                         : 5;  /**< UNUSED (not needed for CN58XX) */
 #else
@@ -905,12 +871,10 @@ typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
  * ASX_RLD_SETTING
  *
  */
-union cvmx_asxx_rld_setting
-{
+union cvmx_asxx_rld_setting {
 	uint64_t u64;
-	struct cvmx_asxx_rld_setting_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t dfaset                       : 5;  /**< RLD ClkGen DLL Setting(debug) */
 	uint64_t dfalag                       : 1;  /**< RLD ClkGen DLL Lag Error(debug) */
@@ -926,9 +890,8 @@ union cvmx_asxx_rld_setting
 	uint64_t reserved_13_63               : 51;
 #endif
 	} s;
-	struct cvmx_asxx_rld_setting_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rld_setting_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< This is the read-only true rld dll_setting. */
 #else
@@ -982,12 +945,10 @@ typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
  *    1.25            24
  *    1.3             25
  */
-union cvmx_asxx_rx_clk_setx
-{
+union cvmx_asxx_rx_clk_setx {
 	uint64_t u64;
-	struct cvmx_asxx_rx_clk_setx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the open-loop RXC delay line */
 #else
@@ -1011,12 +972,10 @@ typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
  * ASX_RX_PRT_EN = RGMII Port Enable
  *
  */
-union cvmx_asxx_rx_prt_en
-{
+union cvmx_asxx_rx_prt_en {
 	uint64_t u64;
-	struct cvmx_asxx_rx_prt_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t prt_en                       : 4;  /**< Port enable.  Must be set for Octane to receive
                                                          RMGII traffic.  When this bit clear on a given
@@ -1027,9 +986,8 @@ union cvmx_asxx_rx_prt_en
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_asxx_rx_prt_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t prt_en                       : 3;  /**< Port enable.  Must be set for Octane to receive
                                                          RMGII traffic.  When this bit clear on a given
@@ -1055,12 +1013,10 @@ typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
  * ASX_RX_WOL = RGMII RX Wake on LAN status register
  *
  */
-union cvmx_asxx_rx_wol
-{
+union cvmx_asxx_rx_wol {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_2_63                : 62;
 	uint64_t status                       : 1;  /**< Copy of PMCSR[15] - PME_status */
 	uint64_t enable                       : 1;  /**< Copy of PMCSR[8]  - PME_enable */
@@ -1081,12 +1037,10 @@ typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
  * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
  *
  */
-union cvmx_asxx_rx_wol_msk
-{
+union cvmx_asxx_rx_wol_msk {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_msk_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t msk                          : 64; /**< Bytes to include in the CRC signature */
 #else
 	uint64_t msk                          : 64;
@@ -1103,12 +1057,10 @@ typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
  * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
  *
  */
-union cvmx_asxx_rx_wol_powok
-{
+union cvmx_asxx_rx_wol_powok {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_powok_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_powok_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_1_63                : 63;
 	uint64_t powerok                      : 1;  /**< Power OK */
 #else
@@ -1127,12 +1079,10 @@ typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
  * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
  *
  */
-union cvmx_asxx_rx_wol_sig
-{
+union cvmx_asxx_rx_wol_sig {
 	uint64_t u64;
-	struct cvmx_asxx_rx_wol_sig_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_rx_wol_sig_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t sig                          : 32; /**< CRC signature */
 #else
@@ -1185,12 +1135,10 @@ typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
  *    1.25            24
  *    1.3             25
  */
-union cvmx_asxx_tx_clk_setx
-{
+union cvmx_asxx_tx_clk_setx {
 	uint64_t u64;
-	struct cvmx_asxx_tx_clk_setx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_5_63                : 59;
 	uint64_t setting                      : 5;  /**< Setting to place on the open-loop TXC delay line */
 #else
@@ -1214,20 +1162,17 @@ typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
  * ASX_TX_COMP_BYP = RGMII Clock delay setting
  *
  */
-union cvmx_asxx_tx_comp_byp
-{
+union cvmx_asxx_tx_comp_byp {
 	uint64_t u64;
-	struct cvmx_asxx_tx_comp_byp_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_0_63                : 64;
 #else
 	uint64_t reserved_0_63                : 64;
 #endif
 	} s;
-	struct cvmx_asxx_tx_comp_byp_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_9_63                : 55;
 	uint64_t bypass                       : 1;  /**< Compensation bypass */
 	uint64_t pctl                         : 4;  /**< PCTL Compensation Value (see Duke) */
@@ -1240,9 +1185,8 @@ union cvmx_asxx_tx_comp_byp
 #endif
 	} cn30xx;
 	struct cvmx_asxx_tx_comp_byp_cn30xx   cn31xx;
-	struct cvmx_asxx_tx_comp_byp_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_8_63                : 56;
 	uint64_t pctl                         : 4;  /**< PCTL Compensation Value (see Duke) */
 	uint64_t nctl                         : 4;  /**< NCTL Compensation Value (see Duke) */
@@ -1253,9 +1197,8 @@ union cvmx_asxx_tx_comp_byp
 #endif
 	} cn38xx;
 	struct cvmx_asxx_tx_comp_byp_cn38xx   cn38xxp2;
-	struct cvmx_asxx_tx_comp_byp_cn50xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t bypass                       : 1;  /**< Compensation bypass */
 	uint64_t reserved_13_15               : 3;
@@ -1271,9 +1214,8 @@ union cvmx_asxx_tx_comp_byp
 	uint64_t reserved_17_63               : 47;
 #endif
 	} cn50xx;
-	struct cvmx_asxx_tx_comp_byp_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_comp_byp_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_13_63               : 51;
 	uint64_t pctl                         : 5;  /**< PCTL Compensation Value (see Duke) */
 	uint64_t reserved_5_7                 : 3;
@@ -1295,12 +1237,10 @@ typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
  * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
  *
  */
-union cvmx_asxx_tx_hi_waterx
-{
+union cvmx_asxx_tx_hi_waterx {
 	uint64_t u64;
-	struct cvmx_asxx_tx_hi_waterx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_hi_waterx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t mark                         : 4;  /**< TX FIFO HiWatermark to stall GMX
                                                          Value of 0 maps to 16
@@ -1315,9 +1255,8 @@ union cvmx_asxx_tx_hi_waterx
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_asxx_tx_hi_waterx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_hi_waterx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t mark                         : 3;  /**< TX FIFO HiWatermark to stall GMX
                                                          Value 0 maps to 8. */
@@ -1341,12 +1280,10 @@ typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
  * ASX_TX_PRT_EN = RGMII Port Enable
  *
  */
-union cvmx_asxx_tx_prt_en
-{
+union cvmx_asxx_tx_prt_en {
 	uint64_t u64;
-	struct cvmx_asxx_tx_prt_en_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_4_63                : 60;
 	uint64_t prt_en                       : 4;  /**< Port enable.  Must be set for Octane to send
                                                          RMGII traffic.   When this bit clear on a given
@@ -1357,9 +1294,8 @@ union cvmx_asxx_tx_prt_en
 	uint64_t reserved_4_63                : 60;
 #endif
 	} s;
-	struct cvmx_asxx_tx_prt_en_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_asxx_tx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t prt_en                       : 3;  /**< Port enable.  Must be set for Octane to send
                                                          RMGII traffic.   When this bit clear on a given

sys/contrib/octeon-sdk/cvmx-atomic.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides atomic operations
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */
@@ -356,7 +356,7 @@ static inline int64_t cvmx_atomic_fetch_and_add64_nosync(int64_t *ptr, int64_t i
     uint64_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(incr) && incr == 1)
@@ -441,7 +441,7 @@ static inline int32_t cvmx_atomic_fetch_and_add32_nosync(int32_t *ptr, int32_t i
     uint32_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(incr) && incr == 1)
@@ -657,7 +657,7 @@ static inline uint64_t cvmx_atomic_swap64_nosync(uint64_t *ptr, uint64_t new_val
     uint64_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(new_val) && new_val == 0)
@@ -719,7 +719,7 @@ static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val
     uint32_t tmp, ret;
 
 #if !defined(__FreeBSD__) || !defined(_KERNEL)
-    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
 	CVMX_PUSH_OCTEON2;
 	if (__builtin_constant_p(new_val) && new_val == 0)
@@ -763,22 +763,6 @@ static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val
     return (ret);
 }
 
-/**
- * This atomic operation is now named cvmx_atomic_compare_and_store32_nosync
- * and the (deprecated) macro is provided for backward compatibility.
- * @deprecated
- */
-#define cvmx_atomic_compare_and_store_nosync32 cvmx_atomic_compare_and_store32_nosync
-
-/**
- * This atomic operation is now named cvmx_atomic_compare_and_store64_nosync
- * and the (deprecated) macro is provided for backward compatibility.
- * @deprecated
- */
-#define cvmx_atomic_compare_and_store_nosync64 cvmx_atomic_compare_and_store64_nosync
-
-
-
 #ifdef	__cplusplus
 }
 #endif

sys/contrib/octeon-sdk/cvmx-bootloader.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  *
  * Bootloader definitions that are shared with other programs
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 
@@ -127,9 +127,9 @@ typedef enum
     BL_HEADER_IMAGE_PCIBOOT,     /* Binary bootloader for PCI boot */
     BL_HEADER_IMAGE_UBOOT_ENV,  /* Environment for u-boot */
     BL_HEADER_IMAGE_MAX,
-    /* Range for customer private use.  Will not be used by Cavium Networks */
+    /* Range for customer private use.  Will not be used by Cavium Inc. */
     BL_HEADER_IMAGE_CUST_RESERVED_MIN = 0x1000,
-    BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff,
+    BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff
 } bootloader_image_t;
 
 #endif /* __ASSEMBLY__ */
@@ -139,7 +139,7 @@ typedef enum
 #define MAX_NAND_SEARCH_ADDR   0x400000
 
 /* Maximum address to look for start of normal bootloader */
-#define MAX_NOR_SEARCH_ADDR   0x100000
+#define MAX_NOR_SEARCH_ADDR   0x200000
 
 /* Defines for RAM based environment set by the host or the previous bootloader
 ** in a chain boot configuration. */
@@ -147,5 +147,6 @@ typedef enum
 #define U_BOOT_RAM_ENV_ADDR     (0x1000)
 #define U_BOOT_RAM_ENV_SIZE     (0x1000)
 #define U_BOOT_RAM_ENV_CRC_SIZE (0x4)
+#define U_BOOT_RAM_ENV_ADDR_2	(U_BOOT_RAM_ENV_ADDR + U_BOOT_RAM_ENV_SIZE)
 
 #endif /* __CVMX_BOOTLOADER__ */

sys/contrib/octeon-sdk/cvmx-bootmem.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
  * Simple allocate only memory allocator.  Used to allocate memory at application
  * start time.
  *
- * <hr>$Revision: 52119 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -302,7 +302,7 @@ static int __cvmx_bootmem_check_version(int exact_match)
     int major_version;
 #ifdef CVMX_BUILD_FOR_LINUX_HOST
     if (!cvmx_bootmem_desc_addr)
-        cvmx_bootmem_desc_addr = cvmx_read64_uint64(0x24100);
+        cvmx_bootmem_desc_addr = cvmx_read64_uint64(0x48100);
 #endif
     major_version = CVMX_BOOTMEM_DESC_GET_FIELD(major_version);
     if ((major_version > 3) || (exact_match && major_version != exact_match))
@@ -459,27 +459,70 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
 EXPORT_SYMBOL(cvmx_bootmem_alloc);
 #endif
 
-void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name)
+void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, void (*init)(void*))
 {
     int64_t addr;
+    void *ptr;
+    uint64_t named_block_desc_addr;
+
+    __cvmx_bootmem_lock(0);
 
     __cvmx_validate_mem_range(&min_addr, &max_addr);
-    addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, 0);
-    if (addr >= 0)
+    named_block_desc_addr = cvmx_bootmem_phy_named_block_find(name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+    if (named_block_desc_addr)
+    {
+        addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_desc_addr, base_addr);
+        __cvmx_bootmem_unlock(0);
         return cvmx_phys_to_ptr(addr);
-    else
+    }
+
+    addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+    if (addr < 0)
+    {
+        __cvmx_bootmem_unlock(0);
         return NULL;
+    }
+    ptr = cvmx_phys_to_ptr(addr);
+    init(ptr);
+    __cvmx_bootmem_unlock(0);
+    return ptr;
+}
+
+static void *cvmx_bootmem_alloc_named_range_flags(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, uint32_t flags)
+{
+	int64_t addr;
+
+	__cvmx_validate_mem_range(&min_addr, &max_addr);
+	addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, flags);
+	if (addr >= 0)
+		return cvmx_phys_to_ptr(addr);
+	else
+		return NULL;
 
 }
+
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name)
+{
+    return cvmx_bootmem_alloc_named_range_flags(size, min_addr, max_addr, align, name, 0);
+}
+
 void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, const char *name)
 {
     return(cvmx_bootmem_alloc_named_range(size, address, address + size, 0, name));
 }
+
 void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name)
 {
     return(cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name));
 }
 
+void *cvmx_bootmem_alloc_named_flags(uint64_t size, uint64_t alignment, const char *name, uint32_t flags)
+{
+    return cvmx_bootmem_alloc_named_range_flags(size, 0, 0, alignment, name, flags);
+}
+
 int cvmx_bootmem_free_named(const char *name)
 {
     return(cvmx_bootmem_phy_named_block_free(name, 0));
@@ -571,16 +614,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
     /* Round req_size up to mult of minimum alignment bytes */
     req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) & ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
 
-    /* Convert !0 address_min and 0 address_max to special case of range that specifies an exact
-    ** memory block to allocate.  Do this before other checks and adjustments so that this tranformation will be validated */
-    if (address_min && !address_max)
-        address_max = address_min + req_size;
-    else if (!address_min && !address_max)
-        address_max = ~0ull;   /* If no limits given, use max limits */
-
-
-
-
+    
     /* Enforce minimum alignment (this also keeps the minimum free block
     ** req_size the same as the alignment req_size */
     if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE)
@@ -594,6 +628,12 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
     if (alignment)
         address_min = (address_min + (alignment - 1)) & ~(alignment - 1);
 
+    /* Convert !0 address_min and 0 address_max to special case of range that specifies an exact
+     ** memory block to allocate.  Do this before other checks and adjustments so that this tranformation will be validated */
+    if (address_min && !address_max)
+        address_max = address_min + req_size;
+    else if (!address_min && !address_max)
+        address_max = ~0ull;   /* If no limits given, use max limits */
 
     /* Reject inconsistent args.  We have adjusted these, so this may fail due to our internal changes
     ** even if this check would pass for the values the user supplied. */
@@ -827,7 +867,7 @@ void cvmx_bootmem_phy_list_print(void)
     }
     while (addr)
     {
-        cvmx_dprintf("Block address: 0x%08qx, size: 0x%08qx, next: 0x%08qx\n",
+        cvmx_dprintf("Block address: 0x%08llx, size: 0x%08llx, next: 0x%08llx\n",
                (ULL)addr,
                (ULL)cvmx_bootmem_phy_get_size(addr),
                (ULL)cvmx_bootmem_phy_get_next(addr));
@@ -1016,7 +1056,7 @@ void cvmx_bootmem_phy_named_block_print(void)
             uint64_t named_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_addr, base_addr);
             CVMX_BOOTMEM_NAMED_GET_NAME(named_block_addr, name_tmp, name_length);
             printed++;
-            cvmx_dprintf("Name: %s, address: 0x%08qx, size: 0x%08qx, index: %d\n",
+            cvmx_dprintf("Name: %s, address: 0x%08llx, size: 0x%08llx, index: %d\n",
                    name_tmp, (ULL)named_addr, (ULL)named_size, i);
         }
         named_block_addr += sizeof(cvmx_bootmem_named_block_desc_t);
@@ -1029,14 +1069,6 @@ void cvmx_bootmem_phy_named_block_print(void)
 }
 
 
-/* Real physical addresses of memory regions */
-#define OCTEON_DDR0_BASE    (0x0ULL)
-#define OCTEON_DDR0_SIZE    (0x010000000ULL)
-#define OCTEON_DDR1_BASE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x20000000ULL : 0x410000000ULL)
-#define OCTEON_DDR1_SIZE    (0x010000000ULL)
-#define OCTEON_DDR2_BASE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x30000000ULL : 0x20000000ULL)
-#define OCTEON_DDR2_SIZE    (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x7d0000000ULL : 0x3e0000000ULL)
-#define OCTEON_MAX_PHY_MEM_SIZE (OCTEON_IS_MODEL(OCTEON_CN63XX) ? 32*1024*1024*1024ULL : 16*1024*1024*1024ULL)
 int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_bytes, cvmx_bootmem_desc_t *desc_buffer)
 {
     uint64_t cur_block_addr;

sys/contrib/octeon-sdk/cvmx-bootmem.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
  * Simple allocate only memory allocator.  Used to allocate memory at application
  * start time.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -66,6 +66,14 @@ extern "C" {
 #define CVMX_BOOTMEM_FLAG_END_ALLOC    (1 << 0)     /* Allocate from end of block instead of beginning */
 #define CVMX_BOOTMEM_FLAG_NO_LOCKING   (1 << 1)     /* Don't do any locking. */
 
+/* Real physical addresses of memory regions */
+#define OCTEON_DDR0_BASE    (0x0ULL)
+#define OCTEON_DDR0_SIZE    (0x010000000ULL)
+#define OCTEON_DDR1_BASE    ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x20000000ULL : 0x410000000ULL)
+#define OCTEON_DDR1_SIZE    (0x010000000ULL)
+#define OCTEON_DDR2_BASE    ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x30000000ULL : 0x20000000ULL)
+#define OCTEON_DDR2_SIZE    ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x7d0000000ULL : 0x3e0000000ULL)
+#define OCTEON_MAX_PHY_MEM_SIZE ((OCTEON_IS_MODEL(OCTEON_CN68XX)) ? 128*1024*1024*1024ULL : (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 32*1024*1024*1024ull : 16*1024*1024*1024ULL)
 
 /* First bytes of each free physical block of memory contain this structure,
  * which is used to maintain the free memory list.  Since the bootloader is
@@ -162,6 +170,21 @@ extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
  */
 extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, uint64_t alignment);
 
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader within a specified
+ * address range. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated in the requested range.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param min_addr  defines the minimum address of the range
+ * @param max_addr  defines the maximum address of the range
+ * @param alignment Alignment required - must be power of 2
+ * @param flags     Flags to control options for the allocation.
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_range_flags(uint64_t size, uint64_t alignment, uint64_t min_addr, uint64_t max_addr, uint32_t flags);
 
 
 /**
@@ -194,6 +217,21 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, uint64_
  */
 extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name);
 
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ * @param name      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param flags     Flags to control options for the allocation.
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_flags(uint64_t size, uint64_t alignment, const char *name, uint32_t flags);
+
 
 
 /**
@@ -230,6 +268,25 @@ extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, c
  */
 extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name);
 
+/**
+ * Allocate if needed a block of memory from a specific range of the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ * If the requested name block is already allocated, return the pointer to block of memory.
+ * If request cannot be satisfied within the address range specified, NULL is returned
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param min_addr  minimum address of range
+ * @param max_addr  maximum address of range
+ * @param align     Alignment of memory to be allocated. (must be a power of 2)
+ * @param name      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param init      Initialization function
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, void (*init)(void*));
+
 /**
  * Frees a previously allocated named bootmem block.
  *

sys/contrib/octeon-sdk/cvmx-clock.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -89,6 +89,9 @@ uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
 
     if (cvmx_unlikely(!rate_eclk))
     {
+	/* Note: The order of these checks is important.
+	** octeon_has_feature(OCTEON_FEATURE_PCIE) is true for both 6XXX
+	** and 52XX/56XX, so OCTEON_FEATURE_NPEI _must_ be checked first */
         if (octeon_has_feature(OCTEON_FEATURE_NPEI))
         {
             cvmx_npei_dbg_data_t npei_dbg_data;
@@ -124,7 +127,7 @@ uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
             return rate_eclk;
 
         case CVMX_CLOCK_DDR:
-#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(__OCTEON_NEWLIB__)
+#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(CVMX_BUILD_FOR_TOOLCHAIN)
             if (cvmx_unlikely(!rate_dclk))
                 rate_dclk = cvmx_sysinfo_get()->dram_data_rate_hz;
 #endif

sys/contrib/octeon-sdk/cvmx-clock.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -120,7 +120,7 @@ static inline uint64_t cvmx_clock_get_count(cvmx_clock_t clock)
             return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
 
         case CVMX_CLOCK_DDR:
-            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+            if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
                 return cvmx_read_csr(CVMX_LMCX_DCLK_CNT(0));
             else
                 return ((cvmx_read_csr(CVMX_LMCX_DCLK_CNT_HI(0)) << 32) | cvmx_read_csr(CVMX_LMCX_DCLK_CNT_LO(0)));

sys/contrib/octeon-sdk/cvmx-cmd-queue.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Support functions for managing command queues used for
  * various hardware blocks.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
@@ -288,7 +288,10 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
             {
                 cvmx_pko_mem_debug8_t debug8;
                 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
-                return debug8.cn58xx.doorbell;
+                if (octeon_has_feature(OCTEON_FEATURE_PKND))
+                    return debug8.cn68xx.doorbell;
+                else
+                    return debug8.cn58xx.doorbell;
             }
         case CVMX_CMD_QUEUE_ZIP:
         case CVMX_CMD_QUEUE_DFA:

sys/contrib/octeon-sdk/cvmx-cmd-queue.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -88,7 +88,7 @@
  * internal cycle counter to completely eliminate any causes of
  * bus traffic.
  *
- * <hr> $Revision: 50049 $ <hr>
+ * <hr> $Revision: 70030 $ <hr>
  */
 
 #ifndef __CVMX_CMD_QUEUE_H__
@@ -125,6 +125,7 @@ typedef enum
     CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
 #define CVMX_CMD_QUEUE_PKO(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
     CVMX_CMD_QUEUE_ZIP      = 0x10000,
+#define CVMX_CMD_QUEUE_ZIP_QUE(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_ZIP + (0xffff&(queue))))
     CVMX_CMD_QUEUE_DFA      = 0x20000,
     CVMX_CMD_QUEUE_RAID     = 0x30000,
     CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
@@ -233,7 +234,7 @@ void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
 static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
 {
     /* Warning: This code currently only works with devices that have 256 queues
-        or less. Devices with more than 16 queues are layed out in memory to allow
+        or less. Devices with more than 16 queues are laid out in memory to allow
         cores quick access to every 16th queue. This reduces cache thrashing
         when you are running 16 queues per port to support lockless operation */
     int unit = queue_id>>16;

sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the EBH-30xx specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  *
  * Interface to the EBH-30xx specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-compactflash.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-compactflash.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-core.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Module to support operations on core such as TLB config, etc.
  *
- * <hr>$Revision: 49862 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-core.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Module to support operations on core such as TLB config, etc.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -134,12 +134,12 @@ typedef union
     uint32_t u32;
     struct
     {
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
         uint32_t m              : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
-        uint32_t w              : 1; /**< Set to 1 indicating coutners are 64 bit */
+        uint32_t w              : 1; /**< Set to 1 indicating counters are 64 bit */
         uint32_t reserved_11_29 :15;
         cvmx_core_perf_t event  :10; /**< Selects the event to be counted by the corresponding Counter Register */
-        uint32_t ie             : 1; /**< Count in interrupt context */
+        uint32_t ie             : 1; /**< Interrupt Enable */
         uint32_t u              : 1; /**< Count in user mode */
         uint32_t s              : 1; /**< Count in supervisor mode */
         uint32_t k              : 1; /**< Count in kernel mode */

sys/contrib/octeon-sdk/cvmx-coremask.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * initialization and differentiation of roles within a single shared binary
  * executable image.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-coremask.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * initialization and differentiation of roles within a single shared binary
  * executable image.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -65,6 +65,162 @@
 extern "C" {
 #endif
 
+typedef uint64_t cvmx_coremask_holder_t;	/* basic type to hold the
+						   coremask bits */
+
+#define CVMX_COREMASK_HLDRSZ ((int)(sizeof(cvmx_coremask_holder_t) * 8))
+						/* bits per holder */
+
+#define CVMX_COREMASK_BMPSZ ((int)(CVMX_MAX_CORES / CVMX_COREMASK_HLDRSZ + 1))
+						/* bit map size */
+
+/*
+ * The macro pair implement a way to iterate active cores in the mask.
+ * @param fec_pcm points to the coremask.
+ * @param fec_ppid is the active core's id.
+ */
+#define CVMX_COREMASK_FOR_EACH_CORE_BEGIN(fec_pcm, fec_ppid)		\
+    do {								\
+    	int fec_i, fec_j;						\
+    				 					\
+	for (fec_i = 0; fec_i < CVMX_COREMASK_BMPSZ; fec_i++)		\
+	{								\
+	    for (fec_j = 0; fec_j < CVMX_COREMASK_HLDRSZ; fec_j++)	\
+	    { 								\
+		if (((cvmx_coremask_holder_t)1 << fec_j) & 		\
+		    (fec_pcm)->coremask_bitmap[fec_i])			\
+		{							\
+	            fec_ppid = fec_i * CVMX_COREMASK_HLDRSZ + fec_j;
+
+
+#define CVMX_COREMASK_FOR_EACH_CORE_END					\
+		}							\
+	    }								\
+	}								\
+   } while (0)
+
+struct cvmx_coremask {
+    /*
+     * Big-endian. Array elems of larger indices represent cores of
+     * bigger ids. So do MSBs within a cvmx_coremask_holder_t. Ditto
+     * MSbs within a byte.
+     */
+    cvmx_coremask_holder_t coremask_bitmap[CVMX_COREMASK_BMPSZ];
+};
+
+/*
+ * Is ``core'' set in the coremask?
+ *
+ * @param pcm is the pointer to the coremask.
+ * @param core
+ * @return 1 if core is set and 0 if not.
+ */
+static inline int cvmx_coremask_is_set_core(struct cvmx_coremask *pcm,
+    int core)
+{
+    int n, i;
+
+    n = core % CVMX_COREMASK_HLDRSZ;
+    i = core / CVMX_COREMASK_HLDRSZ;
+
+    return (int)((pcm->coremask_bitmap[i] & (1ull << n)) != 0);
+}
+
+/*
+ * Set ``core'' in the coremask.
+ *
+ * @param pcm is the pointer to the coremask.
+ * @param core
+ * @return 0.
+ */
+static inline int cvmx_coremask_set_core(struct cvmx_coremask *pcm,
+    int core)
+{
+    int n, i;
+
+    n = core % CVMX_COREMASK_HLDRSZ;
+    i = core / CVMX_COREMASK_HLDRSZ;
+    pcm->coremask_bitmap[i] |= (1ull << n);
+
+    return 0;
+}
+
+/*
+ * Clear ``core'' from the coremask.
+ *
+ * @param pcm is the pointer to the coremask.
+ * @param core
+ * @return 0.
+ */
+static inline int cvmx_coremask_clear_core(struct cvmx_coremask *pcm,
+    int core)
+{
+    int n, i;
+
+    n = core % CVMX_COREMASK_HLDRSZ;
+    i = core / CVMX_COREMASK_HLDRSZ;
+    pcm->coremask_bitmap[i] &= ~(1ull << n);
+
+    return 0;
+}
+
+/*
+ * Clear the coremask.
+ *
+ * @param pcm is the pointer to the coremask.
+ * @return 0.
+ */
+static inline int cvmx_coremask_clear_all(struct cvmx_coremask *pcm)
+{
+    int i;
+
+    for (i = 0; i < CVMX_COREMASK_BMPSZ; i++)
+        pcm->coremask_bitmap[i] = 0;
+
+    return 0;
+}
+
+/*
+ * Is the current core the first in the coremask?
+ *
+ * @param pcm is the pointer to the coremask.
+ * @return 1 for yes and 0 for no.
+ */
+static inline int cvmx_coremask_first_core_bmp(struct cvmx_coremask *pcm)
+{
+     int n, i;
+
+     n = (int) cvmx_get_core_num();
+     for (i = 0; i < CVMX_COREMASK_BMPSZ; i++)
+     {
+         if (pcm->coremask_bitmap[i])
+         {
+             if (n == 0 && pcm->coremask_bitmap[i] & 1)
+                 return 1;
+
+             if (n >= CVMX_COREMASK_HLDRSZ)
+                 return 0;
+
+             return ((((1ull << n) - 1) & pcm->coremask_bitmap[i]) == 0);
+         }
+         else
+             n -= CVMX_COREMASK_HLDRSZ;
+     }
+
+     return 0;
+}
+
+/*
+ * Is the current core a member of the coremask?
+ *
+ * @param pcm is the pointer to the coremask.
+ * @return 1 for yes and 0 for no.
+ */
+static inline int cvmx_coremask_is_member_bmp(struct cvmx_coremask *pcm)
+{
+    return cvmx_coremask_is_set_core(pcm, (int)cvmx_get_core_num());
+}
+
 /*
  * coremask is simply unsigned int (32 bits).
  *
@@ -101,7 +257,7 @@ static inline unsigned int cvmx_coremask_core(unsigned int core_id)
  */
 static inline unsigned int cvmx_coremask_numcores(unsigned int num_cores)
 {
-    return (CVMX_COREMASK_MAX >> (32 - num_cores));
+    return (CVMX_COREMASK_MAX >> (CVMX_MAX_CORES - num_cores));
 }
 
 /**
@@ -115,7 +271,7 @@ static inline unsigned int cvmx_coremask_numcores(unsigned int num_cores)
  */
 static inline unsigned int cvmx_coremask_range(unsigned int low, unsigned int high)
 {
-    return ((CVMX_COREMASK_MAX >> (31 - high + low)) << low);
+    return ((CVMX_COREMASK_MAX >> (CVMX_MAX_CORES - 1 - high + low)) << low);
 }
 
 

sys/contrib/octeon-sdk/cvmx-crypto.c

@@ -1,6 +1,6 @@
 
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -16,7 +16,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -27,7 +27,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-crypto.h

@@ -1,6 +1,6 @@
 
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -16,7 +16,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -27,7 +27,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-csr-db-support.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Utility functions for working with the CSR database
  *
- * <hr>$Revision: 49507 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #define PRINTF printk
@@ -87,8 +87,16 @@ int cvmx_db_get_chipindex(int identifier)
             return 2;
         case 0x000d0700: /* CN52XX */
             return 10;
-        case 0x000d9000: /* CN63XX */
+        case 0x000d9300: /* CN61XX */
             return 11;
+        case 0x000d9000: /* CN63XX */
+            return 13;
+        case 0x000d9200: /* CN66XX */
+            return 14;
+        case 0x000d9100: /* CN68XX */
+            return 16;
+        case 0x000d9400: /* CNF71XX */
+            return 17;
     }
 
     /* Next try PCI device IDs */
@@ -114,8 +122,16 @@ int cvmx_db_get_chipindex(int identifier)
             return 8;
         case 0x0080177d: /* CN52XX Pass 2 */
             return 10;
-        case 0x0090177d: /* CN63XX Pass 1 */
+        case 0x0093177d: /* CN61XX Pass 2 */
             return 11;
+        case 0x0090177d: /* CN63XX Pass 2 */
+            return 13;
+        case 0x0092177d: /* CN66XX Pass 1 */
+            return 14;
+        case 0x0091177d: /* CN68XX Pass 2 */
+            return 16;
+        case 0x0094177d: /* CNF71XX Pass 1 */
+            return 17;
     }
 
     /* Default to Pass 3 if we don't know */

sys/contrib/octeon-sdk/cvmx-csr-db.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
  * Interface for the Octeon CSR database.
  *
  *
- * <hr>$Revision: 49507 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)

sys/contrib/octeon-sdk/cvmx-csr-enums.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
  * @file
  * Definitions for enumerations used with Octeon CSRs.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifndef __CVMX_CSR_ENUMS_H__

sys/contrib/octeon-sdk/cvmx-csr-typedefs.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,7 +46,7 @@
  *
  * This file is auto generated. Do not edit.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 69515 $<hr>
  *
  */
 #ifndef __CVMX_CSR_TYPEDEFS_H__
@@ -54,14 +54,19 @@
 #include "cvmx-agl-defs.h"
 #include "cvmx-asxx-defs.h"
 #include "cvmx-asx0-defs.h"
+#include "cvmx-ciu2-defs.h"
 #include "cvmx-ciu-defs.h"
 #include "cvmx-dbg-defs.h"
 #include "cvmx-dfa-defs.h"
 #include "cvmx-dfm-defs.h"
 #include "cvmx-dpi-defs.h"
+#include "cvmx-endor-defs.h"
+#include "cvmx-eoi-defs.h"
 #include "cvmx-fpa-defs.h"
 #include "cvmx-gmxx-defs.h"
 #include "cvmx-gpio-defs.h"
+#include "cvmx-ilk-defs.h"
+#include "cvmx-iob1-defs.h"
 #include "cvmx-iob-defs.h"
 #include "cvmx-ipd-defs.h"
 #include "cvmx-key-defs.h"
@@ -98,9 +103,10 @@
 #include "cvmx-sriox-defs.h"
 #include "cvmx-sriomaintx-defs.h"
 #include "cvmx-srxx-defs.h"
+#include "cvmx-sso-defs.h"
 #include "cvmx-stxx-defs.h"
 #include "cvmx-tim-defs.h"
-#include "cvmx-tra-defs.h"
+#include "cvmx-trax-defs.h"
 #include "cvmx-uahcx-defs.h"
 #include "cvmx-uctlx-defs.h"
 #include "cvmx-usbcx-defs.h"

sys/contrib/octeon-sdk/cvmx-csr.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Configuration and status register (CSR) address and type definitions for
  * Octoen.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 #ifndef __CVMX_CSR_H__

sys/contrib/octeon-sdk/cvmx-dbg-defs.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_DBG_TYPEDEFS_H__
-#define __CVMX_DBG_TYPEDEFS_H__
+#ifndef __CVMX_DBG_DEFS_H__
+#define __CVMX_DBG_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 #define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
@@ -71,12 +71,10 @@ static inline uint64_t CVMX_DBG_DATA_FUNC(void)
  *
  * Value returned on the debug-data lines from the RSLs
  */
-union cvmx_dbg_data
-{
+union cvmx_dbg_data {
 	uint64_t u64;
-	struct cvmx_dbg_data_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_23_63               : 41;
 	uint64_t c_mul                        : 5;  /**< C_MUL pins sampled at DCOK assertion */
 	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
@@ -89,9 +87,8 @@ union cvmx_dbg_data
 	uint64_t reserved_23_63               : 41;
 #endif
 	} s;
-	struct cvmx_dbg_data_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_31_63               : 33;
 	uint64_t pll_mul                      : 3;  /**< pll_mul pins sampled at DCOK assertion */
 	uint64_t reserved_23_27               : 5;
@@ -109,9 +106,8 @@ union cvmx_dbg_data
 #endif
 	} cn30xx;
 	struct cvmx_dbg_data_cn30xx           cn31xx;
-	struct cvmx_dbg_data_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t d_mul                        : 4;  /**< D_MUL pins sampled on DCOK assertion */
 	uint64_t dclk_mul2                    : 1;  /**< Should always be set for fast DDR-II operation */
@@ -132,9 +128,8 @@ union cvmx_dbg_data
 	} cn38xx;
 	struct cvmx_dbg_data_cn38xx           cn38xxp2;
 	struct cvmx_dbg_data_cn30xx           cn50xx;
-	struct cvmx_dbg_data_cn58xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_dbg_data_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_29_63               : 35;
 	uint64_t rem                          : 6;  /**< Remaining debug_select pins sampled at DCOK */
 	uint64_t c_mul                        : 5;  /**< C_MUL pins sampled at DCOK assertion */

sys/contrib/octeon-sdk/cvmx-debug-handler.S

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights 
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights 
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.  
@@ -26,7 +26,7 @@
  * countries. 
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -52,12 +52,13 @@
 #include <asm/octeon/cvmx-asm.h>
 #include <asm/octeon/octeon-boot-info.h>
 #else
-#include "executive-config.h"
+
 #include "cvmx-asm.h"
 
-#ifndef __OCTEON_NEWLIB__
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
+#ifndef _OCTEON_TOOLCHAIN_RUNTIME
+#include <octeon_mem_map.h>
 #else
+#include "cvmx-platform.h"
 #include "octeon-boot-info.h"
 #endif
 
@@ -97,7 +98,7 @@
 	sd k1, 0(t0);		\
 	addi k0, -8
 
-#define REG_SAVE_BASE_DIV_4  (BOOTLOADER_DEBUG_REG_SAVE_BASE >> 2)
+#define REG_SAVE_BASE_DIV_8  (BOOTLOADER_DEBUG_REG_SAVE_BASE >> 3)
 
 
 #define HW_INSTRUCTION_BREAKPOINT_STATUS            (0xFFFFFFFFFF301000)
@@ -145,10 +146,14 @@ __cvmx_debug_handler_stage2:
         andi    k0, 0xff    // mask off core ID
         sll     k0, 12      // multiply by 4096 (512 dwords) DEBUG_NUMREGS
 
-        addiu   k0,  REG_SAVE_BASE_DIV_4    
-        addiu   k0,  REG_SAVE_BASE_DIV_4
-        addiu   k0,  REG_SAVE_BASE_DIV_4
-        addiu   k0,  REG_SAVE_BASE_DIV_4
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
+        addiu   k0,  REG_SAVE_BASE_DIV_8
 		// add base offset - after exeption vectors for all cores
 
         rotr    k0, k0, 31   // set bit 31 for kseg0 access
@@ -241,6 +246,8 @@ noexc:
 #else
 	ld	sp,0(sp)
 #endif
+	mflo	$4
+	mfhi	$5
 	jal	__cvmx_debug_handler_stage3
 	nop
 

sys/contrib/octeon-sdk/cvmx-debug-remote.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,11 +46,10 @@
 #define cvmx_interrupt_in_isr 0
 
 #else
-#include "executive-config.h"
 #include "cvmx.h"
 #include "cvmx-debug.h"
 
-#ifndef __OCTEON_NEWLIB__
+#ifndef CVMX_BUILD_FOR_TOOLCHAIN
 extern int cvmx_interrupt_in_isr;
 #else
 #define cvmx_interrupt_in_isr 0

sys/contrib/octeon-sdk/cvmx-debug-uart.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -55,17 +55,17 @@ int cvmx_debug_uart = 1;
 #include "cvmx-debug.h"
 #include "cvmx-uart.h"
 #include "cvmx-spinlock.h"
-
-#ifndef __OCTEON_NEWLIB__
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-#else
 #include "octeon-boot-info.h"
 #endif
 
-#endif
+/* 
+ * NOTE: CARE SHOULD BE TAKEN USING STD C LIBRARY FUNCTIONS IN
+ * THIS FILE IF SOMEONE PUTS A BREAKPOINT ON THOSE FUNCTIONS
+ * DEBUGGING WILL FAIL.
+ */
 
 
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
 #pragma weak cvmx_uart_enable_intr
 int cvmx_debug_uart = 1;
 #endif
@@ -127,13 +127,30 @@ static void cvmx_debug_uart_init(void)
 static void cvmx_debug_uart_install_break_handler(void)
 {
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
     if (cvmx_uart_enable_intr)
 #endif
         cvmx_uart_enable_intr(cvmx_debug_uart, cvmx_debug_uart_process_debug_interrupt);
 #endif
 }
 
+/**
+ * Routines to handle hex data
+ *
+ * @param ch
+ * @return
+ */
+static inline int cvmx_debug_uart_hex(char ch)
+{
+    if ((ch >= 'a') && (ch <= 'f'))
+        return(ch - 'a' + 10);
+    if ((ch >= '0') && (ch <= '9'))
+        return(ch - '0');
+    if ((ch >= 'A') && (ch <= 'F'))
+        return(ch - 'A' + 10);
+    return(-1);
+}
+
 /* Get a packet from the UART, return 0 on failure and 1 on success. */
 
 static int cvmx_debug_uart_getpacket(char *buffer, size_t size)
@@ -174,22 +191,33 @@ static int cvmx_debug_uart_getpacket(char *buffer, size_t size)
 
         if (ch == '#')
         {
-	    char csumchars[2];
+	    char csumchars0, csumchars1;
 	    unsigned xmitcsum;
-	    int n;
+	    int n0, n1;
 
-            csumchars[0] = cvmx_uart_read_byte(cvmx_debug_uart);
-            csumchars[1] = cvmx_uart_read_byte(cvmx_debug_uart);
-	    n = sscanf(csumchars, "%2x", &xmitcsum);
-	    if (n != 1)
-		return 1;
+            csumchars0 = cvmx_uart_read_byte(cvmx_debug_uart);
+            csumchars1 = cvmx_uart_read_byte(cvmx_debug_uart);
+            n0 = cvmx_debug_uart_hex(csumchars0);
+            n1 = cvmx_debug_uart_hex(csumchars1);
+	    if (n0 == -1 || n1 == -1)
+		return 0;
 
+            xmitcsum = (n0 << 4) | n1;
             return checksum == xmitcsum;
         }
     }
     return 0;
 }
 
+/* Put the hex value of t into str. */
+static void cvmx_debug_uart_strhex(char *str, unsigned char t)
+{
+  char hexchar[] = "0123456789ABCDEF";
+  str[0] = hexchar[(t>>4)];
+  str[1] = hexchar[t&0xF];
+  str[2] = 0;
+}
+
 static int cvmx_debug_uart_putpacket(char *packet)
 {
     size_t i;
@@ -199,7 +227,7 @@ static int cvmx_debug_uart_putpacket(char *packet)
 
     for (csum = 0, i = 0; ptr[i]; i++)
       csum += ptr[i];
-    sprintf(csumstr, "%02x", csum);
+    cvmx_debug_uart_strhex(csumstr, csum);
 
     cvmx_spinlock_lock(&cvmx_debug_uart_lock);
     cvmx_uart_write_byte(cvmx_debug_uart, '$');
@@ -217,12 +245,12 @@ static void cvmx_debug_uart_change_core(int oldcore, int newcore)
     cvmx_ciu_intx0_t irq_control;
 
     irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(newcore * 2));
-    irq_control.s.uart |= (1<<cvmx_debug_uart);
+    irq_control.s.uart |= (1u<<cvmx_debug_uart);
     cvmx_write_csr(CVMX_CIU_INTX_EN0(newcore * 2), irq_control.u64);
 
     /* Disable interrupts to this core since he is about to die */
     irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(oldcore * 2));
-    irq_control.s.uart &= ~(1<<cvmx_debug_uart);
+    irq_control.s.uart &= ~(1u<<cvmx_debug_uart);
     cvmx_write_csr(CVMX_CIU_INTX_EN0(oldcore* 2), irq_control.u64);
 #endif
 }

sys/contrib/octeon-sdk/cvmx-debug.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -42,6 +42,9 @@
  * @file
  *
  * Interface to debug exception handler
+ * NOTE: CARE SHOULD BE TAKE WHEN USING STD C LIBRARY FUNCTIONS IN
+ * THIS FILE IF SOMEONE PUTS A BREAKPOINT ON THOSE FUNCTIONS
+ * DEBUGGING WILL FAIL.
  *
  * <hr>$Revision: 50060 $<hr>
  */
@@ -56,21 +59,14 @@
 #include <asm/octeon/octeon-boot-info.h>
 #else
 #include <stdint.h>
-#include "executive-config.h"
 #include "cvmx.h"
 #include "cvmx-debug.h"
 #include "cvmx-bootmem.h"
 #include "cvmx-core.h"
 #include "cvmx-coremask.h"
-
-#ifndef __OCTEON_NEWLIB__
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-#else
 #include "octeon-boot-info.h"
 #endif
 
-#endif
-
 #ifdef CVMX_DEBUG_LOGGING
 # undef CVMX_DEBUG_LOGGING
 # define CVMX_DEBUG_LOGGING 1
@@ -119,33 +115,84 @@ volatile uint64_t __cvmx_debug_mode_exception_occured;
 static char cvmx_debug_stack[8*1024] __attribute ((aligned (16)));
 char *__cvmx_debug_stack_top = &cvmx_debug_stack[8*1024];
 
-#ifndef __OCTEON_NEWLIB__
+#ifndef CVMX_BUILD_FOR_TOOLCHAIN
 extern int cvmx_interrupt_in_isr;
 #else
 #define cvmx_interrupt_in_isr 0
 #endif
 
 #else
-uint64_t __cvmx_debug_save_regs_area_all[OCTEON_NUM_CORES][32];
+uint64_t __cvmx_debug_save_regs_area_all[CVMX_MAX_CORES][32];
 #define __cvmx_debug_save_regs_area __cvmx_debug_save_regs_area_all[cvmx_get_core_num()]
 
-volatile uint64_t __cvmx_debug_mode_exception_ignore_all[OCTEON_NUM_CORES];
+volatile uint64_t __cvmx_debug_mode_exception_ignore_all[CVMX_MAX_CORES];
 #define __cvmx_debug_mode_exception_ignore __cvmx_debug_mode_exception_ignore_all[cvmx_get_core_num()]
-volatile uint64_t __cvmx_debug_mode_exception_occured_all[OCTEON_NUM_CORES];
+volatile uint64_t __cvmx_debug_mode_exception_occured_all[CVMX_MAX_CORES];
 #define __cvmx_debug_mode_exception_occured __cvmx_debug_mode_exception_occured_all[cvmx_get_core_num()]
 
-static char cvmx_debug_stack_all[OCTEON_NUM_CORES][8*1024] __attribute ((aligned (16)));
-char *__cvmx_debug_stack_top_all[OCTEON_NUM_CORES];
+static char cvmx_debug_stack_all[CVMX_MAX_CORES][8*1024] __attribute ((aligned (16)));
+char *__cvmx_debug_stack_top_all[CVMX_MAX_CORES];
 
 #define cvmx_interrupt_in_isr 0
 
 #endif
 
 
+static size_t cvmx_debug_strlen (const char *str)
+{
+    size_t size = 0;
+    while (*str)
+    {
+        size++;
+        str++;
+    }
+    return size;
+}
+static void cvmx_debug_strcpy (char *dest, const char *src)
+{
+    while (*src)
+    {
+        *dest = *src;
+        src++;
+        dest++;
+    }
+    *dest = 0;
+}
+
+static void cvmx_debug_memcpy_align (void *dest, const void *src, int size) __attribute__ ((__noinline__));
+static void cvmx_debug_memcpy_align (void *dest, const void *src, int size)
+{
+  long long *dest1 = (long long*)dest;
+  const long long *src1 = (const long long*)src;
+  int i;
+  if (size == 40)
+  {
+    long long a0, a1, a2, a3, a4;
+    a0 = src1[0];
+    a1 = src1[1];
+    a2 = src1[2];
+    a3 = src1[3];
+    a4 = src1[4];
+    dest1[0] = a0;
+    dest1[1] = a1;
+    dest1[2] = a2;
+    dest1[3] = a3;
+    dest1[4] = a4;
+    return;
+  }
+  for(i = 0;i < size;i+=8)
+  {
+    *dest1 = *src1;
+    dest1++;
+    src1++;
+  }
+}
+
+
 static inline uint32_t cvmx_debug_core_mask(void)
 {
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
   extern int __octeon_core_mask;
   return __octeon_core_mask;
 #endif
@@ -157,13 +204,13 @@ return octeon_get_boot_coremask ();
 
 static inline void cvmx_debug_update_state(cvmx_debug_state_t state)
 {
-    memcpy(cvmx_debug_globals->state, &state, sizeof(cvmx_debug_state_t));
+    cvmx_debug_memcpy_align(cvmx_debug_globals->state, &state, sizeof(cvmx_debug_state_t));
 }
 
 static inline cvmx_debug_state_t cvmx_debug_get_state(void)
 {
     cvmx_debug_state_t state;
-    memcpy(&state, cvmx_debug_globals->state, sizeof(cvmx_debug_state_t));
+    cvmx_debug_memcpy_align(&state, cvmx_debug_globals->state, sizeof(cvmx_debug_state_t));
     return state;
 }
 
@@ -201,53 +248,31 @@ static int cvmx_debug_enabled(void)
     return cvmx_debug_booted() || CVMX_DEBUG_ATTACH;
 }
 
+static void cvmx_debug_init_global_ptr (void *ptr)
+{
+    uint64_t phys = cvmx_ptr_to_phys (ptr);
+    cvmx_debug_globals_t *p;
+    /* Since at this point, TLBs are not mapped 1 to 1, we should just use KSEG0 accesses. */
+    p = CASTPTR(cvmx_debug_globals_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, phys));
+    memset (p, 0, sizeof(cvmx_debug_globals_t));
+    p->version = CVMX_DEBUG_GLOBALS_VERSION;
+    p->tlb_entries = cvmx_core_get_tlb_entries();
+}
+
 static void cvmx_debug_init_globals(void)
 {
-    int toclear = 0;
     uint64_t phys;
-    void *a;
+    void *ptr;
 
     if (cvmx_debug_globals)
         return;
+    ptr = cvmx_bootmem_alloc_named_range_once(sizeof(cvmx_debug_globals_t), 0, /* KSEG0 max, 512MB=*/0/*1024*1024*512*/, 8,
+                                              CVMX_DEBUG_GLOBALS_BLOCK_NAME, cvmx_debug_init_global_ptr);
+    phys = cvmx_ptr_to_phys (ptr);
 
-    if (cvmx_get_core_num() != 0)
-    {
-        volatile size_t i;
-        /* Delay here just enough for the writing of the version. */
-        for(i = 0; i < sizeof(cvmx_debug_globals_t)/2 + 8; i++)
-          ;
-    }
-
-    a = cvmx_bootmem_alloc_named(sizeof(cvmx_debug_globals_t), 8, CVMX_DEBUG_GLOBALS_BLOCK_NAME);
-    if (a)
-    {
-       phys = cvmx_ptr_to_phys(a);
-       toclear = 1;
-    }
-    else
-    {
-        const cvmx_bootmem_named_block_desc_t *debug_globals_nblk;
-        debug_globals_nblk = cvmx_bootmem_find_named_block (CVMX_DEBUG_GLOBALS_BLOCK_NAME);
-        phys = debug_globals_nblk->base_addr;
-    }
+    /* Since TLBs are not always mapped 1 to 1, we should just use access via KSEG0. */
     cvmx_debug_globals = CASTPTR(cvmx_debug_globals_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, phys));
     cvmx_debug_printf("Debug named block at %p\n", cvmx_debug_globals);
-    if (toclear)
-        cvmx_debug_printf("Debug named block cleared\n");
-
-    if (toclear)
-    {
-        memset (cvmx_debug_globals, 0, sizeof(cvmx_debug_globals_t));
-        cvmx_debug_globals->version = CVMX_DEBUG_GLOBALS_VERSION;
-        cvmx_debug_globals->tlb_entries = cvmx_core_get_tlb_entries();
-    }
-    else
-    {
-        volatile size_t i;
-        /* Delay here just enough for the writing of the version. */
-        for(i = 0; i < sizeof(cvmx_debug_globals_t) + 8; i++)
-          ;
-    }
 }
 
 
@@ -265,7 +290,7 @@ static void cvmx_debug_globals_check_version(void)
 }
 
 static inline volatile cvmx_debug_core_context_t *cvmx_debug_core_context(void);
-static inline void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context);
+static inline void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context, uint64_t hi, uint64_t lo);
 
 void cvmx_debug_init(void)
 {
@@ -295,9 +320,9 @@ void cvmx_debug_init(void)
     /*  Install the debugger handler on the cores. */
     {
         int core1 = 0;
-        for (core1 = 0; core1 < OCTEON_NUM_CORES; core1++)
+        for (core1 = 0; core1 < CVMX_MAX_CORES; core1++)
         {
-            if ((1<<core1) & coremask)
+            if ((1u<<core1) & coremask)
                 cvmx_debug_install_handler(core1);
         }
     }
@@ -315,8 +340,8 @@ void cvmx_debug_init(void)
         state.known_cores |= coremask;
         state.core_finished &= ~coremask;
 #else
-        state.known_cores |= (1 << core);
-        state.core_finished &= ~(1 << core);
+        state.known_cores |= (1u << core);
+        state.core_finished &= ~(1u << core);
 #endif
         cvmx_debug_update_state(state);
         cvmx_spinlock_unlock(lock);
@@ -342,7 +367,7 @@ void cvmx_debug_init(void)
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
         {
             int i;
-            for (i = 0; i < OCTEON_NUM_CORES; i++)
+            for (i = 0; i < CVMX_MAX_CORES; i++)
                 __cvmx_debug_stack_top_all[i] = &cvmx_debug_stack_all[i][8*1024];
         }
 #endif
@@ -367,27 +392,34 @@ void cvmx_debug_init(void)
     }
 }
 
-static int cvmx_debug_putpacket_noformat(char *packet);
-
-static __attribute__ ((format (printf, 1, 2))) int cvmx_debug_putpacket(char *format, ...)
+static const char cvmx_debug_hexchar[] = "0123456789ABCDEF";
+/* Put the hex value of t into str. */
+static void cvmx_debug_int8_to_strhex(char *str, unsigned char t)
 {
-    va_list ap;
-    size_t n;
-    char packet[CVMX_DEBUG_MAX_RESPONSE_SIZE];
+  str[0] = cvmx_debug_hexchar[(t>>4)&0xf];
+  str[1] = cvmx_debug_hexchar[t&0xF];
+  str[2] = 0;
+}
 
-    if (cvmx_debug_comms[cvmx_debug_globals->comm_type]->putpacket == NULL)
-        return 0;
-
-    va_start(ap, format);
-    n = vsnprintf(packet, sizeof(packet), format, ap);
-    va_end(ap);
-
-    if (n >= sizeof(packet))
-    {
-        cvmx_debug_printf("packet truncated (needed %d bytes): %s\n", (int)n, packet);
-        return 0;
-    }
-    return cvmx_debug_putpacket_noformat(packet);
+static void cvmx_debug_int64_to_strhex(char *str, uint64_t t)
+{
+  str[0] = cvmx_debug_hexchar[(t>>60)&0xF];
+  str[1] = cvmx_debug_hexchar[(t>>56)&0xF];
+  str[2] = cvmx_debug_hexchar[(t>>52)&0xF];
+  str[3] = cvmx_debug_hexchar[(t>>48)&0xF];
+  str[4] = cvmx_debug_hexchar[(t>>44)&0xF];
+  str[5] = cvmx_debug_hexchar[(t>>40)&0xF];
+  str[6] = cvmx_debug_hexchar[(t>>36)&0xF];
+  str[7] = cvmx_debug_hexchar[(t>>32)&0xF];
+  str[8] = cvmx_debug_hexchar[(t>>28)&0xF];
+  str[9] = cvmx_debug_hexchar[(t>>24)&0xF];
+  str[10] = cvmx_debug_hexchar[(t>>20)&0xF];
+  str[11] = cvmx_debug_hexchar[(t>>16)&0xF];
+  str[12] = cvmx_debug_hexchar[(t>>12)&0xF];
+  str[13] = cvmx_debug_hexchar[(t>>8)&0xF];
+  str[14] = cvmx_debug_hexchar[(t>>4)&0xF];
+  str[15] = cvmx_debug_hexchar[(t>>0)&0xF];
+  str[16] = 0;
 }
 
 static int cvmx_debug_putpacket_noformat(char *packet)
@@ -398,9 +430,50 @@ static int cvmx_debug_putpacket_noformat(char *packet)
     return cvmx_debug_comms[cvmx_debug_globals->comm_type]->putpacket(packet);
 }
 
-static int cvmx_debug_active_core(cvmx_debug_state_t state, int core)
+static int cvmx_debug_putcorepacket(char *buf, int core)
 {
-    return state.active_cores & (1 << core);
+     char *tmp = "!Core XX ";
+     int tmpsize = cvmx_debug_strlen(tmp);
+     int bufsize = cvmx_debug_strlen(buf);
+     char *packet = __builtin_alloca(tmpsize + bufsize + 1);
+     cvmx_debug_strcpy(packet, tmp);
+     cvmx_debug_strcpy(&packet[tmpsize], buf);
+     if (core < 10)
+     {
+         packet[6] = ' ';
+         packet[7] = core + '0';
+     }
+     else if (core < 20)
+     {
+         packet[6] = '1';
+         packet[7] = core - 10 + '0';
+     }
+     else if (core < 30)
+     {
+         packet[6] = '2';
+         packet[7] = core - 20 + '0';
+     }
+     else
+     {
+         packet[6] = '3';
+         packet[7] = core - 30 + '0';
+     }
+     return cvmx_debug_putpacket_noformat(packet);
+}
+
+/* Put a buf followed by an integer formated as a hex.  */
+static int cvmx_debug_putpacket_hexint(char *buf, uint64_t value)
+{
+    size_t size = cvmx_debug_strlen(buf);
+    char *packet = __builtin_alloca(size + 16 + 1);
+    cvmx_debug_strcpy(packet, buf);
+    cvmx_debug_int64_to_strhex(&packet[size], value);
+    return cvmx_debug_putpacket_noformat(packet);
+}
+
+static int cvmx_debug_active_core(cvmx_debug_state_t state, unsigned core)
+{
+    return state.active_cores & (1u << core);
 }
 
 static volatile cvmx_debug_core_context_t *cvmx_debug_core_context(void)
@@ -470,22 +543,59 @@ static int cvmx_debug_probe_store(unsigned char *ptr)
     return ok;
 }
 
-/* Put the hex value of t into str. */
-static void strhex(char *str, unsigned char t)
+
+/**
+ * Routines to handle hex data
+ *
+ * @param ch
+ * @return
+ */
+static inline int cvmx_debug_hex(char ch)
 {
-  char a[] = "0123456789ABCDEF";
-  str[0] = a[(t>>4)];
-  str[1] = a[t&0xF];
-  str[2] = 0;
+    if ((ch >= 'a') && (ch <= 'f'))
+        return(ch - 'a' + 10);
+    if ((ch >= '0') && (ch <= '9'))
+        return(ch - '0');
+    if ((ch >= 'A') && (ch <= 'F'))
+        return(ch - 'A' + 10);
+    return(-1);
+}
+
+/**
+ * While we find nice hex chars, build an int.
+ * Return number of chars processed.
+ *
+ * @param ptr
+ * @param intValue
+ * @return
+ */
+static int cvmx_debug_hexToLong(const char **ptr, uint64_t *intValue)
+{
+    int numChars = 0;
+    long hexValue;
+
+    *intValue = 0;
+    while (**ptr)
+    {
+        hexValue = cvmx_debug_hex(**ptr);
+        if (hexValue < 0)
+            break;
+
+        *intValue = (*intValue << 4) | hexValue;
+        numChars ++;
+
+        (*ptr)++;
+    }
+
+    return(numChars);
 }
 
 /**
   * Initialize the performance counter control registers.
   *
   */
-static void cvmx_debug_set_perf_control_reg (int perf_event, int perf_counter)
+static void cvmx_debug_set_perf_control_reg (volatile cvmx_debug_core_context_t *context, int perf_event, int perf_counter)
 {
-    volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
     cvmx_core_perf_control_t control;
 
     control.u32 = 0;
@@ -500,7 +610,7 @@ static void cvmx_debug_set_perf_control_reg (int perf_event, int perf_counter)
     context->cop0.perfctrl[perf_counter] = control.u32;
 }
 
-static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
+static cvmx_debug_command_t cvmx_debug_process_packet(const char *packet)
 {
     const char *buf = packet;
     cvmx_debug_command_t result = COMMAND_NOP;
@@ -519,18 +629,20 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
 
         case 'F':   /* Change the focus core */
         {
-            int core;
-            sscanf(buf, "%x", &core);
-
+            uint64_t core;
+            if (!cvmx_debug_hexToLong(&buf, &core))
+            {
+                cvmx_debug_putpacket_noformat("!Uknown core.  Focus not changed.");
+            }
             /* Only cores in the exception handler may become the focus.
-            If a core not in the exception handler got focus the
-            debugger would hang since nobody would talk to it.  */
-            if (state.handler_cores & (1 << core))
+               If a core not in the exception handler got focus the
+               debugger would hang since nobody would talk to it.  */
+            else if (state.handler_cores & (1u << core))
             {
                 /* Focus change reply must be sent before the focus
-                changes. Otherwise the new focus core will eat our ACK
-                from the debugger.  */
-                cvmx_debug_putpacket("F%02x", core);
+                   changes. Otherwise the new focus core will eat our ACK
+                   from the debugger.  */
+                cvmx_debug_putpacket_hexint("F", core);
                 cvmx_debug_comms[cvmx_debug_globals->comm_type]->change_core(state.focus_core, core);
                 state.focus_core = core;
                 cvmx_debug_update_state(state);
@@ -542,7 +654,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
         }
         /* fall through */
         case 'f':   /* Get the focus core */
-            cvmx_debug_putpacket("F%02x", (unsigned)state.focus_core);
+            cvmx_debug_putpacket_hexint("F", state.focus_core);
             break;
 
         case 'J': /* Set the flag for skip-over-isr in Single-Stepping mode */
@@ -557,14 +669,15 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
            same as the get step-isr command */
 
         case 'j':   /* Reply with step_isr status  */
-            cvmx_debug_putpacket("J%x", (unsigned)state.step_isr);
+            cvmx_debug_putpacket_hexint("J", (unsigned)state.step_isr);
             break;
 
 
         case 'I':   /* Set the active cores */
         {
-            long long active_cores;
-            sscanf(buf, "%llx", &active_cores);
+            uint64_t active_cores;
+            if (!cvmx_debug_hexToLong(&buf, &active_cores))
+                active_cores = 0;
             /* Limit the active mask to the known to exist cores */
             state.active_cores = active_cores & state.known_cores;
 
@@ -573,10 +686,10 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 state.active_cores = state.known_cores;
 
             /* The focus core must be in the active_cores mask */
-            if ((state.active_cores & (1 << state.focus_core)) == 0)
+            if ((state.active_cores & (1u << state.focus_core)) == 0)
             {
                 cvmx_debug_putpacket_noformat("!Focus core was added to the masked.");
-                state.active_cores |= 1 << state.focus_core;
+                state.active_cores |= 1u << state.focus_core;
             }
 
             cvmx_debug_update_state(state);
@@ -585,7 +698,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
            same as the get active cores command */
 
         case 'i':   /* Get the active cores */
-            cvmx_debug_putpacket("I%llx", (long long) state.active_cores);
+            cvmx_debug_putpacket_hexint("I", state.active_cores);
             break;
 
         case 'A':   /* Setting the step mode all or one */
@@ -600,34 +713,46 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
            same as the get step-all command */
 
         case 'a':   /* Getting the current step mode */
-            cvmx_debug_putpacket("A%x", (unsigned)state.step_all);
+            cvmx_debug_putpacket_hexint("A", state.step_all);
             break;
 
         case 'g':   /* read a register from global place. */
         {
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
-            int regno;
+            uint64_t regno;
             volatile uint64_t *reg;
 
             /* Get the register number to read */
-            sscanf(buf, "%x", &regno);
+            if (!cvmx_debug_hexToLong(&buf, &regno))
+            {
+                cvmx_debug_printf("Register number cannot be read.\n");
+                cvmx_debug_putpacket_hexint("", 0xDEADBEEF);
+                break;
+            }
 
             reg = cvmx_debug_regnum_to_context_ref(regno, context);
             if (!reg)
-                cvmx_debug_printf("Register #%d is not valid\n", regno);
-            cvmx_debug_putpacket("%llx", (unsigned long long) *reg);
+            {
+                cvmx_debug_printf("Register #%d is not valid\n", (int)regno);
+                cvmx_debug_putpacket_hexint("", 0xDEADBEEF);
+                break;
+            }
+            cvmx_debug_putpacket_hexint("", *reg);
         }
         break;
 
         case 'G':   /* set the value of a register. */
         {
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
-            int regno;
+            uint64_t regno;
             volatile uint64_t *reg;
-            long long value;
+            uint64_t value;
 
-            /* Get the register number to read */
-            if (sscanf(buf, "%x,%llx", &regno, &value) != 2)
+            /* Get the register number to write. It should be followed by
+               a comma */
+            if (!cvmx_debug_hexToLong(&buf, &regno)
+                || (*buf++ != ',')
+                || !cvmx_debug_hexToLong(&buf, &value))
             {
                 cvmx_debug_printf("G packet corrupt: %s\n", buf);
                 goto error_packet;
@@ -636,7 +761,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
             reg = cvmx_debug_regnum_to_context_ref(regno, context);
             if (!reg)
             {
-                cvmx_debug_printf("Register #%d is not valid\n", regno);
+                cvmx_debug_printf("Register #%d is not valid\n", (int)regno);
                 goto error_packet;
             }
             *reg = value;
@@ -645,18 +770,21 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
 
         case 'm':   /* Memory read. mAA..AA,LLLL  Read LLLL bytes at address AA..AA */
         {
-            long long addr, i, length;
+            uint64_t addr, i, length;
             unsigned char *ptr;
             char *reply;
 
-            if (sscanf(buf, "%llx,%llx", &addr, &length) != 2)
+            /* Get the memory address, a comma, and the length */
+            if (!cvmx_debug_hexToLong(&buf, &addr)
+                || (*buf++ != ',')
+                || !cvmx_debug_hexToLong(&buf, &length))
             {
                 cvmx_debug_printf("m packet corrupt: %s\n", buf);
                 goto error_packet;
             }
             if (length >= 1024)
             {
-                cvmx_debug_printf("m packet length out of range: %lld\n", length);
+                cvmx_debug_printf("m packet length out of range: %lld\n", (long long)length);
                 goto error_packet;
             }
 
@@ -668,7 +796,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 unsigned char t;
                 if (!cvmx_debug_probe_load(&ptr[i], &t))
                   goto error_packet;
-                strhex(&reply[i * 2], t);
+                cvmx_debug_int8_to_strhex(&reply[i * 2], t);
             }
             cvmx_debug_putpacket_noformat(reply);
         }
@@ -676,28 +804,31 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
 
         case 'M':   /* Memory write. MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
         {
-            long long addr, i, length;
+            uint64_t addr, i, length;
             unsigned char *ptr;
-            char value[1024];
 
-            if (sscanf(buf, "%llx,%llx:%1024s", &addr, &length, value) != 3)
+            if (!cvmx_debug_hexToLong(&buf, &addr)
+                || *buf++ != ','
+                || !cvmx_debug_hexToLong(&buf, &length)
+                || *buf++ != ':')
             {
                 cvmx_debug_printf("M packet corrupt: %s\n", buf);
                 goto error_packet;
             }
-            
+
             ptr = (unsigned char *)(long)addr;
             for (i = 0; i < length; i++)
             {
-                int c;
-                int n;
-                char tempstr[3] = {0, 0, 0};
-                memcpy (tempstr, &value[i * 2], 2);
+                int n, n1;
+                unsigned char c;
+
+                n = cvmx_debug_hex(buf[i * 2]);
+                n1 = cvmx_debug_hex(buf[i * 2 + 1]);
+                c = (n << 4) | n1;
             
-                n = sscanf(tempstr, "%2x", &c);
-                if (n != 1)
+                if (n == -1 || n1 == -1)
                 {
-                    cvmx_debug_printf("M packet corrupt: %s\n", &value[i * 2]);
+                    cvmx_debug_printf("M packet corrupt: %s\n", &buf[i * 2]);
                     goto error_packet;
                 }
                 /* Probe memory.  If not accessible fail.   */
@@ -716,30 +847,38 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                       is the performance counter to set X is the performance
                       event.  [34] is to get the same thing.  */
         {
-            int perf_event = 0;
-            int counter, encoded_counter;
+            uint64_t perf_event = 0;
+            char encoded_counter = *buf++;
+            uint64_t counter;
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
-            sscanf(buf, "%1d%x", &encoded_counter, &perf_event);
+
+            /* Ignore errors from the packet. */
+            cvmx_debug_hexToLong(&buf, &perf_event);
 
             switch (encoded_counter)
             {
-                case 1: /* Set performance counter0 event. */
-                case 2: /* Set performance counter1 event. */
+                case '1': /* Set performance counter0 event. */
+                case '2': /* Set performance counter1 event. */
 
-                counter = encoded_counter - 1;
+                counter = encoded_counter - '1';
                 context->cop0.perfval[counter] = 0;
-                cvmx_debug_set_perf_control_reg(perf_event, counter);
+                cvmx_debug_set_perf_control_reg(context, perf_event, counter);
                 break;
 
-                case 3: /* Get performance counter0 event. */
-                case 4: /* Get performance counter1 event. */
+                case '3': /* Get performance counter0 event. */
+                case '4': /* Get performance counter1 event. */
                 {
                     cvmx_core_perf_control_t c;
-                    counter = encoded_counter - 3;
+                    char outpacket[16*2 +2];
+                    counter = encoded_counter - '3';
                     /* Pass performance counter0 event and counter to
                        the debugger.  */
                     c.u32 = context->cop0.perfctrl[counter];
-                    cvmx_debug_putpacket("%llx,%llx", (long long) context->cop0.perfval[counter], (long long) c.s.event);
+                    cvmx_debug_int64_to_strhex(outpacket, context->cop0.perfval[counter]);
+                    outpacket[16] = ',';
+                    cvmx_debug_int64_to_strhex(&outpacket[17], c.s.event);
+                    outpacket[33] = 0;
+                    cvmx_debug_putpacket_noformat(outpacket);
                 }
                 break;
             }
@@ -782,21 +921,27 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 WP_ACCESS = 3
             };
 
-            int num, size;
-            long long addr;
-            enum type type;
-            char bp_type;
+            uint64_t num, size;
+            uint64_t addr;
+            uint64_t type;
+            char bp_type = *buf++;
             const int BE = 1, TE = 4;
-            int n;
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
 
-            n = sscanf(buf, "%c%x,%llx,%x,%x", &bp_type, &num, &addr, &size, &type);
+            if (!cvmx_debug_hexToLong(&buf, &num)
+                || *buf++ != ','
+                || !cvmx_debug_hexToLong(&buf, &addr))
+            {
+                cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
+                goto error_packet;
+            }
+
             switch (bp_type)
             {
                 case 'i':	// Instruction hardware breakpoint
-                    if (n != 3 || num > 4)
+                    if (num > 4)
                     {
-                        cvmx_debug_printf("Z packet corrupt: %s\n", buf);
+                        cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
                         goto error_packet;
                     }
 
@@ -810,9 +955,15 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                 {
                     uint64_t dbc = 0xff0 | BE | TE;
                     uint64_t dbm;
-                    if (n != 5 || num > 4)
+                    if (num > 4
+                        || *buf++ != ','
+                        || !cvmx_debug_hexToLong(&buf, &size)
+                        || *buf++ != ','
+                        || !cvmx_debug_hexToLong(&buf, &type)
+                        || type > WP_ACCESS
+                        || type < WP_LOAD)
                     {
-                        cvmx_debug_printf("Z packet corrupt: %s\n", buf);
+                        cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
                         goto error_packet;
                     }
 
@@ -831,7 +982,7 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
                     break;
                 }
                 default:
-                    cvmx_debug_printf("z packet corrupt: %s\n", buf);
+                    cvmx_debug_printf("Z packet corrupt: %s\n", &packet[1]);
                     goto error_packet;
             }
         }
@@ -840,11 +991,11 @@ static cvmx_debug_command_t cvmx_debug_process_packet(char *packet)
         case 'z': /* Remove hardware breakpoint: z[di]NN..N remove NN..Nth
 breakpoint.  */
         {
-            int num;
-            char bp_type;
+            uint64_t num;
+            char bp_type = *buf++;
             volatile cvmx_debug_core_context_t *context = cvmx_debug_core_context();
 
-            if (sscanf(buf, "%c%x", &bp_type, &num) != 2 || num > 4)
+            if (!cvmx_debug_hexToLong(&buf, &num) || num > 4)
             {
                 cvmx_debug_printf("z packet corrupt: %s\n", buf);
                 goto error_packet;
@@ -919,7 +1070,7 @@ static int cvmx_debug_stop_core(cvmx_debug_state_t state, unsigned core, cvmx_de
         cvmx_debug_printf("Core #%d not in active cores, continuing.\n", core);
         return 0;
     }
-    if ((state.core_finished & (1<<core)) && proxy)
+    if ((state.core_finished & (1u<<core)) && proxy)
       return 0;
     return 1;
 }
@@ -936,7 +1087,7 @@ static int cvmx_debug_single_step_exc(cvmx_debug_register_t *debug_reg)
 static void cvmx_debug_set_focus_core(cvmx_debug_state_t *state, int core)
 {
     if (state->ever_been_in_debug)
-        cvmx_debug_putpacket("!Core %2x taking focus.", core);
+        cvmx_debug_putcorepacket("taking focus.", core);
     cvmx_debug_comms[cvmx_debug_globals->comm_type]->change_core (state->focus_core, core);
     state->focus_core = core;
 }
@@ -944,7 +1095,7 @@ static void cvmx_debug_set_focus_core(cvmx_debug_state_t *state, int core)
 static void cvmx_debug_may_elect_as_focus_core(cvmx_debug_state_t *state, int core, cvmx_debug_register_t *debug_reg)
 {
     /* If another core has already elected itself as the focus core, we're late.  */
-    if (state->handler_cores & (1 << state->focus_core))
+    if (state->handler_cores & (1u << state->focus_core))
         return;
 
     /* If we hit a breakpoint, elect ourselves.  */
@@ -954,7 +1105,7 @@ static void cvmx_debug_may_elect_as_focus_core(cvmx_debug_state_t *state, int co
     /* It is possible the focus core has completed processing and exited the
        program. When this happens the focus core will not be in
        known_cores. If this is the case we need to elect a new focus. */
-    if ((state->known_cores & (1 << state->focus_core)) == 0)
+    if ((state->known_cores & (1u << state->focus_core)) == 0)
         cvmx_debug_set_focus_core(state, core);
 }
 
@@ -962,7 +1113,7 @@ static void cvmx_debug_send_stop_reason(cvmx_debug_register_t *debug_reg, volati
 {
     /* Handle Debug Data Breakpoint Store/Load Exception. */
     if (debug_reg->s.ddbs || debug_reg->s.ddbl)
-        cvmx_debug_putpacket("T8:%x", (int) context->hw_dbp.status);
+        cvmx_debug_putpacket_hexint("T8:", (int) context->hw_dbp.status);
     else
         cvmx_debug_putpacket_noformat("T9");
 }
@@ -980,10 +1131,12 @@ static void cvmx_debug_clear_status(volatile cvmx_debug_core_context_t *context)
 
 static void cvmx_debug_sync_up_cores(void)
 {
-    cvmx_debug_state_t state;
+    /* NOTE this reads directly from the state array for speed reasons
+       and we don't change the array. */
     do {
-        state = cvmx_debug_get_state();
-    } while (state.step_all && state.handler_cores != 0);
+      asm("": : : "memory");
+    } while (cvmx_debug_globals->state[offsetof(cvmx_debug_state_t, step_all)/sizeof(uint32_t)]
+	     && cvmx_debug_globals->state[offsetof(cvmx_debug_state_t, handler_cores)/sizeof(uint32_t)] != 0);
 }
 
 /* Delay the focus core a little if it is likely another core needs to steal
@@ -993,7 +1146,7 @@ static void cvmx_debug_delay_focus_core(cvmx_debug_state_t state, unsigned core,
     volatile int i;
     if (debug_reg->s.dss || debug_reg->s.dbp || core != state.focus_core)
         return;
-    for (i = 0; i < 24000; i++)
+    for (i = 0; i < 2400; i++)
     {
         asm volatile (".set push		\n\t"
                       ".set noreorder		\n\t"
@@ -1086,7 +1239,7 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
         cvmx_spinlock_lock(&cvmx_debug_globals->lock);
         state = cvmx_debug_get_state();
 
-        state.handler_cores |= (1 << core);
+        state.handler_cores |= (1u << core);
         cvmx_debug_may_elect_as_focus_core(&state, core, debug_reg);
 
 /* Push all updates before exiting the critical section */
@@ -1098,10 +1251,17 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
         cvmx_debug_send_stop_reason(debug_reg, context);
 
     do {
+        unsigned oldfocus = state.focus_core;
         state = cvmx_debug_get_state();
         /* Note the focus core can change in this loop. */
         if (__cvmx_debug_in_focus(state, core))
         {
+            /* If the focus has changed and the old focus has exited, then send a signal
+               that we should stop if step_all is off.  */
+            if (oldfocus != state.focus_core && ((1u << oldfocus) & state.core_finished)
+                && !state.step_all)
+              cvmx_debug_send_stop_reason(debug_reg, context);
+
             command = cvmx_debug_process_next_packet();
             state = cvmx_debug_get_state();
             /* When resuming let the other cores resume as well with
@@ -1135,7 +1295,7 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
     {
         cvmx_spinlock_lock(&cvmx_debug_globals->lock);
         state = cvmx_debug_get_state();
-        state.handler_cores ^= (1 << core);
+        state.handler_cores ^= (1u << core);
         cvmx_debug_update_state(state);
         cvmx_spinlock_unlock(&cvmx_debug_globals->lock);
     }
@@ -1153,12 +1313,12 @@ static int cvmx_debug_perform_proxy(cvmx_debug_register_t *debug_reg, volatile c
     return 0;
 }
 
-static void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context)
+static void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *context, uint64_t hi, uint64_t lo)
 {
     unsigned i;
-    memcpy((char *) context->regs, __cvmx_debug_save_regs_area, sizeof(context->regs));
-    asm("mflo %0" : "=r"(context->lo));
-    asm("mfhi %0" : "=r"(context->hi));
+    cvmx_debug_memcpy_align ((char *) context->regs, __cvmx_debug_save_regs_area, sizeof(context->regs));
+    context->lo = lo;
+    context->hi = hi;
     CVMX_MF_COP0(context->cop0.index, COP0_INDEX);
     CVMX_MF_COP0(context->cop0.entrylo[0], COP0_ENTRYLO0);
     CVMX_MF_COP0(context->cop0.entrylo[1], COP0_ENTRYLO1);
@@ -1209,10 +1369,9 @@ static void cvmx_debug_save_core_context(volatile cvmx_debug_core_context_t *con
 
 static void cvmx_debug_restore_core_context(volatile cvmx_debug_core_context_t *context)
 {
+    uint64_t hi, lo;
     int i;
-    memcpy(__cvmx_debug_save_regs_area, (char *) context->regs, sizeof(context->regs));
-    asm("mtlo %0" :: "r"(context->lo));
-    asm("mthi %0" :: "r"(context->hi));
+    cvmx_debug_memcpy_align (__cvmx_debug_save_regs_area, (char *) context->regs, sizeof(context->regs));
     /* We don't change the TLB so no need to restore it.  */
     cvmx_write_csr(CVMX_DEBUG_HW_DATA_BREAKPOINT_STATUS, context->hw_dbp.status);
     for (i = 0; i < 4; i++)
@@ -1245,6 +1404,10 @@ static void cvmx_debug_restore_core_context(volatile cvmx_debug_core_context_t *
     CVMX_MT_COP0(context->cop0.perfctrl[1], COP0_PERFCONTROL1);
     CVMX_MT_COP0(context->cop0.depc, COP0_DEPC);
     CVMX_MT_COP0(context->cop0.desave, COP0_DESAVE);
+    lo = context->lo;
+    hi = context->hi;
+    asm("mtlo %0" :: "r"(lo));
+    asm("mthi %0" :: "r"(hi));
 }
 
 static inline void cvmx_debug_print_cause(volatile cvmx_debug_core_context_t *context)
@@ -1273,7 +1436,7 @@ static inline void cvmx_debug_print_cause(volatile cvmx_debug_core_context_t *co
         cvmx_dprintf("Debug Single Step (DSS) exception\n");
 }
 
-void __cvmx_debug_handler_stage3 (void)
+void __cvmx_debug_handler_stage3 (uint64_t lo, uint64_t hi)
 {
     volatile cvmx_debug_core_context_t *context;
     int comms_changed = 0;
@@ -1293,7 +1456,7 @@ void __cvmx_debug_handler_stage3 (void)
     }
 
     context = cvmx_debug_core_context();
-    cvmx_debug_save_core_context(context);
+    cvmx_debug_save_core_context(context, hi, lo);
 
     {
         cvmx_debug_state_t state;
@@ -1370,7 +1533,7 @@ void __cvmx_debug_handler_stage3 (void)
 void cvmx_debug_trigger_exception(void)
 {
   /* Set CVMX_CIU_DINT to enter debug exception handler.  */
-  cvmx_write_csr (CVMX_CIU_DINT, 1 << cvmx_get_core_num ());
+  cvmx_write_csr (CVMX_CIU_DINT, 1u << cvmx_get_core_num ());
   /* Perform an immediate read after every write to an RSL register to force
      the write to complete. It doesn't matter what RSL read we do, so we
      choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
@@ -1387,6 +1550,7 @@ void cvmx_debug_finish(void)
     unsigned coreid = cvmx_get_core_num();
     cvmx_debug_state_t state;
 
+    if (!cvmx_debug_globals) return;
     cvmx_debug_printf ("Debug _exit reached!, core %d, cvmx_debug_globals = %p\n", coreid, cvmx_debug_globals);
 
 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -1396,13 +1560,13 @@ void cvmx_debug_finish(void)
 
     cvmx_spinlock_lock(&cvmx_debug_globals->lock);
     state = cvmx_debug_get_state();
-    state.known_cores ^= (1 << coreid);
-    state.core_finished |= (1<<coreid);
+    state.known_cores ^= (1u << coreid);
+    state.core_finished |= (1u <<coreid);
     cvmx_debug_update_state(state);
 
     /* Tell the user the core has finished. */
     if (state.ever_been_in_debug)
-        cvmx_debug_putpacket("!Core %d finish.", coreid);
+        cvmx_debug_putcorepacket("finished.", coreid);
 
     /* Notify the debugger if all cores have completed the program */
     if ((cvmx_debug_core_mask () & state.core_finished) == cvmx_debug_core_mask ())
@@ -1417,9 +1581,9 @@ void cvmx_debug_finish(void)
            Since we already check that known_cores is non zero, this
            should always find a core */
         unsigned newcore;
-        for (newcore = 0; newcore < CVMX_DEBUG_MAX_CORES; newcore++)
+        for (newcore = 0; newcore < CVMX_MAX_CORES; newcore++)
         {
-           if (state.known_cores & (1<<newcore))
+           if (state.known_cores & (1u<<newcore))
            {
                cvmx_debug_printf("Routing uart interrupts to Core #%u.\n", newcore);
                cvmx_debug_set_focus_core(&state, newcore);

sys/contrib/octeon-sdk/cvmx-debug.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -67,7 +67,7 @@ void cvmx_debug_init(void);
 void cvmx_debug_finish(void);
 void cvmx_debug_trigger_exception(void);
 
-#ifdef __OCTEON_NEWLIB__
+#ifdef CVMX_BUILD_FOR_TOOLCHAIN
 extern int __octeon_debug_booted;
 
 static inline int cvmx_debug_booted(void)
@@ -247,9 +247,6 @@ typedef struct
 
 typedef int cvmx_debug_state_t_should_fit_inside_a_cache_block[sizeof(cvmx_debug_state_t)+sizeof(cvmx_spinlock_t)+4*sizeof(uint64_t) > 128 ? -1 : 1];
 
-/* Total number of cores in Octeon. */
-#define CVMX_DEBUG_MAX_CORES 16
-
 typedef struct cvmx_debug_globals_s
 {
     uint64_t version; /* This is always the first element of this struct */
@@ -260,7 +257,7 @@ typedef struct cvmx_debug_globals_s
     uint32_t state[sizeof(cvmx_debug_state_t)/sizeof(uint32_t)];
     cvmx_spinlock_t lock;
 
-    volatile cvmx_debug_core_context_t contextes[CVMX_DEBUG_MAX_CORES];
+    volatile cvmx_debug_core_context_t contextes[CVMX_MAX_CORES];
 } cvmx_debug_globals_t;
 
 typedef union

sys/contrib/octeon-sdk/cvmx-dfa.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Support library for the CN31XX, CN38XX, and CN58XX hardware DFA engine.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "executive-config.h"
 #ifdef CVMX_ENABLE_DFA_FUNCTIONS

sys/contrib/octeon-sdk/cvmx-dfa.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the CN31XX, CN38XX, and CN58XX hardware DFA engine.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_DFA_H__
@@ -486,7 +486,7 @@ typedef union
     uint64_t u64;
     struct {
 #define CVMX_DFA_STATE_TICKET_BIT_POS 16
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
 	// NOTE:  must clear LSB of base_address_div16 due to ticket overflow
 	uint32_t		base_address_div16;  /**< Current DFA instruction queue chunck base address/16 (clear LSB). */
 	uint8_t			ticket_loops;	     /**< bits [15:8] of total number of tickets requested. */
@@ -503,7 +503,7 @@ typedef union
 #endif
     } s;
     struct {	// a bitfield version of the same thing to extract base address while clearing carry.
-#if __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t		base_address_div32	: 31;	/**< Current DFA instruction queue chunck base address/32. */
 	uint64_t		carry			: 1;	/**< Carry out from total_tickets. */
 	uint64_t		total_tickets		: 16;	/**< Total tickets. */

sys/contrib/octeon-sdk/cvmx-dma-engine.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,13 +49,29 @@
  * Interface to the PCI / PCIe DMA engines. These are only avialable
  * on chips with PCI / PCIe.
  *
- * <hr>$Revision: 50126 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/octeon-model.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
+#include <asm/octeon/cvmx-dma-engine.h>
+#include <asm/octeon/octeon-feature.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
+#else
 #include "executive-config.h"
 #include "cvmx-config.h"
 #include "cvmx.h"
 #include "cvmx-cmd-queue.h"
 #include "cvmx-dma-engine.h"
+#include "cvmx-helper-cfg.h"
+#endif
 
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 
@@ -153,6 +169,7 @@ int cvmx_dma_engine_initialize(void)
     else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
     {
         cvmx_dpi_engx_buf_t dpi_engx_buf;
+        cvmx_dpi_dma_engx_en_t dpi_dma_engx_en;
         cvmx_dpi_dma_control_t dma_control;
         cvmx_dpi_ctl_t dpi_ctl;
 
@@ -172,11 +189,16 @@ int cvmx_dma_engine_initialize(void)
         dma_control.s.pkt_hp = 1;
         dma_control.s.pkt_en = 1;
         dma_control.s.dma_enb = 0x1f;
-        dma_control.s.dwb_denb = 1;
+        dma_control.s.dwb_denb = cvmx_helper_cfg_opt_get(CVMX_HELPER_CFG_OPT_USE_DWB);
         dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
         dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
         dma_control.s.o_mode = 1;
         cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
+        /* When dma_control[pkt_en] = 1, engine 5 is used for packets and is not
+           available for DMA. */
+        dpi_dma_engx_en.u64 = cvmx_read_csr(CVMX_DPI_DMA_ENGX_EN(5));
+        dpi_dma_engx_en.s.qen = 0;
+        cvmx_write_csr(CVMX_DPI_DMA_ENGX_EN(5), dpi_dma_engx_en.u64);
         dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
         dpi_ctl.s.en = 1;
         cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
@@ -197,10 +219,12 @@ int cvmx_dma_engine_initialize(void)
 
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_dma_engine_initialize);
+#endif
 
 /**
- * Shutdown all DMA engines. The engeines must be idle when this
+ * Shutdown all DMA engines. The engines must be idle when this
  * function is called.
  *
  * @return Zero on success, negative on failure
@@ -270,16 +294,18 @@ int cvmx_dma_engine_shutdown(void)
 
     return 0;
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_dma_engine_shutdown);
+#endif
 
 /**
- * Submit a series of DMA comamnd to the DMA engines.
+ * Submit a series of DMA command to the DMA engines.
  *
  * @param engine  Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header  Command header
  * @param num_buffers
  *                The number of data pointers
- * @param buffers Comamnd data pointers
+ * @param buffers Command data pointers
  *
  * @return Zero on success, negative on failure
  */
@@ -519,5 +545,7 @@ int cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header,
     }
     return cvmx_dma_engine_submit(engine, header, words, buffers);
 }
-
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(cvmx_dma_engine_transfer);
+#endif
 #endif

sys/contrib/octeon-sdk/cvmx-dma-engine.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,12 +49,18 @@
  * Interface to the PCI / PCIe DMA engines. These are only avialable
  * on chips with PCI / PCIe.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_DMA_ENGINES_H__
 #define __CVMX_DMA_ENGINES_H__
 
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <asm/octeon/cvmx-dpi-defs.h>
+#else
+#include "cvmx-dpi-defs.h"
+#endif
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
@@ -264,13 +270,13 @@ int cvmx_dma_engine_shutdown(void);
 int cvmx_dma_engine_get_num(void);
 
 /**
- * Submit a series of DMA comamnd to the DMA engines.
+ * Submit a series of DMA command to the DMA engines.
  *
  * @param engine  Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
  * @param header  Command header
  * @param num_buffers
  *                The number of data pointers
- * @param buffers Comamnd data pointers
+ * @param buffers Command data pointers
  *
  * @return Zero on success, negative on failure
  */
@@ -327,6 +333,44 @@ static inline int cvmx_dma_engine_memcpy(int engine, void *dest, void *source, i
                                     cvmx_ptr_to_phys(dest), length);
 }
 
+/**
+ * Simplified interface to the DMA engines to emulate memcpy()
+ * When dici_mode is enabled, send zero byte.
+ *
+ * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1)
+ * @param dest   Pointer to the destination memory. cvmx_ptr_to_phys() will be
+ *               used to turn this into a physical address. It cannot be a local
+ *               or CVMX_SHARED block.
+ * @param source Pointer to the source memory.
+ *               cvmx_ptr_to_phys() will be used to turn this
+ *               into a physical address. It cannot be a local
+ *               or CVMX_SHARED block.
+ * @param length Number of bytes to copy
+ * @param core   core number for zero byte write
+ *
+ * @return Zero on success, negative on failure
+ */
+static inline int cvmx_dma_engine_memcpy_zero_byte(int engine, void *dest, void *source, int length, int core)
+{
+    cvmx_dma_engine_header_t header;
+    header.u64 = 0;
+    header.s.type = CVMX_DMA_ENGINE_TRANSFER_INTERNAL;
+    /* If dici_mode is set, DPI increments the DPI_DMA_PPn_CNT[CNT], where the
+       value of core n is PTR<5:0>-1 when WQP=0 and PTR != 0 && PTR < 64. */
+    if (octeon_has_feature(OCTEON_FEATURE_DICI_MODE))
+    {
+        cvmx_dpi_dma_control_t dma_control;
+        dma_control.u64 = cvmx_read_csr(CVMX_DPI_DMA_CONTROL);
+        if (dma_control.s.dici_mode)
+        {
+           header.s.wqp = 0;           // local memory pointer
+           header.s.addr = core + 1;
+        }
+    }
+    return cvmx_dma_engine_transfer(engine, header, cvmx_ptr_to_phys(source),
+                                    cvmx_ptr_to_phys(dest), length);
+}
+
 #ifdef	__cplusplus
 }
 #endif

sys/contrib/octeon-sdk/cvmx-ebt3000.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the EBT3000 specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-ebt3000.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  *
  * Interface to the EBT3000 specific devices
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-eoi-defs.h

@@ -0,0 +1,689 @@
+/***********************license start***************
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * cvmx-eoi-defs.h
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon eoi.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 69515 $<hr>
+ *
+ */
+#ifndef __CVMX_EOI_DEFS_H__
+#define __CVMX_EOI_DEFS_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_BIST_CTL_STA CVMX_EOI_BIST_CTL_STA_FUNC()
+static inline uint64_t CVMX_EOI_BIST_CTL_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_BIST_CTL_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000118ull);
+}
+#else
+#define CVMX_EOI_BIST_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000118ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_CTL_STA CVMX_EOI_CTL_STA_FUNC()
+static inline uint64_t CVMX_EOI_CTL_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_CTL_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000000ull);
+}
+#else
+#define CVMX_EOI_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000000ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_DEF_STA0 CVMX_EOI_DEF_STA0_FUNC()
+static inline uint64_t CVMX_EOI_DEF_STA0_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_DEF_STA0 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000020ull);
+}
+#else
+#define CVMX_EOI_DEF_STA0 (CVMX_ADD_IO_SEG(0x0001180013000020ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_DEF_STA1 CVMX_EOI_DEF_STA1_FUNC()
+static inline uint64_t CVMX_EOI_DEF_STA1_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_DEF_STA1 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000028ull);
+}
+#else
+#define CVMX_EOI_DEF_STA1 (CVMX_ADD_IO_SEG(0x0001180013000028ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_DEF_STA2 CVMX_EOI_DEF_STA2_FUNC()
+static inline uint64_t CVMX_EOI_DEF_STA2_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_DEF_STA2 not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000030ull);
+}
+#else
+#define CVMX_EOI_DEF_STA2 (CVMX_ADD_IO_SEG(0x0001180013000030ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ECC_CTL CVMX_EOI_ECC_CTL_FUNC()
+static inline uint64_t CVMX_EOI_ECC_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ECC_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000110ull);
+}
+#else
+#define CVMX_EOI_ECC_CTL (CVMX_ADD_IO_SEG(0x0001180013000110ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ENDOR_BISTR_CTL_STA CVMX_EOI_ENDOR_BISTR_CTL_STA_FUNC()
+static inline uint64_t CVMX_EOI_ENDOR_BISTR_CTL_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ENDOR_BISTR_CTL_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000120ull);
+}
+#else
+#define CVMX_EOI_ENDOR_BISTR_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000120ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ENDOR_CLK_CTL CVMX_EOI_ENDOR_CLK_CTL_FUNC()
+static inline uint64_t CVMX_EOI_ENDOR_CLK_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ENDOR_CLK_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000038ull);
+}
+#else
+#define CVMX_EOI_ENDOR_CLK_CTL (CVMX_ADD_IO_SEG(0x0001180013000038ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_ENDOR_CTL CVMX_EOI_ENDOR_CTL_FUNC()
+static inline uint64_t CVMX_EOI_ENDOR_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_ENDOR_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000100ull);
+}
+#else
+#define CVMX_EOI_ENDOR_CTL (CVMX_ADD_IO_SEG(0x0001180013000100ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_INT_ENA CVMX_EOI_INT_ENA_FUNC()
+static inline uint64_t CVMX_EOI_INT_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_INT_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000010ull);
+}
+#else
+#define CVMX_EOI_INT_ENA (CVMX_ADD_IO_SEG(0x0001180013000010ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_INT_STA CVMX_EOI_INT_STA_FUNC()
+static inline uint64_t CVMX_EOI_INT_STA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_INT_STA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000008ull);
+}
+#else
+#define CVMX_EOI_INT_STA (CVMX_ADD_IO_SEG(0x0001180013000008ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_IO_DRV CVMX_EOI_IO_DRV_FUNC()
+static inline uint64_t CVMX_EOI_IO_DRV_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_IO_DRV not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000018ull);
+}
+#else
+#define CVMX_EOI_IO_DRV (CVMX_ADD_IO_SEG(0x0001180013000018ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_EOI_THROTTLE_CTL CVMX_EOI_THROTTLE_CTL_FUNC()
+static inline uint64_t CVMX_EOI_THROTTLE_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_EOI_THROTTLE_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x0001180013000108ull);
+}
+#else
+#define CVMX_EOI_THROTTLE_CTL (CVMX_ADD_IO_SEG(0x0001180013000108ull))
+#endif
+
+/**
+ * cvmx_eoi_bist_ctl_sta
+ *
+ * EOI_BIST_CTL_STA =  EOI BIST Status Register
+ *
+ * Description:
+ *   This register control EOI memory BIST and contains the bist result of EOI memories.
+ */
+union cvmx_eoi_bist_ctl_sta {
+	uint64_t u64;
+	struct cvmx_eoi_bist_ctl_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_18_63               : 46;
+	uint64_t clear_bist                   : 1;  /**< Clear BIST on the HCLK memories */
+	uint64_t start_bist                   : 1;  /**< Starts BIST on the HCLK memories during 0-to-1
+                                                         transition. */
+	uint64_t reserved_3_15                : 13;
+	uint64_t stdf                         : 1;  /**< STDF Bist Status. */
+	uint64_t ppaf                         : 1;  /**< PPAF Bist Status. */
+	uint64_t lddf                         : 1;  /**< LDDF Bist Status. */
+#else
+	uint64_t lddf                         : 1;
+	uint64_t ppaf                         : 1;
+	uint64_t stdf                         : 1;
+	uint64_t reserved_3_15                : 13;
+	uint64_t start_bist                   : 1;
+	uint64_t clear_bist                   : 1;
+	uint64_t reserved_18_63               : 46;
+#endif
+	} s;
+	struct cvmx_eoi_bist_ctl_sta_s        cnf71xx;
+};
+typedef union cvmx_eoi_bist_ctl_sta cvmx_eoi_bist_ctl_sta_t;
+
+/**
+ * cvmx_eoi_ctl_sta
+ *
+ * EOI_CTL_STA = EOI Configure Control Reigster
+ * This register configures EOI.
+ */
+union cvmx_eoi_ctl_sta {
+	uint64_t u64;
+	struct cvmx_eoi_ctl_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_13_63               : 51;
+	uint64_t ppaf_wm                      : 5;  /**< Number of entries when PP Access FIFO will assert
+                                                         full (back pressure) */
+	uint64_t reserved_5_7                 : 3;
+	uint64_t busy                         : 1;  /**< 1: EOI is busy; 0: EOI is idle */
+	uint64_t rwam                         : 2;  /**< Rread Write Aribitration Mode:
+                                                         - 10: Reads  have higher priority
+                                                         - 01: Writes have higher priority
+                                                         00,11: Round-Robin between Reads and Writes */
+	uint64_t ena                          : 1;  /**< When reset, all the inbound DMA accesses will be
+                                                         drop and all the outbound read response and write
+                                                         commits will be drop. It must be set to 1'b1 for
+                                                         normal access. */
+	uint64_t reset                        : 1;  /**< EOI block Software Reset. */
+#else
+	uint64_t reset                        : 1;
+	uint64_t ena                          : 1;
+	uint64_t rwam                         : 2;
+	uint64_t busy                         : 1;
+	uint64_t reserved_5_7                 : 3;
+	uint64_t ppaf_wm                      : 5;
+	uint64_t reserved_13_63               : 51;
+#endif
+	} s;
+	struct cvmx_eoi_ctl_sta_s             cnf71xx;
+};
+typedef union cvmx_eoi_ctl_sta cvmx_eoi_ctl_sta_t;
+
+/**
+ * cvmx_eoi_def_sta0
+ *
+ * Note: Working settings tabulated for each corner.
+ * ================================
+ * Corner pctl    nctl
+ * ===============================
+ *     1   26      22
+ *     2   30      28
+ *     3   32      31
+ *     4   23      19
+ *     5   27      24
+ *     6   29      27
+ *     7   21      17
+ *     8   25      22
+ *     9   27      24
+ *    10   29      24
+ *    11   34      31
+ *    12   36      35
+ *    13   26      21
+ *    14   31      27
+ *    15   33      30
+ *    16   23      18
+ *    17   28      24
+ *    18   30      27
+ *    19   21      17
+ *    20   27      25
+ *    21   29      28
+ *    22   21      17
+ *    23   25      22
+ *    24   27      25
+ *    25   19      15
+ *    26   23      20
+ *    27   25      22
+ *    28   24      24
+ *    29   28      31
+ *    30   30      35
+ *    31   21      21
+ *    32   25      27
+ *    33   27      30
+ *    34   19      18
+ *    35   23      24
+ *    36   25      27
+ *    37   29      19
+ *    38   33      25
+ *    39   36      28
+ *    40   25      17
+ *    41   30      22
+ *    42   32      25
+ *    43   23      15
+ *    44   27      20
+ *    45   29      22
+ * ===============================
+ *
+ *                   EOI_DEF_STA0 = EOI Defect Status Register 0
+ *
+ *  Register to hold repairout 0/1/2
+ */
+union cvmx_eoi_def_sta0 {
+	uint64_t u64;
+	struct cvmx_eoi_def_sta0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t rout2                        : 18; /**< Repairout2 */
+	uint64_t rout1                        : 18; /**< Repairout1 */
+	uint64_t rout0                        : 18; /**< Repairout0 */
+#else
+	uint64_t rout0                        : 18;
+	uint64_t rout1                        : 18;
+	uint64_t rout2                        : 18;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_eoi_def_sta0_s            cnf71xx;
+};
+typedef union cvmx_eoi_def_sta0 cvmx_eoi_def_sta0_t;
+
+/**
+ * cvmx_eoi_def_sta1
+ *
+ * EOI_DEF_STA1 = EOI Defect Status Register 1
+ *
+ * Register to hold repairout 3/4/5
+ */
+union cvmx_eoi_def_sta1 {
+	uint64_t u64;
+	struct cvmx_eoi_def_sta1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_54_63               : 10;
+	uint64_t rout5                        : 18; /**< Repairout5 */
+	uint64_t rout4                        : 18; /**< Repairout4 */
+	uint64_t rout3                        : 18; /**< Repairout3 */
+#else
+	uint64_t rout3                        : 18;
+	uint64_t rout4                        : 18;
+	uint64_t rout5                        : 18;
+	uint64_t reserved_54_63               : 10;
+#endif
+	} s;
+	struct cvmx_eoi_def_sta1_s            cnf71xx;
+};
+typedef union cvmx_eoi_def_sta1 cvmx_eoi_def_sta1_t;
+
+/**
+ * cvmx_eoi_def_sta2
+ *
+ * EOI_DEF_STA2 = EOI Defect Status Register 2
+ *
+ * Register to hold repairout 6 and toomanydefects.
+ */
+union cvmx_eoi_def_sta2 {
+	uint64_t u64;
+	struct cvmx_eoi_def_sta2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_25_63               : 39;
+	uint64_t toomany                      : 1;  /**< Toomanydefects */
+	uint64_t reserved_18_23               : 6;
+	uint64_t rout6                        : 18; /**< Repairout6 */
+#else
+	uint64_t rout6                        : 18;
+	uint64_t reserved_18_23               : 6;
+	uint64_t toomany                      : 1;
+	uint64_t reserved_25_63               : 39;
+#endif
+	} s;
+	struct cvmx_eoi_def_sta2_s            cnf71xx;
+};
+typedef union cvmx_eoi_def_sta2 cvmx_eoi_def_sta2_t;
+
+/**
+ * cvmx_eoi_ecc_ctl
+ *
+ * EOI_ECC_CTL =  EOI ECC Control Register
+ *
+ * Description:
+ *   This register enables ECC for each individual internal memory that requires ECC. For debug purpose, it can also
+ *   control 1 or 2 bits be flipped in the ECC data.
+ */
+union cvmx_eoi_ecc_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_ecc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_3_63                : 61;
+	uint64_t rben                         : 1;  /**< 1: ECC Enable for read buffer
+                                                         - 0: ECC Enable for instruction buffer */
+	uint64_t rbsf                         : 2;  /**< read buffer ecc syndrome flip
+                                                         2'b00       : No Error Generation
+                                                         2'b10, 2'b01: Flip 1 bit
+                                                         2'b11       : Flip 2 bits */
+#else
+	uint64_t rbsf                         : 2;
+	uint64_t rben                         : 1;
+	uint64_t reserved_3_63                : 61;
+#endif
+	} s;
+	struct cvmx_eoi_ecc_ctl_s             cnf71xx;
+};
+typedef union cvmx_eoi_ecc_ctl cvmx_eoi_ecc_ctl_t;
+
+/**
+ * cvmx_eoi_endor_bistr_ctl_sta
+ *
+ * EOI_ENDOR_BISTR_CTL_STA =  EOI BIST/BISR Control Status Register
+ *
+ * Description:
+ *   This register the bist result of EOI memories.
+ */
+union cvmx_eoi_endor_bistr_ctl_sta {
+	uint64_t u64;
+	struct cvmx_eoi_endor_bistr_ctl_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t bisr_done                    : 1;  /**< Endor DSP Memroy Bisr Done Status: 1 - done;
+                                                         0 - Not done. */
+	uint64_t failed                       : 1;  /**< Bist/Bisr Status: 1 - failed; 0 - Not failed. */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t bisr_hr                      : 1;  /**< BISR Hardrepair */
+	uint64_t bisr_dir                     : 1;  /**< BISR Direction: 0 = input repair packets;
+                                                         1 = output defect packets. */
+	uint64_t start_bist                   : 1;  /**< Start Bist */
+#else
+	uint64_t start_bist                   : 1;
+	uint64_t bisr_dir                     : 1;
+	uint64_t bisr_hr                      : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t failed                       : 1;
+	uint64_t bisr_done                    : 1;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} s;
+	struct cvmx_eoi_endor_bistr_ctl_sta_s cnf71xx;
+};
+typedef union cvmx_eoi_endor_bistr_ctl_sta cvmx_eoi_endor_bistr_ctl_sta_t;
+
+/**
+ * cvmx_eoi_endor_clk_ctl
+ *
+ * EOI_ENDOR_CLK_CTL = EOI Endor Clock Control
+ *
+ * Register control the generation of Endor DSP and HAB clocks.
+ */
+union cvmx_eoi_endor_clk_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_endor_clk_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_28_63               : 36;
+	uint64_t habclk_sel                   : 1;  /**< HAB CLK select
+                                                         0x0: HAB CLK select from PHY_PLL output from HAB PS
+                                                         0x1: HAB CLK select from DDR_PLL output from HAB PS */
+	uint64_t reserved_26_26               : 1;
+	uint64_t dsp_div_reset                : 1;  /**< DSP postscalar divider reset */
+	uint64_t dsp_ps_en                    : 3;  /**< DSP postscalar divide ratio
+                                                         Determines the DSP CK speed.
+                                                         0x0 : Divide DSP PLL output by 1
+                                                         0x1 : Divide DSP PLL output by 2
+                                                         0x2 : Divide DSP PLL output by 3
+                                                         0x3 : Divide DSP PLL output by 4
+                                                         0x4 : Divide DSP PLL output by 6
+                                                         0x5 : Divide DSP PLL output by 8
+                                                         0x6 : Divide DSP PLL output by 12
+                                                         0x7 : Divide DSP PLL output by 12
+                                                         DSP_PS_EN is not used when DSP_DIV_RESET = 1 */
+	uint64_t hab_div_reset                : 1;  /**< HAB postscalar divider reset */
+	uint64_t hab_ps_en                    : 3;  /**< HAB postscalar divide ratio
+                                                         Determines the LMC CK speed.
+                                                         0x0 : Divide HAB PLL output by 1
+                                                         0x1 : Divide HAB PLL output by 2
+                                                         0x2 : Divide HAB PLL output by 3
+                                                         0x3 : Divide HAB PLL output by 4
+                                                         0x4 : Divide HAB PLL output by 6
+                                                         0x5 : Divide HAB PLL output by 8
+                                                         0x6 : Divide HAB PLL output by 12
+                                                         0x7 : Divide HAB PLL output by 12
+                                                         HAB_PS_EN is not used when HAB_DIV_RESET = 1 */
+	uint64_t diffamp                      : 4;  /**< PLL diffamp input transconductance */
+	uint64_t cps                          : 3;  /**< PLL charge-pump current */
+	uint64_t cpb                          : 3;  /**< PLL charge-pump current */
+	uint64_t reset_n                      : 1;  /**< PLL reset */
+	uint64_t clkf                         : 7;  /**< Multiply reference by CLKF
+                                                         32 <= CLKF <= 64
+                                                         PHY PLL frequency = 50 * CLKF
+                                                         min = 1.6 GHz, max = 3.2 GHz */
+#else
+	uint64_t clkf                         : 7;
+	uint64_t reset_n                      : 1;
+	uint64_t cpb                          : 3;
+	uint64_t cps                          : 3;
+	uint64_t diffamp                      : 4;
+	uint64_t hab_ps_en                    : 3;
+	uint64_t hab_div_reset                : 1;
+	uint64_t dsp_ps_en                    : 3;
+	uint64_t dsp_div_reset                : 1;
+	uint64_t reserved_26_26               : 1;
+	uint64_t habclk_sel                   : 1;
+	uint64_t reserved_28_63               : 36;
+#endif
+	} s;
+	struct cvmx_eoi_endor_clk_ctl_s       cnf71xx;
+};
+typedef union cvmx_eoi_endor_clk_ctl cvmx_eoi_endor_clk_ctl_t;
+
+/**
+ * cvmx_eoi_endor_ctl
+ *
+ * EOI_ENDOR_CTL_STA = Endor Control Reigster
+ * This register controls Endor phy reset and access.
+ */
+union cvmx_eoi_endor_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_endor_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_12_63               : 52;
+	uint64_t r_emod                       : 2;  /**< Endian format for data read from the L2C.
+                                                         IN:    A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t w_emod                       : 2;  /**< Endian format for data written the L2C.
+                                                         IN:    A-B-C-D-E-F-G-H
+                                                         OUT0:  A-B-C-D-E-F-G-H
+                                                         OUT1:  H-G-F-E-D-C-B-A
+                                                         OUT2:  D-C-B-A-H-G-F-E
+                                                         OUT3:  E-F-G-H-A-B-C-D */
+	uint64_t inv_rsl_ra2                  : 1;  /**< Invert RSL CSR read  address bit 2. */
+	uint64_t inv_rsl_wa2                  : 1;  /**< Invert RSL CSR write address bit 2. */
+	uint64_t inv_pp_ra2                   : 1;  /**< Invert PP CSR read  address bit 2. */
+	uint64_t inv_pp_wa2                   : 1;  /**< Invert PP CSR write address bit 2. */
+	uint64_t reserved_1_3                 : 3;
+	uint64_t reset                        : 1;  /**< Endor block software reset. After hardware reset,
+                                                         this bit is set to 1'b1 which put Endor into reset
+                                                         state. Software must clear this bit to use Endor. */
+#else
+	uint64_t reset                        : 1;
+	uint64_t reserved_1_3                 : 3;
+	uint64_t inv_pp_wa2                   : 1;
+	uint64_t inv_pp_ra2                   : 1;
+	uint64_t inv_rsl_wa2                  : 1;
+	uint64_t inv_rsl_ra2                  : 1;
+	uint64_t w_emod                       : 2;
+	uint64_t r_emod                       : 2;
+	uint64_t reserved_12_63               : 52;
+#endif
+	} s;
+	struct cvmx_eoi_endor_ctl_s           cnf71xx;
+};
+typedef union cvmx_eoi_endor_ctl cvmx_eoi_endor_ctl_t;
+
+/**
+ * cvmx_eoi_int_ena
+ *
+ * EOI_INT_ENA = EOI Interrupt Enable Register
+ *
+ * Register to enable individual interrupt source in corresponding to EOI_INT_STA
+ */
+union cvmx_eoi_int_ena {
+	uint64_t u64;
+	struct cvmx_eoi_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t rb_dbe                       : 1;  /**< Read Buffer ECC DBE */
+	uint64_t rb_sbe                       : 1;  /**< Read Buffer ECC SBE */
+#else
+	uint64_t rb_sbe                       : 1;
+	uint64_t rb_dbe                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_eoi_int_ena_s             cnf71xx;
+};
+typedef union cvmx_eoi_int_ena cvmx_eoi_int_ena_t;
+
+/**
+ * cvmx_eoi_int_sta
+ *
+ * EOI_INT_STA = EOI Interrupt Status Register
+ *
+ * Summary of different bits of RSL interrupt status.
+ */
+union cvmx_eoi_int_sta {
+	uint64_t u64;
+	struct cvmx_eoi_int_sta_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_2_63                : 62;
+	uint64_t rb_dbe                       : 1;  /**< Read Buffer ECC DBE */
+	uint64_t rb_sbe                       : 1;  /**< Read Buffer ECC SBE */
+#else
+	uint64_t rb_sbe                       : 1;
+	uint64_t rb_dbe                       : 1;
+	uint64_t reserved_2_63                : 62;
+#endif
+	} s;
+	struct cvmx_eoi_int_sta_s             cnf71xx;
+};
+typedef union cvmx_eoi_int_sta cvmx_eoi_int_sta_t;
+
+/**
+ * cvmx_eoi_io_drv
+ *
+ * EOI_IO_DRV = EOI Endor IO Drive Control
+ *
+ * Register to control Endor Phy IOs
+ */
+union cvmx_eoi_io_drv {
+	uint64_t u64;
+	struct cvmx_eoi_io_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_24_63               : 40;
+	uint64_t rfif_p                       : 6;  /**< RFIF output driver P-Mos control */
+	uint64_t rfif_n                       : 6;  /**< RFIF output driver N-Mos control */
+	uint64_t gpo_p                        : 6;  /**< GPO  output driver P-Mos control */
+	uint64_t gpo_n                        : 6;  /**< GPO  output driver N-Mos control */
+#else
+	uint64_t gpo_n                        : 6;
+	uint64_t gpo_p                        : 6;
+	uint64_t rfif_n                       : 6;
+	uint64_t rfif_p                       : 6;
+	uint64_t reserved_24_63               : 40;
+#endif
+	} s;
+	struct cvmx_eoi_io_drv_s              cnf71xx;
+};
+typedef union cvmx_eoi_io_drv cvmx_eoi_io_drv_t;
+
+/**
+ * cvmx_eoi_throttle_ctl
+ *
+ * EOI_THROTTLE_CTL = EOI THROTTLE Control Reigster
+ * This register controls number of outstanding EOI loads to L2C . It is in phy_clock domain.
+ */
+union cvmx_eoi_throttle_ctl {
+	uint64_t u64;
+	struct cvmx_eoi_throttle_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_21_63               : 43;
+	uint64_t std                          : 5;  /**< Number of outstanding store data accepted by EOI on
+                                                         AXI before backpressure ADMA. The value must be from
+                                                         from 16 to 31 inclusively. */
+	uint64_t reserved_10_15               : 6;
+	uint64_t stc                          : 2;  /**< Number of outstanding L2C store command accepted by
+                                                         EOI on AXI before backpressure ADMA. The value must be
+                                                         from 1 to 3 inclusively. */
+	uint64_t reserved_4_7                 : 4;
+	uint64_t ldc                          : 4;  /**< Number of outstanding L2C loads. The value must be
+                                                         from 1 to 8 inclusively. */
+#else
+	uint64_t ldc                          : 4;
+	uint64_t reserved_4_7                 : 4;
+	uint64_t stc                          : 2;
+	uint64_t reserved_10_15               : 6;
+	uint64_t std                          : 5;
+	uint64_t reserved_21_63               : 43;
+#endif
+	} s;
+	struct cvmx_eoi_throttle_ctl_s        cnf71xx;
+};
+typedef union cvmx_eoi_throttle_ctl cvmx_eoi_throttle_ctl_t;
+
+#endif

sys/contrib/octeon-sdk/cvmx-error-custom.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -58,6 +58,7 @@
 #include <asm/octeon/cvmx-gmxx-defs.h>
 #include <asm/octeon/cvmx-lmcx-defs.h>
 #include <asm/octeon/cvmx-pemx-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
 #define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
 #else
 #include "cvmx.h"
@@ -82,6 +83,21 @@ static int __cvmx_error_handle_gmxx_rxx_int_reg(const struct cvmx_error_info *in
 {
 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
     int ipd_port = info->group_index;
+    switch(ipd_port)
+    {
+        case 0x800:
+            ipd_port = 0x840;
+            break;
+        case 0xa00:
+            ipd_port = 0xa40;
+            break;
+        case 0xb00:
+            ipd_port = 0xb40;
+            break;
+        case 0xc00:
+            ipd_port = 0xc40;
+            break;
+    }
     cvmx_helper_link_autoconf(ipd_port);
 #endif
     cvmx_write_csr(info->status_addr, info->status_mask);
@@ -140,6 +156,136 @@ static int __cvmx_error_handle_npei_int_sum_c1_ldwn(const struct cvmx_error_info
     return 1;
 }
 
+#define DECODE_FAILING_ADDRESS
+//#define DECODE_FAILING_BIT
+
+#ifdef DECODE_FAILING_BIT
+#define _Db(x) (x)              /* Data Bit */
+#define _Ec(x) (0x100+x)        /* ECC Bit */
+#define _Ad(x) (0x200+x)        /* Address Bit */
+#define _Bu(x) (0x400+x)        /* Burst */
+#define _Un()  (-1)             /* Unused */
+/* Use ECC Code as index to lookup corrected bit */
+const static short lmc_syndrome_bits[256] = {
+    /*        __ 0 __  __ 1 __  __ 2 __  __ 3 __  __ 4 __  __ 5 __  __ 6 __  __ 7 __  __ 8 __  __ 9 __  __ A __  __ B __  __ C __  __ D __  __ E __  __ F __ */
+    /* 00: */ _Un(  ), _Ec( 0), _Ec( 1), _Un(  ), _Ec( 2), _Un(  ), _Un(  ), _Un(  ), _Ec( 3), _Un(  ), _Un(  ), _Db(17), _Un(  ), _Un(  ), _Db(16), _Un(  ),    
+    /* 10: */ _Ec( 4), _Un(  ), _Un(  ), _Db(18), _Un(  ), _Db(19), _Db(20), _Un(  ), _Un(  ), _Db(21), _Db(22), _Un(  ), _Db(23), _Un(  ), _Un(  ), _Un(  ),    
+    /* 20: */ _Ec( 5), _Un(  ), _Un(  ), _Db( 8), _Un(  ), _Db( 9), _Db(10), _Un(  ), _Un(  ), _Db(11), _Db(12), _Un(  ), _Db(13), _Un(  ), _Un(  ), _Un(  ),    
+    /* 30: */ _Un(  ), _Db(14), _Un(  ), _Un(  ), _Db(15), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Ad(34), _Un(  ),    
+    /* 40: */ _Ec( 6), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Ad( 7), _Ad( 8), _Un(  ), _Un(  ), _Ad( 9), _Db(33), _Un(  ), _Ad(10), _Un(  ), _Un(  ), _Db(32),    
+    /* 50: */ _Un(  ), _Ad(11), _Db(34), _Un(  ), _Db(35), _Un(  ), _Un(  ), _Db(36), _Db(37), _Un(  ), _Un(  ), _Db(38), _Un(  ), _Db(39), _Ad(12), _Un(  ),    
+    /* 60: */ _Un(  ), _Ad(13), _Db(56), _Un(  ), _Db(57), _Un(  ), _Un(  ), _Db(58), _Db(59), _Un(  ), _Un(  ), _Db(60), _Un(  ), _Db(61), _Ad(14), _Un(  ),    
+    /* 70: */ _Db(62), _Un(  ), _Un(  ), _Ad(15), _Un(  ), _Db(63), _Ad(16), _Un(  ), _Un(  ), _Ad(17), _Ad(18), _Un(  ), _Ad(19), _Un(  ), _Ad(20), _Un(  ),    
+    /* 80: */ _Ec( 7), _Un(  ), _Un(  ), _Ad(21), _Un(  ), _Ad(22), _Ad(23), _Un(  ), _Un(  ), _Ad(24), _Db(49), _Un(  ), _Ad(25), _Un(  ), _Un(  ), _Db(48),    
+    /* 90: */ _Un(  ), _Ad(26), _Db(50), _Un(  ), _Db(51), _Un(  ), _Un(  ), _Db(52), _Db(53), _Un(  ), _Un(  ), _Db(54), _Un(  ), _Db(55), _Ad(27), _Un(  ),    
+    /* A0: */ _Un(  ), _Ad(28), _Db(40), _Un(  ), _Db(41), _Un(  ), _Un(  ), _Db(42), _Db(43), _Un(  ), _Un(  ), _Db(44), _Un(  ), _Db(45), _Ad(29), _Un(  ),    
+    /* B0: */ _Db(46), _Un(  ), _Un(  ), _Ad(30), _Un(  ), _Db(47), _Ad(31), _Un(  ), _Un(  ), _Ad(32), _Ad(33), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ),    
+    /* C0: */ _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Db( 1), _Un(  ), _Un(  ), _Db( 0), _Un(  ),    
+    /* D0: */ _Un(  ), _Un(  ), _Un(  ), _Db( 2), _Un(  ), _Db( 3), _Db( 4), _Un(  ), _Un(  ), _Db( 5), _Db( 6), _Un(  ), _Db( 7), _Un(  ), _Un(  ), _Un(  ),    
+    /* E0: */ _Un(  ), _Un(  ), _Un(  ), _Db(24), _Un(  ), _Db(25), _Db(26), _Un(  ), _Un(  ), _Db(27), _Db(28), _Un(  ), _Db(29), _Un(  ), _Un(  ), _Un(  ),    
+    /* F0: */ _Un(  ), _Db(30), _Un(  ), _Un(  ), _Db(31), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  ), _Un(  )
+};
+#endif
+
+/**
+ * @INTERNAL
+ * This error bit handler clears the status and prints failure infomation.
+ *
+ * @param info   Error register to check
+ *
+ * @return
+ */
+static int __cvmx_cn6xxx_lmc_ecc_error_display(const cvmx_error_info_t *info)
+{
+#ifdef DECODE_FAILING_ADDRESS
+    cvmx_lmcx_config_t lmc_config;
+    uint64_t fadr_physical, fadr_data;
+#endif
+
+    int ddr_controller = info->group_index;
+    cvmx_lmcx_int_t lmc_int;
+    cvmx_lmcx_fadr_t fadr;
+    cvmx_lmcx_ecc_synd_t ecc_synd;
+    int sec_err;
+    int ded_err;
+    int syndrome = -1;
+    int phase;
+
+    lmc_int.u64 = cvmx_read_csr(CVMX_LMCX_INT(ddr_controller));
+    fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(ddr_controller));
+    ecc_synd.u64 = cvmx_read_csr(CVMX_LMCX_ECC_SYND(ddr_controller));
+    /* This assumes that all bits in the status register are RO or R/W1C */
+    cvmx_write_csr(info->status_addr, info->status_mask);
+
+#ifdef DECODE_FAILING_ADDRESS
+    lmc_config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(ddr_controller));
+#endif
+
+    sec_err = lmc_int.s.sec_err;
+    ded_err = lmc_int.s.ded_err;
+
+    phase = ded_err ? ded_err : sec_err; /* Double bit errors take precedence. */
+
+    switch (phase) {
+    case 1:
+        syndrome = ecc_synd.cn63xx.mrdsyn0;
+        break;
+    case 2:
+        syndrome = ecc_synd.cn63xx.mrdsyn1;
+        break;
+    case 4:
+        syndrome = ecc_synd.cn63xx.mrdsyn2;
+        break;
+    case 8:
+        syndrome = ecc_synd.cn63xx.mrdsyn3;
+        break;
+    }
+
+#ifdef DECODE_FAILING_ADDRESS
+    fadr_physical  = (uint64_t)fadr.cn63xx.fdimm      << (lmc_config.s.pbank_lsb + 28);
+    fadr_physical |= (uint64_t)fadr.cn63xx.frow       << (lmc_config.s.row_lsb + 14);
+    fadr_physical |= (uint64_t)fadr.cn63xx.fbank      << 7;
+    fadr_physical |= (uint64_t)(fadr.cn63xx.fcol&0xf) << 3;
+    fadr_physical |= (uint64_t)(fadr.cn63xx.fcol>>4)  << 10;
+
+    fadr_data = *(uint64_t*)cvmx_phys_to_ptr(fadr_physical);
+#endif
+
+    PRINT_ERROR("LMC%d ECC: sec_err:%d ded_err:%d\n"
+                "LMC%d ECC:\tFailing dimm:   %u\n"
+                "LMC%d ECC:\tFailing rank:   %u\n"
+                "LMC%d ECC:\tFailing bank:   %u\n"
+                "LMC%d ECC:\tFailing row:    0x%x\n"
+                "LMC%d ECC:\tFailing column: 0x%x\n"
+                "LMC%d ECC:\tsyndrome: 0x%x"
+#ifdef DECODE_FAILING_BIT
+                ", bit: %d"
+#endif
+                "\n"
+#ifdef DECODE_FAILING_ADDRESS
+                "Failing  Address: 0x%016llx, Data: 0x%016llx\n"
+#endif
+                ,               /* Comma */
+                ddr_controller, sec_err, ded_err,
+                ddr_controller, fadr.cn63xx.fdimm,
+                ddr_controller, fadr.cn63xx.fbunk,
+                ddr_controller, fadr.cn63xx.fbank,
+                ddr_controller, fadr.cn63xx.frow,
+                ddr_controller, fadr.cn63xx.fcol,
+                ddr_controller, syndrome
+#ifdef DECODE_FAILING_BIT
+                ,               /* Comma */
+                lmc_syndrome_bits[syndrome]
+#endif
+#ifdef DECODE_FAILING_ADDRESS
+                ,               /* Comma */
+                (unsigned long long) fadr_physical, (unsigned long long) fadr_data
+#endif
+                );
+
+    return 1;
+}
+
 /**
  * @INTERNAL
  * Some errors require more complicated error handing functions than the
@@ -150,25 +296,60 @@ static int __cvmx_error_handle_npei_int_sum_c1_ldwn(const struct cvmx_error_info
  */
 int __cvmx_error_custom_initialize(void)
 {
-    if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
     {
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,0), 1ull<<21 /* rem_fault */,
+        int lmc;
+        for (lmc = 0; lmc < CVMX_L2C_TADS; lmc++)
+        {
+            if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+            {
+                cvmx_lmcx_dll_ctl2_t ctl;
+                ctl.u64 = cvmx_read_csr(CVMX_LMCX_DLL_CTL2(lmc));
+                if (ctl.s.intf_en == 0)
+                    continue;
+            }
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                    CVMX_LMCX_INT(lmc), 0xfull<<1 /* sec_err */,
+                    __cvmx_cn6xxx_lmc_ecc_error_display, 0, NULL, NULL);
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                    CVMX_LMCX_INT(lmc), 0xfull<<5 /* ded_err */,
+                    __cvmx_cn6xxx_lmc_ecc_error_display, 0, NULL, NULL);
+            if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+	    {
+	        int i;
+
+	        for (i = 0; i < 6; i++)
+                    cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_L2C_TADX_INT(lmc), (1ull << i),
+                            __cvmx_error_handle_63XX_l2_ecc, 0, NULL, NULL);
+            }
+	}
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX)
+        || OCTEON_IS_MODEL(OCTEON_CN56XX)
+        || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+        || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+    {
+        int i;
+
+        /* Install special handler for all the interfaces, these are
+           specific to XAUI interface */
+        for (i = 0; i < CVMX_HELPER_MAX_GMX; i++)
+        {
+            if ((OCTEON_IS_MODEL(OCTEON_CN63XX) 
+                 || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                 || OCTEON_IS_MODEL(OCTEON_CNF71XX))
+                && i == 1)
+                continue;
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,i), 1ull<<21 /* rem_fault */,
                             __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,0), 1ull<<20 /* loc_fault */,
+            cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
+                            CVMX_GMXX_RXX_INT_REG(0,i), 1ull<<20 /* loc_fault */,
                             __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
+        }
     }
     if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-    {
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,1), 1ull<<21 /* rem_fault */,
-                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
-        cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
-                            CVMX_GMXX_RXX_INT_REG(0,1), 1ull<<20 /* loc_fault */,
-                            __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
-    }
-    if (octeon_has_feature(OCTEON_FEATURE_NPEI))
     {
         cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
                             CVMX_PEXP_NPEI_INT_SUM, 1ull<<59 /* c0_ldwn */,
@@ -191,6 +372,14 @@ int __cvmx_error_custom_initialize(void)
         cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(1),
             1ull<<13);
     }
+    /* According to the workaround for errata SRIO-15282, clearing
+       SRIOx_INT_ENABLE[MAC_BUF]. */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) && OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
+    {
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_SRIOX_INT_ENABLE(0), 1ull<<22);
+        cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_SRIOX_INT_ENABLE(1), 1ull<<22);
+    }
+
     return 0;
 }
 
@@ -622,3 +811,79 @@ int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info)
 }
 
 
+/**
+ * @INTERNAL
+ *
+ * @param info
+ *
+ * @return
+ */
+int __cvmx_error_handle_63XX_l2_ecc(const struct cvmx_error_info *info)
+{
+    cvmx_l2c_err_tdtx_t l2c_err_tdt;
+    cvmx_l2c_err_ttgx_t l2c_err_ttg;
+    cvmx_l2c_err_vbfx_t l2c_err_vbf;
+    cvmx_l2c_tadx_int_t tadx_int;
+    tadx_int.u64 = cvmx_read_csr(CVMX_L2C_TADX_INT(0));
+    l2c_err_tdt.u64 = cvmx_read_csr(CVMX_L2C_ERR_TDTX(0));
+    l2c_err_ttg.u64 = cvmx_read_csr(CVMX_L2C_ERR_TTGX(0));
+    l2c_err_vbf.u64 = cvmx_read_csr(CVMX_L2C_ERR_VBFX(0));
+    cvmx_write_csr(CVMX_L2C_TADX_INT(0), tadx_int.u64);
+
+    if (tadx_int.cn63xx.l2ddbe ||  tadx_int.cn63xx.l2dsbe)
+    {
+	/* L2 Data error */
+
+
+	if (tadx_int.cn63xx.l2dsbe)
+        {
+            /* l2c_err_tdt.cn63xx.wayidx formated same as CACHE instruction arg */
+            CVMX_CACHE_WBIL2I((l2c_err_tdt.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+            PRINT_ERROR("L2C_TADX_INT(0)[L2DSBE]: Data Single-Bit Error\n");
+        }
+        if (tadx_int.cn63xx.l2ddbe)
+        {
+            /* TODO - fatal error, for now, flush so error cleared..... */
+            CVMX_CACHE_WBIL2I((l2c_err_tdt.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+	    PRINT_ERROR("L2C_TADX_INT(0)[L2DDBE]: Data Double-Bit Error\n");
+        }
+	PRINT_ERROR("CVMX_L2C_ERR_TDT: 0x%llx\n", (unsigned long long)l2c_err_tdt.u64);
+    }
+    if (tadx_int.cn63xx.tagdbe || tadx_int.cn63xx.tagsbe)
+    {
+	/* L2 Tag error */
+	if (tadx_int.cn63xx.tagsbe)
+        {
+            CVMX_CACHE_WBIL2I((l2c_err_ttg.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+	    PRINT_ERROR("L2C_TADX_INT(0)[TAGSBE]: Tag Single-Bit Error\n");
+        }
+	if (tadx_int.cn63xx.tagdbe)
+        {
+            /* TODO - fatal error, for now, flush so error cleared..... */
+            CVMX_CACHE_WBIL2I((l2c_err_ttg.u64 & 0x1fff80) | (1ULL << 63), 0);
+            CVMX_SYNC;
+	    PRINT_ERROR("L2C_TADX_INT(0)[TAGDBE]: Tag Double-Bit Error\n");
+        }
+	PRINT_ERROR("CVMX_L2C_ERR_TTG: 0x%llx\n", (unsigned long long)l2c_err_ttg.u64);
+    }
+    if (tadx_int.cn63xx.vbfdbe || tadx_int.cn63xx.vbfsbe)
+    {
+	/* L2 Victim buffer error */
+	if (tadx_int.cn63xx.vbfsbe)
+        {
+            /* No action here, hardware fixed up on write to DRAM */
+	    PRINT_ERROR("L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n");
+        }
+	if (tadx_int.cn63xx.vbfdbe)
+        {
+            /* TODO - fatal error.  Bad data written to DRAM. */
+	    PRINT_ERROR("L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n");
+        }
+	PRINT_ERROR("CVMX_L2C_ERR_VBF: 0x%llx\n", (unsigned long long)l2c_err_vbf.u64);
+    }
+
+    return 1;
+}

sys/contrib/octeon-sdk/cvmx-error-custom.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -83,6 +83,7 @@ int __cvmx_error_handle_pow_ecc_err_dbe(const struct cvmx_error_info *info);
 int __cvmx_error_handle_pow_ecc_err_iop(const struct cvmx_error_info *info);
 int __cvmx_error_handle_pow_ecc_err_rpe(const struct cvmx_error_info *info);
 int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info);
+int __cvmx_error_handle_63XX_l2_ecc(const struct cvmx_error_info *info);
 
 #ifdef	__cplusplus
 }

sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -102,7 +102,7 @@
  *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
  *     cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
  *     cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
- *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
  *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
  *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
  *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
@@ -120,7 +120,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -2908,22 +2908,6 @@ int cvmx_error_initialize_cn52xx(void)
     fail |= cvmx_error_add(&info);
 
     /* CVMX_PEXP_NPEI_INT_SUM */
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<59 /* c0_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 0;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
-    fail |= cvmx_error_add(&info);
-
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<21 /* c0_se */;
@@ -3195,22 +3179,6 @@ int cvmx_error_initialize_cn52xx(void)
         "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
     fail |= cvmx_error_add(&info);
 
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<60 /* c1_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 1;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
-    fail |= cvmx_error_add(&info);
-
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<28 /* c1_se */;
@@ -5355,6 +5323,22 @@ int cvmx_error_initialize_cn52xx(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;

sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -100,7 +100,7 @@
  *     cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
  *     cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
  *     cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
- *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"];
+ *     cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"];
  *     cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
  *     cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
  *     cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
@@ -118,7 +118,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -2824,22 +2824,6 @@ int cvmx_error_initialize_cn52xxp1(void)
     fail |= cvmx_error_add(&info);
 
     /* CVMX_PEXP_NPEI_INT_SUM */
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<59 /* c0_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<59 /* c0_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 0;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
-    fail |= cvmx_error_add(&info);
-
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<21 /* c0_se */;
@@ -3111,22 +3095,6 @@ int cvmx_error_initialize_cn52xxp1(void)
         "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
     fail |= cvmx_error_add(&info);
 
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
-    info.status_mask        = 1ull<<60 /* c1_ldwn */;
-    info.enable_addr        = CVMX_PEXP_NPEI_INT_ENB2;
-    info.enable_mask        = 1ull<<60 /* c1_ldwn */;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_PCI;
-    info.group_index        = 1;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
-    info.parent.status_mask = 1ull<<3 /* npei */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
-    fail |= cvmx_error_add(&info);
-
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_NPEI_INT_SUM;
     info.status_mask        = 1ull<<28 /* c1_se */;
@@ -5254,6 +5222,22 @@ int cvmx_error_initialize_cn52xxp1(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;

sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -124,7 +124,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
  *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
@@ -134,7 +134,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
  *     cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
@@ -5552,6 +5552,22 @@ int cvmx_error_initialize_cn56xx(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(1);
     info.status_mask        = 1ull<<4 /* synlos */;
@@ -6182,6 +6198,22 @@ int cvmx_error_initialize_cn56xx(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;

sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -124,7 +124,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
  *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
@@ -134,7 +134,7 @@
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
  *     cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
  *     cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
@@ -5120,6 +5120,22 @@ int cvmx_error_initialize_cn56xxp1(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(1);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 16;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(1);
     info.status_mask        = 1ull<<4 /* synlos */;
@@ -5750,6 +5766,22 @@ int cvmx_error_initialize_cn56xxp1(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;

sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM

sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -67,10 +67,8 @@
  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
  *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
- *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
+ *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
+ *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
  *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
  *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
@@ -86,7 +84,7 @@
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -142,9 +140,9 @@
  *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
  *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
  *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
- *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
+ *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
  *     cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
- *     cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
+ *     cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
  *     cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
  *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
  *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
@@ -769,12 +767,12 @@ int cvmx_error_initialize_cn63xx(void)
     info.user_info          = 0;
     fail |= cvmx_error_add(&info);
 
-    /* CVMX_L2C_ERR_TDTX(0) */
+    /* CVMX_L2C_TADX_INT(0) */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<60 /* vsbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<0 /* l2dsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<0 /* l2dsbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -783,14 +781,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
+        "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<61 /* vdbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<1 /* l2ddbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<1 /* l2ddbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -799,14 +799,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
+        "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<62 /* sbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<2 /* tagsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<2 /* tagsbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -815,14 +817,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
+        "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TDTX(0);
-    info.status_mask        = 1ull<<63 /* dbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<3 /* tagdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<3 /* tagdbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -831,44 +835,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
-    fail |= cvmx_error_add(&info);
-
-    /* CVMX_L2C_ERR_TTGX(0) */
-    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
-    info.status_mask        = 1ull<<61 /* noway */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
-    info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
-    info.group_index        = 0;
-    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
-    info.parent.status_addr = CVMX_L2C_INT_REG;
-    info.parent.status_mask = 1ull<<16 /* tad0 */;
-    info.func               = __cvmx_error_display;
-    info.user_info          = (long)
-        "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
-        "    L2C sets NOWAY during its processing of a\n"
-        "    transaction whenever it needed/wanted to allocate\n"
-        "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
-        "    is (generally) not an indication that L2C failed to\n"
-        "    complete transactions. Rather, it is a hint of\n"
-        "    possible performance degradation. (For example, L2C\n"
-        "    must read-modify-write DRAM for every transaction\n"
-        "    that updates some, but not all, of the bytes in a\n"
-        "    cache block, misses in the L2 cache, and cannot\n"
-        "    allocate a WAY.) There is one \"failure\" case where\n"
-        "    L2C will set NOWAY: when it cannot leave a block\n"
-        "    locked in the L2 cache as part of a LCKL2\n"
-        "    transaction.\n";
+        "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
-    info.status_mask        = 1ull<<62 /* sbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<4 /* vbfsbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<4 /* vbfsbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -877,14 +853,16 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
+        "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
     fail |= cvmx_error_add(&info);
 
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
-    info.status_addr        = CVMX_L2C_ERR_TTGX(0);
-    info.status_mask        = 1ull<<63 /* dbe */;
-    info.enable_addr        = 0;
-    info.enable_mask        = 0;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<5 /* vbfdbe */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<5 /* vbfdbe */;
     info.flags              = 0;
     info.group              = CVMX_ERROR_GROUP_INTERNAL;
     info.group_index        = 0;
@@ -893,7 +871,61 @@ int cvmx_error_initialize_cn63xx(void)
     info.parent.status_mask = 1ull<<16 /* tad0 */;
     info.func               = __cvmx_error_display;
     info.user_info          = (long)
-        "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
+        "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
+        "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
+        "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<6 /* noway */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<6 /* noway */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
+        "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
+        "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<7 /* rddislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<7 /* rddislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
+        "    A DRAM read  arrived before the LMC(s) were enabled\n";
+    fail |= cvmx_error_add(&info);
+
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_L2C_TADX_INT(0);
+    info.status_mask        = 1ull<<8 /* wrdislmc */;
+    info.enable_addr        = CVMX_L2C_TADX_IEN(0);
+    info.enable_mask        = 1ull<<8 /* wrdislmc */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_L2C_INT_REG;
+    info.parent.status_mask = 1ull<<16 /* tad0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
+        "    A DRAM write arrived before the LMC(s) were enabled\n";
     fail |= cvmx_error_add(&info);
 
     /* CVMX_IPD_INT_SUM */
@@ -1808,6 +1840,22 @@ int cvmx_error_initialize_cn63xx(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
@@ -4421,7 +4469,7 @@ int cvmx_error_initialize_cn63xx(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<0 /* sbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
@@ -4439,7 +4487,7 @@ int cvmx_error_initialize_cn63xx(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<1 /* dbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
@@ -6249,6 +6297,22 @@ int cvmx_error_initialize_cn63xx(void)
         "    See SRIOMAINT(0..1)_DROP_PACKET\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(0);
+    info.status_mask        = 1ull<<26 /* zero_pkt */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
+    info.enable_mask        = 1ull<<26 /* zero_pkt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<32 /* srio0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
+    fail |= cvmx_error_add(&info);
+
     /* CVMX_SRIOX_INT_REG(1) */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_SRIOX_INT_REG(1);
@@ -6486,6 +6550,22 @@ int cvmx_error_initialize_cn63xx(void)
         "    See SRIOMAINT(0..1)_DROP_PACKET\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_SRIOX_INT_REG(1);
+    info.status_mask        = 1ull<<26 /* zero_pkt */;
+    info.enable_addr        = CVMX_SRIOX_INT_ENABLE(1);
+    info.enable_mask        = 1ull<<26 /* zero_pkt */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_SRIO;
+    info.group_index        = 1;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<33 /* srio1 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR SRIOX_INT_REG(1)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
+    fail |= cvmx_error_add(&info);
+
     /* CVMX_PEXP_SLI_INT_SUM */
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;

sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -86,7 +86,7 @@
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
+ *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
  *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
@@ -1776,6 +1776,22 @@ int cvmx_error_initialize_cn63xxp1(void)
         "    in one of the 4 xaui lanes\n";
     fail |= cvmx_error_add(&info);
 
+    info.reg_type           = CVMX_ERROR_REGISTER_IO64;
+    info.status_addr        = CVMX_PCSXX_INT_REG(0);
+    info.status_mask        = 1ull<<3 /* bitlckls */;
+    info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
+    info.enable_mask        = 1ull<<3 /* bitlckls_en */;
+    info.flags              = 0;
+    info.group              = CVMX_ERROR_GROUP_ETHERNET;
+    info.group_index        = 0;
+    info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
+    info.parent.status_addr = CVMX_CIU_BLOCK_INT;
+    info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
+    info.func               = __cvmx_error_display;
+    info.user_info          = (long)
+        "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
+    fail |= cvmx_error_add(&info);
+
     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
     info.status_addr        = CVMX_PCSXX_INT_REG(0);
     info.status_mask        = 1ull<<4 /* synlos */;
@@ -4117,7 +4133,7 @@ int cvmx_error_initialize_cn63xxp1(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<0 /* sbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
@@ -4135,7 +4151,7 @@ int cvmx_error_initialize_cn63xxp1(void)
     info.enable_addr        = CVMX_DFM_FNT_IENA;
     info.enable_mask        = 1ull<<1 /* dbe_intena */;
     info.flags              = 0;
-    info.group              = CVMX_ERROR_GROUP_INTERNAL;
+    info.group              = CVMX_ERROR_GROUP_DFM;
     info.group_index        = 0;
     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
     info.parent.status_addr = CVMX_CIU_BLOCK_INT;

sys/contrib/octeon-sdk/cvmx-error.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,6 +51,9 @@
 #include <asm/octeon/cvmx-error-custom.h>
 #include <asm/octeon/cvmx-pcie.h>
 #include <asm/octeon/cvmx-srio.h>
+#include <asm/octeon/cvmx-ciu2-defs.h>
+#include <asm/octeon/cvmx-dfm-defs.h>
+#include <asm/octeon/cvmx-lmcx-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
 #else
 #include "cvmx.h"
@@ -63,8 +66,13 @@
 
 #define MAX_TABLE_SIZE 1024   /* Max number of error status bits we can support */
 
+extern int cvmx_error_initialize_cnf71xx(void);
+extern int cvmx_error_initialize_cn68xx(void);
+extern int cvmx_error_initialize_cn68xxp1(void);
+extern int cvmx_error_initialize_cn66xx(void);
 extern int cvmx_error_initialize_cn63xx(void);
 extern int cvmx_error_initialize_cn63xxp1(void);
+extern int cvmx_error_initialize_cn61xx(void);
 extern int cvmx_error_initialize_cn58xxp1(void);
 extern int cvmx_error_initialize_cn58xx(void);
 extern int cvmx_error_initialize_cn56xxp1(void);
@@ -221,6 +229,17 @@ int __cvmx_error_display(const cvmx_error_info_t *info)
     /* This assumes that all bits in the status register are RO or R/W1C */
     __cvmx_error_write_hw(info->reg_type, info->status_addr, info->status_mask);
     cvmx_safe_printf("%s", message);
+
+    /* Clear the source to reduce the chance for spurious interrupts.  */
+                                                                                
+    /* CN68XX has an CIU-15786 errata that accessing the ACK registers
+     * can stop interrupts from propagating
+     */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
+    else if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+        cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP4(cvmx_get_core_num()));
+
     return 1;
 }
 
@@ -237,7 +256,27 @@ int __cvmx_error_display(const cvmx_error_info_t *info)
 int cvmx_error_initialize(cvmx_error_flags_t flags)
 {
     __cvmx_error_flags = flags;
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
+    if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
+    {
+        if (cvmx_error_initialize_cnf71xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        if (cvmx_error_initialize_cn68xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
+    {
+        if (cvmx_error_initialize_cn68xxp1())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+    {
+        if (cvmx_error_initialize_cn66xx())
+            return -1;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
     {
         if (cvmx_error_initialize_cn63xx())
             return -1;
@@ -247,6 +286,11 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
         if (cvmx_error_initialize_cn63xxp1())
             return -1;
     }
+    else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+    {
+        if (cvmx_error_initialize_cn61xx())
+            return -1;
+    }
     else if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS1_X))
     {
         if (cvmx_error_initialize_cn58xxp1())
@@ -314,6 +358,11 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
     /* Enable all of the purely internal error sources by default */
     cvmx_error_enable_group(CVMX_ERROR_GROUP_INTERNAL, 0);
 
+    /* According to workaround for errata KEY-14814 in cn63xx, clearing 
+       SLI_INT_SUM[RML_TO] after enabling KEY interrupts */
+    if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+        cvmx_write_csr(CVMX_PEXP_SLI_INT_SUM, 1);
+
     /* Enable DDR error reporting based on the memory controllers */
     if (OCTEON_IS_MODEL(OCTEON_CN56XX))
     {
@@ -327,6 +376,32 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
     else
         cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 0);
 
+    /* Enable error interrupts for other LMC only if it is
+       available. */
+    if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+    {
+        int i;
+        for (i = 1; i < 4; i++)
+        {
+            cvmx_lmcx_dll_ctl2_t ctl2;
+            ctl2.u64 = cvmx_read_csr(CVMX_LMCX_DLL_CTL2(i));
+            if (ctl2.s.intf_en)
+                cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, i);
+        } 
+    }
+
+    /* Enable DFM error reporting based on feature availablility */
+    if (octeon_has_feature(OCTEON_FEATURE_DFM))
+    {
+        /* Only configure interrupts if DFM clock is enabled. */
+        cvmx_dfm_fnt_sclk_t dfm_fnt_sclk;
+        dfm_fnt_sclk.u64 = cvmx_read_csr(CVMX_DFM_FNT_SCLK);
+        if (!dfm_fnt_sclk.s.sclkdis)
+        {
+            cvmx_error_enable_group(CVMX_ERROR_GROUP_DFM, 0);
+        }
+    }
+
     /* Old PCI parts don't have a common PCI init, so enable error
         reporting if the bootloader told us we are a PCI host. PCIe
         is handled when cvmx_pcie_rc_initialize is called */
@@ -334,9 +409,8 @@ int cvmx_error_initialize(cvmx_error_flags_t flags)
         (cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST))
         cvmx_error_enable_group(CVMX_ERROR_GROUP_PCI, 0);
 
-    /* FIXME: Why is this needed for CN63XX? */
-    if (OCTEON_IS_MODEL(OCTEON_CN63XX))
-        cvmx_write_csr(CVMX_PEXP_SLI_INT_SUM, 1);
+    /* Call poll once to clear out any pending interrupts */
+    cvmx_error_poll();
 
     return 0;
 }
@@ -501,6 +575,24 @@ int cvmx_error_enable_group(cvmx_error_group_t group, int group_index)
     for (i = 0; i < __cvmx_error_table_size; i++)
     {
         const cvmx_error_info_t *h = &__cvmx_error_table[i];
+        /* SGMII and XAUI has different ipd_port, use the same group_index
+           for both the interfaces */
+        switch(group_index)
+        {
+            case 0x840:
+                group_index = 0x800;
+                break;
+            case 0xa40:
+                group_index = 0xa00;
+                break;
+            case 0xb40:
+                group_index = 0xb00;
+                break;
+            case 0xc40:
+                group_index = 0xc00;
+                break;
+        }
+            
         /* Skip entries that have a different group or group index. We
             also skip entries that don't have an enable */
         if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
@@ -544,6 +636,24 @@ int cvmx_error_disable_group(cvmx_error_group_t group, int group_index)
     for (i = 0; i < __cvmx_error_table_size; i++)
     {
         const cvmx_error_info_t *h = &__cvmx_error_table[i];
+
+        /* SGMII and XAUI has different ipd_port, use the same group_index
+           for both the interfaces */
+        switch(group_index)
+        {
+            case 0x840:
+                group_index = 0x800;
+                break;
+            case 0xa40:
+                group_index = 0xa00;
+                break;
+            case 0xb40:
+                group_index = 0xb00;
+                break;
+            case 0xc40:
+                group_index = 0xc00;
+                break;
+        }
         /* Skip entries that have a different group or group index. We
             also skip entries that don't have an enable */
         if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
@@ -641,3 +751,23 @@ int cvmx_error_disable(cvmx_error_register_t reg_type,
     }
 }
 
+
+/**
+ * Find the handler for a specific status register and mask
+ *
+ * @param status_addr
+ *                Status register address
+ *
+ * @return  Return the handler on success or null on failure.
+ */
+cvmx_error_info_t *cvmx_error_get_index(uint64_t status_addr)
+{
+    int i;
+    for (i = 0; i < __cvmx_error_table_size; i++)
+    {
+        if (__cvmx_error_table[i].status_addr == status_addr)
+            return &__cvmx_error_table[i];
+    }
+
+    return NULL;
+}

sys/contrib/octeon-sdk/cvmx-error.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -67,6 +67,8 @@ typedef enum
     CVMX_ERROR_GROUP_SRIO,      /* All errors related to SRIO when the bus is up. Index by port number (0-1) */
     CVMX_ERROR_GROUP_USB,       /* All errors related to USB when the port is enabled. Index by port number (0-1) */
     CVMX_ERROR_GROUP_LMC,       /* All errors related to LMC when the controller is enabled. Index by controller number (0-1) */
+    CVMX_ERROR_GROUP_ILK,       /* All errors related to ILK when the controller is enabled. Index by controller number (0-1) */
+    CVMX_ERROR_GROUP_DFM,       /* All errors related to DFM when the controller is enabled. */
 } cvmx_error_group_t;
 
 /**
@@ -311,6 +313,16 @@ int __cvmx_error_decode(const cvmx_error_info_t *info);
  */
 int __cvmx_error_display(const cvmx_error_info_t *info);
 
+/**
+ * Find the handler for a specific status register and mask
+ *
+ * @param status_addr
+ *                Status register address
+ *
+ * @return  Return the handler on success or null on failure.
+ */
+cvmx_error_info_t *cvmx_error_get_index(uint64_t status_addr);
+
 #ifdef	__cplusplus
 }
 #endif

sys/contrib/octeon-sdk/cvmx-fau.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Interface to the hardware Fetch and Add Unit.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_FAU_H__

sys/contrib/octeon-sdk/cvmx-flash.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides bootbus flash operations
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */

sys/contrib/octeon-sdk/cvmx-flash.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * This file provides bootbus flash operations
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  *
  */

sys/contrib/octeon-sdk/cvmx-fpa.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Support library for the hardware Free Pool Allocator.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 

sys/contrib/octeon-sdk/cvmx-fpa.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -43,7 +43,7 @@
  *
  * Interface to the hardware Free Pool Allocator.
  *
- * <hr>$Revision: 50048 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  *
  */
 
@@ -145,7 +145,12 @@ static inline void cvmx_fpa_enable(void)
     status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
     if (status.s.enb)
     {
-        cvmx_dprintf("Warning: Enabling FPA when FPA already enabled.\n");
+	/*
+	 * CN68XXP1 should not reset the FPA (doing so may break the
+	 * SSO, so we may end up enabling it more than once.  Just
+	 * return and don't spew messages.
+	 */
+	return;
     }
 
     status.u64 = 0;
@@ -154,13 +159,13 @@ static inline void cvmx_fpa_enable(void)
 }
 
 /**
- * Reset FPA to disable. Make sure buffers from all FPA pools are freed
+ * Reset FPA to disable. Make sure buffers from all FPA pools are freed 
  * before disabling FPA.
  */
 static inline void cvmx_fpa_disable(void)
 {
     cvmx_fpa_ctl_status_t status;
-    
+
     status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
     status.s.reset = 1;
     cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
@@ -204,7 +209,7 @@ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
 {
    cvmx_fpa_iobdma_data_t data;
 
-   /* Hardware only uses 64 bit alligned locations, so convert from byte address
+   /* Hardware only uses 64 bit aligned locations, so convert from byte address
    ** to 64-bit index
    */
    data.s.scraddr = scr_addr >> 3;

sys/contrib/octeon-sdk/cvmx-gmx.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Interface to the GMX hardware.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_GMX_H__

sys/contrib/octeon-sdk/cvmx-gpio-defs.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
  * <hr>$Revision$<hr>
  *
  */
-#ifndef __CVMX_GPIO_TYPEDEFS_H__
-#define __CVMX_GPIO_TYPEDEFS_H__
+#ifndef __CVMX_GPIO_DEFS_H__
+#define __CVMX_GPIO_DEFS_H__
 
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
@@ -63,7 +63,11 @@ static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 15))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
 		cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
 }
@@ -87,7 +91,11 @@ static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 		cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
 }
@@ -98,7 +106,11 @@ static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
 static inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset)
 {
 	if (!(
-	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 		cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
 }
@@ -117,7 +129,40 @@ static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
 #endif
 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_MULTI_CAST CVMX_GPIO_MULTI_CAST_FUNC()
+static inline uint64_t CVMX_GPIO_MULTI_CAST_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+		cvmx_warn("CVMX_GPIO_MULTI_CAST not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008B0ull);
+}
+#else
+#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_PIN_ENA CVMX_GPIO_PIN_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_PIN_ENA_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
+		cvmx_warn("CVMX_GPIO_PIN_ENA not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008B8ull);
+}
+#else
+#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
+#endif
 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_GPIO_TIM_CTL CVMX_GPIO_TIM_CTL_FUNC()
+static inline uint64_t CVMX_GPIO_TIM_CTL_FUNC(void)
+{
+	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+		cvmx_warn("CVMX_GPIO_TIM_CTL not supported on this chip\n");
+	return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
+}
+#else
+#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#endif
 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
@@ -126,7 +171,10 @@ static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
 	if (!(
 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
-	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23))))))
+	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 16) && (offset <= 19)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 16) && (offset <= 19)))) ||
+	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 16) && (offset <= 19))))))
 		cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
 	return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16;
 }
@@ -136,18 +184,20 @@ static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
 
 /**
  * cvmx_gpio_bit_cfg#
+ *
+ * Notes:
+ * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
+ * will not be used, read out always zero.
  */
-union cvmx_gpio_bit_cfgx
-{
+union cvmx_gpio_bit_cfgx {
 	uint64_t u64;
-	struct cvmx_gpio_bit_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_bit_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_17_63               : 47;
 	uint64_t synce_sel                    : 2;  /**< Selects the QLM clock output
                                                          x0=Normal GPIO output
-                                                         01=GPIO QLM clock selected by GPIO_CLK_QLM0
-                                                         11=GPIO QLM clock selected by GPIO_CLK_QLM1 */
+                                                         01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
+                                                         11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
 	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
 	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
 	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
@@ -171,9 +221,8 @@ union cvmx_gpio_bit_cfgx
 	uint64_t reserved_17_63               : 47;
 #endif
 	} s;
-	struct cvmx_gpio_bit_cfgx_cn30xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_bit_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
 	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
@@ -197,9 +246,8 @@ union cvmx_gpio_bit_cfgx
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn38xx;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn38xxp2;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn50xx;
-	struct cvmx_gpio_bit_cfgx_cn52xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_bit_cfgx_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_15_63               : 49;
 	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
 	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
@@ -228,20 +276,23 @@ union cvmx_gpio_bit_cfgx
 	struct cvmx_gpio_bit_cfgx_cn52xx      cn56xxp1;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn58xx;
 	struct cvmx_gpio_bit_cfgx_cn30xx      cn58xxp1;
+	struct cvmx_gpio_bit_cfgx_s           cn61xx;
 	struct cvmx_gpio_bit_cfgx_s           cn63xx;
 	struct cvmx_gpio_bit_cfgx_s           cn63xxp1;
+	struct cvmx_gpio_bit_cfgx_s           cn66xx;
+	struct cvmx_gpio_bit_cfgx_s           cn68xx;
+	struct cvmx_gpio_bit_cfgx_s           cn68xxp1;
+	struct cvmx_gpio_bit_cfgx_s           cnf71xx;
 };
 typedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t;
 
 /**
  * cvmx_gpio_boot_ena
  */
-union cvmx_gpio_boot_ena
-{
+union cvmx_gpio_boot_ena {
 	uint64_t u64;
-	struct cvmx_gpio_boot_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_boot_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t boot_ena                     : 4;  /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
 	uint64_t reserved_0_7                 : 8;
@@ -260,12 +311,10 @@ typedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t;
 /**
  * cvmx_gpio_clk_gen#
  */
-union cvmx_gpio_clk_genx
-{
+union cvmx_gpio_clk_genx {
 	uint64_t u64;
-	struct cvmx_gpio_clk_genx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_clk_genx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_32_63               : 32;
 	uint64_t n                            : 32; /**< Determines the frequency of the GPIO clk generator
                                                          NOTE: Fgpio_clk = Feclk * N / 2^32
@@ -281,8 +330,13 @@ union cvmx_gpio_clk_genx
 	struct cvmx_gpio_clk_genx_s           cn52xxp1;
 	struct cvmx_gpio_clk_genx_s           cn56xx;
 	struct cvmx_gpio_clk_genx_s           cn56xxp1;
+	struct cvmx_gpio_clk_genx_s           cn61xx;
 	struct cvmx_gpio_clk_genx_s           cn63xx;
 	struct cvmx_gpio_clk_genx_s           cn63xxp1;
+	struct cvmx_gpio_clk_genx_s           cn66xx;
+	struct cvmx_gpio_clk_genx_s           cn68xx;
+	struct cvmx_gpio_clk_genx_s           cn68xxp1;
+	struct cvmx_gpio_clk_genx_s           cnf71xx;
 };
 typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
 
@@ -290,6 +344,7 @@ typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
  * cvmx_gpio_clk_qlm#
  *
  * Notes:
+ * QLM0(A) and QLM1(B) can configured to source any of QLM0 or QLM2 as clock source.
  * Clock speed output for different modes ...
  *
  *                        Speed With      Speed with
@@ -301,12 +356,59 @@ typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
  *      5.0                 250             125
  *      6.25                312.5           156.25
  */
-union cvmx_gpio_clk_qlmx
-{
+union cvmx_gpio_clk_qlmx {
 	uint64_t u64;
-	struct cvmx_gpio_clk_qlmx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_clk_qlmx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_11_63               : 53;
+	uint64_t qlm_sel                      : 3;  /**< Selects which DLM to select from
+                                                         x0 = select DLM0 as clock source
+                                                         x1 = Disabled */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t div                          : 1;  /**< Internal clock divider
+                                                         0=DIV2
+                                                         1=DIV4 */
+	uint64_t lane_sel                     : 2;  /**< Selects which RX lane clock from QLMx to use as
+                                                         the GPIO internal QLMx clock.  The GPIO block can
+                                                         support upto two unique clocks to send out any
+                                                         GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
+                                                         The clock can either be a divided by 2 or divide
+                                                         by 4 of the selected RX lane clock. */
+#else
+	uint64_t lane_sel                     : 2;
+	uint64_t div                          : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qlm_sel                      : 3;
+	uint64_t reserved_11_63               : 53;
+#endif
+	} s;
+	struct cvmx_gpio_clk_qlmx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_10_63               : 54;
+	uint64_t qlm_sel                      : 2;  /**< Selects which QLM to select from
+                                                         01 = select QLM0 as clock source
+                                                         1x = select QLM2 as clock source
+                                                         0  = Disabled */
+	uint64_t reserved_3_7                 : 5;
+	uint64_t div                          : 1;  /**< Internal clock divider
+                                                         0=DIV2
+                                                         1=DIV4 */
+	uint64_t lane_sel                     : 2;  /**< Selects which RX lane clock from QLMx to use as
+                                                         the GPIO internal QLMx clock.  The GPIO block can
+                                                         support upto two unique clocks to send out any
+                                                         GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
+                                                         The clock can either be a divided by 2 or divide
+                                                         by 4 of the selected RX lane clock. */
+#else
+	uint64_t lane_sel                     : 2;
+	uint64_t div                          : 1;
+	uint64_t reserved_3_7                 : 5;
+	uint64_t qlm_sel                      : 2;
+	uint64_t reserved_10_63               : 54;
+#endif
+	} cn61xx;
+	struct cvmx_gpio_clk_qlmx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_3_63                : 61;
 	uint64_t div                          : 1;  /**< Internal clock divider
                                                          0=DIV2
@@ -322,21 +424,22 @@ union cvmx_gpio_clk_qlmx
 	uint64_t div                          : 1;
 	uint64_t reserved_3_63                : 61;
 #endif
-	} s;
-	struct cvmx_gpio_clk_qlmx_s           cn63xx;
-	struct cvmx_gpio_clk_qlmx_s           cn63xxp1;
+	} cn63xx;
+	struct cvmx_gpio_clk_qlmx_cn63xx      cn63xxp1;
+	struct cvmx_gpio_clk_qlmx_cn61xx      cn66xx;
+	struct cvmx_gpio_clk_qlmx_s           cn68xx;
+	struct cvmx_gpio_clk_qlmx_s           cn68xxp1;
+	struct cvmx_gpio_clk_qlmx_cn61xx      cnf71xx;
 };
 typedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t;
 
 /**
  * cvmx_gpio_dbg_ena
  */
-union cvmx_gpio_dbg_ena
-{
+union cvmx_gpio_dbg_ena {
 	uint64_t u64;
-	struct cvmx_gpio_dbg_ena_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_dbg_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_21_63               : 43;
 	uint64_t dbg_ena                      : 21; /**< Enable the debug port to be driven on the gpio */
 #else
@@ -352,13 +455,15 @@ typedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t;
 
 /**
  * cvmx_gpio_int_clr
+ *
+ * Notes:
+ * Only 16 out of 20 GPIOs support interrupt.GPIO_INT_CLR only apply to GPIO0-GPIO15.
+ *
  */
-union cvmx_gpio_int_clr
-{
+union cvmx_gpio_int_clr {
 	uint64_t u64;
-	struct cvmx_gpio_int_clr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_int_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t type                         : 16; /**< Clear the interrupt rising edge detector */
 #else
@@ -377,20 +482,126 @@ union cvmx_gpio_int_clr
 	struct cvmx_gpio_int_clr_s            cn56xxp1;
 	struct cvmx_gpio_int_clr_s            cn58xx;
 	struct cvmx_gpio_int_clr_s            cn58xxp1;
+	struct cvmx_gpio_int_clr_s            cn61xx;
 	struct cvmx_gpio_int_clr_s            cn63xx;
 	struct cvmx_gpio_int_clr_s            cn63xxp1;
+	struct cvmx_gpio_int_clr_s            cn66xx;
+	struct cvmx_gpio_int_clr_s            cn68xx;
+	struct cvmx_gpio_int_clr_s            cn68xxp1;
+	struct cvmx_gpio_int_clr_s            cnf71xx;
 };
 typedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t;
 
+/**
+ * cvmx_gpio_multi_cast
+ *
+ * Notes:
+ * GPIO<7:4> have the option of operating in GPIO Interrupt Multicast mode.  In
+ * this mode, the PP GPIO interrupts (CIU_INT<0-7>_SUM0/CIU_INT<0-3>_SUM4[GPIO<7:4>] values are
+ * stored per cnMIPS core.
+ * For GPIO<7:4> (x=4-7):
+ *    When GPIO_MULTI_CAST[EN] = 1:
+ *        When GPIO_BIT_CFGx[INT_EN]==1 &  GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
+ *          * Reads to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will return a unique interrupt state per
+ *            cnMIPS core.
+ *          * Reads to CIU_INT32/33_SUM0/4[GPIO<x>] will return the common GPIO<x>
+ *            interrupt state.
+ *          * Write of '1' to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will clear the individual
+ *            interrupt associated with the cnMIPS core.
+ *          * Write of '1' to CIU_INT32/33_SUM0/4[GPIO<x>] will clear the common GPIO<x>
+ *            interrupt state.
+ *          * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
+ *            CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
+ *        When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
+ *          * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
+ *            will have no effects.
+ *     When GPIO_MULTI_CAST[EN] = 0:
+ *        * Write of '1' to CIU_INT_SUM0/4[GPIO<x>] will have no effects, as this field is RO,
+ *          backward compatible with o63.
+ *        When GPIO_BIT_CFGx[INT_EN]==1 &  GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
+ *          * Reads to CIU_INT*_SUM0/4[GPIO<x>] will return the common GPIO<X> interrupt state.
+ *          * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
+ *            CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
+ *        When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
+ *          * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
+ *            will have no effects.
+ *
+ * GPIO<15:8> and GPIO<3:0> will never be in multicast mode as those don't have per cnMIPS capabilities.
+ * For GPIO<y> (y=0-3,8-15):
+ *    When GPIO_BIT_CFGx[INT_EN]==1 &  GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
+ *       * Reads to CIU_INT*_SUM0/4[GPIO<y>] will return the common GPIO<y> interrupt state.
+ *       * Write of '1' to GPIO_INT_CLR[TYPE<y>] will clear all CIU_INT*_SUM0/4[GPIO<y>] common GPIO<y>
+ *         interrupt states.
+ *       When GPIO_MULTI_CAST[EN] = 1:
+ *         * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] will clear the common GPIO<y> interrupt state.
+ *       When GPIO_MULTI_CAST[EN] = 0:
+ *         * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] has no effect, as this field is RO,
+ *           backward compatible to o63.
+ *    When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
+ *       * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<y>]
+ *         will have no effects.
+ *
+ * Whenever there is mode change, (GPIO_BIT_CFGx[INT_EN] or  GPIO_BIT_CFGx[INT_TYPE] or GPIO_MULTI_CAST[EN])
+ * software needs to write to  $GPIO_INT_CLR to clear up all pending/stale interrupts.
+ */
+union cvmx_gpio_multi_cast {
+	uint64_t u64;
+	struct cvmx_gpio_multi_cast_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_1_63                : 63;
+	uint64_t en                           : 1;  /**< Enable GPIO Interrupt Multicast mode
+                                                         When EN is set, GPIO<7:4> will function in
+                                                         multicast mode allowing these four GPIOs to
+                                                         interrupt multi-cores.
+                                                         Multicast functionality allows the GPIO to exist
+                                                         as per cnMIPS interrupts as opposed to a global
+                                                         interrupt. */
+#else
+	uint64_t en                           : 1;
+	uint64_t reserved_1_63                : 63;
+#endif
+	} s;
+	struct cvmx_gpio_multi_cast_s         cn61xx;
+	struct cvmx_gpio_multi_cast_s         cnf71xx;
+};
+typedef union cvmx_gpio_multi_cast cvmx_gpio_multi_cast_t;
+
+/**
+ * cvmx_gpio_pin_ena
+ *
+ * Notes:
+ * GPIO0-GPIO17 has dedicated pins.
+ * GPIO18 share pin with UART (UART0_CTS_L/GPIO_18), GPIO18 enabled when $GPIO_PIN_ENA[ENA18]=1
+ * GPIO19 share pin with UART (UART1_CTS_L/GPIO_19), GPIO18 enabled when $GPIO_PIN_ENA[ENA19]=1
+ */
+union cvmx_gpio_pin_ena {
+	uint64_t u64;
+	struct cvmx_gpio_pin_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t ena19                        : 1;  /**< If 0, UART1_CTS_L/GPIO_19 pin is UART pin
+                                                         If 1, UART1_CTS_L/GPIO_19 pin is GPIO19 pin */
+	uint64_t ena18                        : 1;  /**< If 0, UART0_CTS_L/GPIO_18 pin is UART pin
+                                                         If 1, UART0_CTS_L/GPIO_18 pin is GPIO18 pin */
+	uint64_t reserved_0_17                : 18;
+#else
+	uint64_t reserved_0_17                : 18;
+	uint64_t ena18                        : 1;
+	uint64_t ena19                        : 1;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} s;
+	struct cvmx_gpio_pin_ena_s            cn66xx;
+};
+typedef union cvmx_gpio_pin_ena cvmx_gpio_pin_ena_t;
+
 /**
  * cvmx_gpio_rx_dat
  */
-union cvmx_gpio_rx_dat
-{
+union cvmx_gpio_rx_dat {
 	uint64_t u64;
-	struct cvmx_gpio_rx_dat_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_rx_dat_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t dat                          : 24; /**< GPIO Read Data */
 #else
@@ -400,9 +611,8 @@ union cvmx_gpio_rx_dat
 	} s;
 	struct cvmx_gpio_rx_dat_s             cn30xx;
 	struct cvmx_gpio_rx_dat_s             cn31xx;
-	struct cvmx_gpio_rx_dat_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_rx_dat_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t dat                          : 16; /**< GPIO Read Data */
 #else
@@ -418,20 +628,50 @@ union cvmx_gpio_rx_dat
 	struct cvmx_gpio_rx_dat_cn38xx        cn56xxp1;
 	struct cvmx_gpio_rx_dat_cn38xx        cn58xx;
 	struct cvmx_gpio_rx_dat_cn38xx        cn58xxp1;
+	struct cvmx_gpio_rx_dat_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t dat                          : 20; /**< GPIO Read Data */
+#else
+	uint64_t dat                          : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
 	struct cvmx_gpio_rx_dat_cn38xx        cn63xx;
 	struct cvmx_gpio_rx_dat_cn38xx        cn63xxp1;
+	struct cvmx_gpio_rx_dat_cn61xx        cn66xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn68xx;
+	struct cvmx_gpio_rx_dat_cn38xx        cn68xxp1;
+	struct cvmx_gpio_rx_dat_cn61xx        cnf71xx;
 };
 typedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t;
 
+/**
+ * cvmx_gpio_tim_ctl
+ */
+union cvmx_gpio_tim_ctl {
+	uint64_t u64;
+	struct cvmx_gpio_tim_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_4_63                : 60;
+	uint64_t sel                          : 4;  /**< Selects the GPIO pin to route to TIM */
+#else
+	uint64_t sel                          : 4;
+	uint64_t reserved_4_63                : 60;
+#endif
+	} s;
+	struct cvmx_gpio_tim_ctl_s            cn68xx;
+	struct cvmx_gpio_tim_ctl_s            cn68xxp1;
+};
+typedef union cvmx_gpio_tim_ctl cvmx_gpio_tim_ctl_t;
+
 /**
  * cvmx_gpio_tx_clr
  */
-union cvmx_gpio_tx_clr
-{
+union cvmx_gpio_tx_clr {
 	uint64_t u64;
-	struct cvmx_gpio_tx_clr_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_clr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t clr                          : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
                                                          to '0'. When read, CLR returns the GPIO_TX_DAT
@@ -443,9 +683,8 @@ union cvmx_gpio_tx_clr
 	} s;
 	struct cvmx_gpio_tx_clr_s             cn30xx;
 	struct cvmx_gpio_tx_clr_s             cn31xx;
-	struct cvmx_gpio_tx_clr_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_clr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t clr                          : 16; /**< Bit mask to indicate which bits to drive to '0'. */
 #else
@@ -461,20 +700,33 @@ union cvmx_gpio_tx_clr
 	struct cvmx_gpio_tx_clr_cn38xx        cn56xxp1;
 	struct cvmx_gpio_tx_clr_cn38xx        cn58xx;
 	struct cvmx_gpio_tx_clr_cn38xx        cn58xxp1;
+	struct cvmx_gpio_tx_clr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t clr                          : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
+                                                         to '0'. When read, CLR returns the GPIO_TX_DAT
+                                                         storage. */
+#else
+	uint64_t clr                          : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
 	struct cvmx_gpio_tx_clr_cn38xx        cn63xx;
 	struct cvmx_gpio_tx_clr_cn38xx        cn63xxp1;
+	struct cvmx_gpio_tx_clr_cn61xx        cn66xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn68xx;
+	struct cvmx_gpio_tx_clr_cn38xx        cn68xxp1;
+	struct cvmx_gpio_tx_clr_cn61xx        cnf71xx;
 };
 typedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t;
 
 /**
  * cvmx_gpio_tx_set
  */
-union cvmx_gpio_tx_set
-{
+union cvmx_gpio_tx_set {
 	uint64_t u64;
-	struct cvmx_gpio_tx_set_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_24_63               : 40;
 	uint64_t set                          : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
                                                          to '1'. When read, SET returns the GPIO_TX_DAT
@@ -486,9 +738,8 @@ union cvmx_gpio_tx_set
 	} s;
 	struct cvmx_gpio_tx_set_s             cn30xx;
 	struct cvmx_gpio_tx_set_s             cn31xx;
-	struct cvmx_gpio_tx_set_cn38xx
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_tx_set_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_16_63               : 48;
 	uint64_t set                          : 16; /**< Bit mask to indicate which bits to drive to '1'. */
 #else
@@ -504,20 +755,67 @@ union cvmx_gpio_tx_set
 	struct cvmx_gpio_tx_set_cn38xx        cn56xxp1;
 	struct cvmx_gpio_tx_set_cn38xx        cn58xx;
 	struct cvmx_gpio_tx_set_cn38xx        cn58xxp1;
+	struct cvmx_gpio_tx_set_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_20_63               : 44;
+	uint64_t set                          : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
+                                                         to '1'. When read, SET returns the GPIO_TX_DAT
+                                                         storage. */
+#else
+	uint64_t set                          : 20;
+	uint64_t reserved_20_63               : 44;
+#endif
+	} cn61xx;
 	struct cvmx_gpio_tx_set_cn38xx        cn63xx;
 	struct cvmx_gpio_tx_set_cn38xx        cn63xxp1;
+	struct cvmx_gpio_tx_set_cn61xx        cn66xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn68xx;
+	struct cvmx_gpio_tx_set_cn38xx        cn68xxp1;
+	struct cvmx_gpio_tx_set_cn61xx        cnf71xx;
 };
 typedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t;
 
 /**
  * cvmx_gpio_xbit_cfg#
+ *
+ * Notes:
+ * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
+ * will not be used, read out always zero.
  */
-union cvmx_gpio_xbit_cfgx
-{
+union cvmx_gpio_xbit_cfgx {
 	uint64_t u64;
-	struct cvmx_gpio_xbit_cfgx_s
-	{
-#if __BYTE_ORDER == __BIG_ENDIAN
+	struct cvmx_gpio_xbit_cfgx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+	uint64_t reserved_17_63               : 47;
+	uint64_t synce_sel                    : 2;  /**< Selects the QLM clock output
+                                                         x0=Normal GPIO output
+                                                         01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
+                                                         11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
+	uint64_t clk_gen                      : 1;  /**< When TX_OE is set, GPIO pin becomes a clock */
+	uint64_t clk_sel                      : 2;  /**< Selects which of the 4 GPIO clock generators */
+	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
+	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
+	uint64_t int_type                     : 1;  /**< Type of interrupt
+                                                         0 = level (default)
+                                                         1 = rising edge */
+	uint64_t int_en                       : 1;  /**< Bit mask to indicate which bits to raise interrupt */
+	uint64_t rx_xor                       : 1;  /**< Invert the GPIO pin */
+	uint64_t tx_oe                        : 1;  /**< Drive the GPIO pin as an output pin */
+#else
+	uint64_t tx_oe                        : 1;
+	uint64_t rx_xor                       : 1;
+	uint64_t int_en                       : 1;
+	uint64_t int_type                     : 1;
+	uint64_t fil_cnt                      : 4;
+	uint64_t fil_sel                      : 4;
+	uint64_t clk_sel                      : 2;
+	uint64_t clk_gen                      : 1;
+	uint64_t synce_sel                    : 2;
+	uint64_t reserved_17_63               : 47;
+#endif
+	} s;
+	struct cvmx_gpio_xbit_cfgx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint64_t reserved_12_63               : 52;
 	uint64_t fil_sel                      : 4;  /**< Global counter bit-select (controls sample rate) */
 	uint64_t fil_cnt                      : 4;  /**< Number of consecutive samples to change state */
@@ -532,10 +830,12 @@ union cvmx_gpio_xbit_cfgx
 	uint64_t fil_sel                      : 4;
 	uint64_t reserved_12_63               : 52;
 #endif
-	} s;
-	struct cvmx_gpio_xbit_cfgx_s          cn30xx;
-	struct cvmx_gpio_xbit_cfgx_s          cn31xx;
-	struct cvmx_gpio_xbit_cfgx_s          cn50xx;
+	} cn30xx;
+	struct cvmx_gpio_xbit_cfgx_cn30xx     cn31xx;
+	struct cvmx_gpio_xbit_cfgx_cn30xx     cn50xx;
+	struct cvmx_gpio_xbit_cfgx_s          cn61xx;
+	struct cvmx_gpio_xbit_cfgx_s          cn66xx;
+	struct cvmx_gpio_xbit_cfgx_s          cnf71xx;
 };
 typedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t;
 

sys/contrib/octeon-sdk/cvmx-gpio.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * General Purpose IO interface.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 
 #ifndef __CVMX_GPIO_H__
@@ -64,17 +64,78 @@ extern "C" {
  * Clear the interrupt rising edge detector for the supplied
  * pins in the mask. Chips which have more than 16 GPIO pins
  * can't use them for interrupts.
- *
+ e
  * @param clear_mask Mask of pins to clear
  */
 static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask)
 {
+    if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+    {
+        cvmx_gpio_multi_cast_t multi_cast;
+        cvmx_gpio_bit_cfgx_t gpio_bit;
+        int core = cvmx_get_core_num();
+        
+        multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST);
+        gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core));
+
+        /* If Multicast mode is enabled, and GPIO interrupt is enabled for
+           edge detection, then GPIO<4..7> interrupts are per core */
+        if (multi_cast.s.en && gpio_bit.s.int_en && gpio_bit.s.int_type)
+        {
+            /* Clear GPIO<4..7> per core */
+            cvmx_ciu_intx_sum0_t ciu_sum0;
+            ciu_sum0.u64 = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core * 2));
+            ciu_sum0.s.gpio = clear_mask & 0xf0;
+            cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64);
+
+            /* Clear other GPIO pins for all cores. */
+            cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0));
+            return;
+        }
+    }
+    /* Clear GPIO pins state across all cores and common interrupt states. */ 
     cvmx_gpio_int_clr_t gpio_int_clr;
     gpio_int_clr.u64 = 0;
     gpio_int_clr.s.type = clear_mask;
     cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
 }
 
+/**
+ * GPIO Output Pin
+ *
+ * @param bit   The GPIO to use
+ * @param mode  Drive GPIO as output pin or not.
+ *
+ */
+static inline void cvmx_gpio_cfg(int bit, int mode)
+{
+    if (bit > 15 && bit < 20)
+    {
+        /* CN61XX/CN66XX has 20 GPIO pins and only 16 are interruptable. */
+        if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
+        {
+            cvmx_gpio_xbit_cfgx_t gpio_xbit;
+            gpio_xbit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(bit));
+            if (mode)
+                gpio_xbit.s.tx_oe = 1;
+            else
+                gpio_xbit.s.tx_oe = 0;
+            cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64);
+        }
+        else
+            cvmx_dprintf("cvmx_gpio_cfg: Invalid GPIO bit(%d)\n", bit);
+    }
+    else
+    {
+        cvmx_gpio_bit_cfgx_t gpio_bit;
+        gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit));
+        if (mode)
+            gpio_bit.s.tx_oe = 1;
+        else
+            gpio_bit.s.tx_oe = 0;
+        cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64);
+    }
+}
 
 /**
  * GPIO Read Data

sys/contrib/octeon-sdk/cvmx-helper-board.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2011  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Helper functions to abstract board specific data about
  * network ports from the rest of the cvmx-helper files.
  *
- * <hr>$Revision: 49627 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <linux/module.h>
@@ -72,6 +72,13 @@
 #include "cvmx-helper.h"
 #include "cvmx-helper-util.h"
 #include "cvmx-helper-board.h"
+#include "cvmx-gpio.h"
+#ifdef __U_BOOT__
+# include <libfdt.h>
+#else
+# include "libfdt/libfdt.h"
+#endif
+#include "cvmx-swap.h"
 #endif
 
 /**
@@ -84,6 +91,245 @@
  */
 CVMX_SHARED cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port) = NULL;
 
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+
+static void cvmx_retry_i2c_write(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
+{
+    int tries = 3;
+    int r;
+    do {
+        r = cvmx_twsix_write_ia(twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data);
+    } while (tries-- > 0 && r < 0);
+}
+
+static int __pip_eth_node(const void *fdt_addr, int aliases, int ipd_port)
+{
+    char name_buffer[20];
+    const char*pip_path;
+    int pip, iface, eth;
+    int interface_num    = cvmx_helper_get_interface_num(ipd_port);
+    int interface_index  = cvmx_helper_get_interface_index_num(ipd_port);
+
+    pip_path = fdt_getprop(fdt_addr, aliases, "pip", NULL);
+    if (!pip_path)
+    {
+        cvmx_dprintf("ERROR: pip path not found in device tree\n");
+        return -1;
+    }
+    pip = fdt_path_offset(fdt_addr, pip_path);
+    if (pip < 0)
+    {
+        cvmx_dprintf("ERROR: pip not found in device tree\n");
+        return -1;
+    }
+#ifdef __U_BOOT__
+    sprintf(name_buffer, "interface@%d", interface_num);
+#else
+    snprintf(name_buffer, sizeof(name_buffer), "interface@%d", interface_num);
+#endif
+    iface =  fdt_subnode_offset(fdt_addr, pip, name_buffer);
+    if (iface < 0)
+    {
+        cvmx_dprintf("ERROR : pip intf %d not found in device tree \n",
+                     interface_num);
+        return -1;
+    }
+#ifdef __U_BOOT__
+    sprintf(name_buffer, "ethernet@%x", interface_index);
+#else
+    snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", interface_index);
+#endif
+    eth = fdt_subnode_offset(fdt_addr, iface, name_buffer);
+    if (eth < 0)
+    {
+        cvmx_dprintf("ERROR : pip interface@%d ethernet@%d not found in device "
+                     "tree\n", interface_num, interface_index);
+        return -1;
+    }
+    return eth;
+}
+
+static int __mix_eth_node(const void *fdt_addr, int aliases, int interface_index)
+{
+    char name_buffer[20];
+    const char*mix_path;
+    int mix;
+
+#ifdef __U_BOOT__
+    sprintf(name_buffer, "mix%d", interface_index);
+#else
+    snprintf(name_buffer, sizeof(name_buffer), "mix%d", interface_index);
+#endif
+    mix_path = fdt_getprop(fdt_addr, aliases, name_buffer, NULL);
+    if (!mix_path)
+    {
+        cvmx_dprintf("ERROR: mix%d path not found in device tree\n",interface_index);
+    }
+    mix = fdt_path_offset(fdt_addr, mix_path);
+    if (mix < 0)
+    {
+        cvmx_dprintf("ERROR: %s not found in device tree\n", mix_path);
+        return -1;
+    }
+    return mix;
+}
+
+typedef struct cvmx_phy_info
+{
+    int phy_addr;
+    int direct_connect;
+    cvmx_phy_type_t phy_type;
+}cvmx_phy_info_t;
+
+
+static int __mdiobus_addr_to_unit(uint32_t addr)
+{
+    int unit = (addr >> 7) & 3;
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+        unit >>= 1;
+    return unit;
+}
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. The phy address is obtained from the device tree.
+ *
+ * @param ipd_port Octeon IPD port to get the MII address for.
+ *
+ * @return MII PHY address and bus number or -1.
+ */
+
+static cvmx_phy_info_t __get_phy_info_from_dt(int ipd_port)
+{
+    const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr);
+    uint32_t *phy_handle;
+    int aliases, eth, phy, phy_parent, phandle, ret;
+    cvmx_phy_info_t phy_info;
+    int mdio_unit=-1;
+    const char *phy_comaptible_str;
+    uint32_t *phy_addr_ptr;
+
+    phy_info.phy_addr = -1;
+    phy_info.direct_connect = -1;
+    phy_info.phy_type = (cvmx_phy_type_t) -1;
+
+    if (!fdt_addr)
+    {
+        cvmx_dprintf("No device tree found.\n");
+        return phy_info;
+    }
+    aliases = fdt_path_offset(fdt_addr, "/aliases");
+    if (aliases < 0) {
+        cvmx_dprintf("Error: No /aliases node in device tree.\n");
+        return phy_info;
+    }
+    if (ipd_port < 0)
+    {
+        int interface_index = ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
+        eth = __mix_eth_node(fdt_addr, aliases, interface_index) ;
+    }
+    else
+    {
+        eth = __pip_eth_node(fdt_addr, aliases, ipd_port);
+    }
+    if (eth < 0 )
+    {
+        cvmx_dprintf("ERROR : cannot find interface for ipd_port=%d\n", ipd_port);
+        return phy_info;
+    }
+    /* Get handle to phy */
+    phy_handle = (uint32_t *) fdt_getprop(fdt_addr, eth, "phy-handle", NULL);
+    if (!phy_handle)
+    {
+        cvmx_dprintf("ERROR : phy handle not found in device tree ipd_port=%d"
+                     "\n", ipd_port);
+        return phy_info;
+    }
+    phandle = cvmx_be32_to_cpu(*phy_handle);
+    phy = fdt_node_offset_by_phandle(fdt_addr, phandle);
+    if (phy < 0)
+    {
+        cvmx_dprintf("ERROR : cannot find phy for ipd_port=%d ret=%d\n",
+                     ipd_port, phy);
+        return phy_info;
+    }
+    phy_comaptible_str = (const char *) fdt_getprop(fdt_addr, phy,
+                                                    "compatible", NULL);
+    if (!phy_comaptible_str)
+    {
+        cvmx_dprintf("ERROR : no compatible prop in phy\n");
+        return phy_info;
+    }
+    if (memcmp("marvell", phy_comaptible_str, strlen("marvell")) == 0)
+    {
+        phy_info.phy_type = MARVELL_GENERIC_PHY;
+    }
+    else if (memcmp("broadcom", phy_comaptible_str, strlen("broadcom")) == 0)
+    {
+        phy_info.phy_type = BROADCOM_GENERIC_PHY;
+    }
+    else
+    {
+        phy_info.phy_type = -1;
+    }
+
+    /* Check if PHY parent is the octeon MDIO bus. Some boards are connected
+       though a MUX and for them direct_connect_to_phy will be 0 */
+    phy_parent = fdt_parent_offset(fdt_addr, phy);
+    if (phy_parent < 0)
+    {
+        cvmx_dprintf("ERROR : cannot find phy parent for ipd_port=%d ret=%d\n",
+                     ipd_port, phy_parent);
+        return phy_info;
+    }
+    ret = fdt_node_check_compatible(fdt_addr, phy_parent,
+                                    "cavium,octeon-3860-mdio");
+    if (ret == 0)
+    {
+        phy_info.direct_connect = 1 ;
+        uint32_t *mdio_reg_base = (uint32_t *) fdt_getprop(fdt_addr, phy_parent,"reg",0);
+        if (mdio_reg_base == 0)
+        {
+            cvmx_dprintf("ERROR : unable to get reg property in phy mdio\n");
+            return phy_info;
+        }
+        mdio_unit = __mdiobus_addr_to_unit(mdio_reg_base[1]);
+        //cvmx_dprintf("phy parent=%s reg_base=%08x unit=%d \n",
+        //             fdt_get_name(fdt_addr,phy_parent, NULL), mdio_reg_base[1], mdio_unit);
+    }
+    else
+    {
+        phy_info.direct_connect = 0;
+        /* The PHY is not directly connected to the Octeon MDIO bus.
+           SE doesn't  have abstractions for MDIO MUX or MDIO MUX drivers and
+           hence for the non direct cases code will be needed which is
+           board specific.
+           For now the the MDIO Unit is defaulted to 1.
+        */
+        mdio_unit = 1;
+    }
+
+    phy_addr_ptr = (uint32_t *) fdt_getprop(fdt_addr, phy, "reg", NULL);
+    phy_info.phy_addr = cvmx_be32_to_cpu(*phy_addr_ptr) | mdio_unit << 8;
+    return phy_info;
+
+}
+
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. The phy address is obtained from the device tree.
+ *
+ * @param ipd_port Octeon IPD port to get the MII address for.
+ *
+ * @return MII PHY address and bus number or -1.
+ */
+
+int cvmx_helper_board_get_mii_address_from_dt(int ipd_port)
+{
+        cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port);
+        return phy_info.phy_addr;
+}
+#endif
+
 /**
  * Return the MII PHY address associated with the given IPD
  * port. A result of -1 means there isn't a MII capable PHY
@@ -122,6 +368,16 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
     /*
      * For board types we can determine at runtime.
      */
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+        return -1;
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+    if (cvmx_sysinfo_get()->fdt_addr)
+    {
+        cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port);
+        //cvmx_dprintf("ipd_port=%d phy_addr=%d\n", ipd_port, phy_info.phy_addr);
+        if (phy_info.phy_addr >= 0) return phy_info.phy_addr;
+    }
+#endif
     switch (cvmx_sysinfo_get()->board_type)
     {
         case CVMX_BOARD_TYPE_SIM:
@@ -161,14 +417,6 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                 return 9;
             else
                 return -1;
-        case CVMX_BOARD_TYPE_NAC38:
-            /* Board has 8 RGMII ports PHYs are 0-7 */
-            if ((ipd_port >= 0) && (ipd_port < 4))
-                return ipd_port;
-            else if ((ipd_port >= 16) && (ipd_port < 20))
-                return ipd_port - 16 + 4;
-            else
-                return -1;
         case CVMX_BOARD_TYPE_EBH3000:
             /* Board has dual SPI4 and no PHYs */
             return -1;
@@ -241,6 +489,37 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                 return ipd_port + 1 + (1<<8);
             else
                 return -1;
+        case CVMX_BOARD_TYPE_EBB6800:
+            /* Board has 1 management ports */
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                return 6;
+            if (ipd_port >= 0x800 && ipd_port < 0x900) /* QLM 0*/
+                return 0x101 + ((ipd_port >> 4) & 3); /* SMI 1*/
+            if (ipd_port >= 0xa00 && ipd_port < 0xb00) /* QLM 2*/
+                return 0x201 + ((ipd_port >> 4) & 3); /* SMI 2*/
+            if (ipd_port >= 0xb00 && ipd_port < 0xc00) /* QLM 3*/
+                return 0x301 + ((ipd_port >> 4) & 3); /* SMI 3*/
+            if (ipd_port >= 0xc00 && ipd_port < 0xd00) /* QLM 4*/
+                return 0x001 + ((ipd_port >> 4) & 3); /* SMI 0*/
+            return -1;
+        case CVMX_BOARD_TYPE_EP6300C:
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                return 0x01;
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT+1)
+                return 0x02;
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+            {
+                int interface = cvmx_helper_get_interface_num(ipd_port);
+                int mode = cvmx_helper_interface_get_mode(interface);
+                if (mode == CVMX_HELPER_INTERFACE_MODE_XAUI)
+                    return ipd_port;
+                else if ((ipd_port >= 0) && (ipd_port < 4))
+                    return ipd_port + 3;
+                else
+                    return -1;
+            }
+#endif
+            break;
         case CVMX_BOARD_TYPE_CUST_NB5:
             if (ipd_port == 2)
                 return 4;
@@ -253,7 +532,20 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
             else
                 return -1;
         case CVMX_BOARD_TYPE_NIC_XLE_10G:
+        case CVMX_BOARD_TYPE_NIC10E:
             return -1;  /* We don't use clause 45 MDIO for anything */
+        case CVMX_BOARD_TYPE_NIC4E:
+            if (ipd_port >= 0 && ipd_port <= 3)
+                return (ipd_port + 0x1f) & 0x1f;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_NIC2E:
+            if (ipd_port >= 0 && ipd_port <= 1)
+                return (ipd_port + 1);
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_REDWING:
+	    return -1;  /* No PHYs connected to Octeon */
         case CVMX_BOARD_TYPE_BBGW_REF:
             return -1;  /* No PHYs are connected to Octeon, everything is through switch */
 	case CVMX_BOARD_TYPE_CUST_WSX16:
@@ -303,10 +595,329 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
 EXPORT_SYMBOL(cvmx_helper_board_get_mii_address);
 #endif
 
+/**
+ * @INTERNAL
+ * Get link state of marvell PHY
+ */
+static cvmx_helper_link_info_t __get_marvell_phy_link_state(int phy_addr)
+{
+    cvmx_helper_link_info_t  result;
+    int phy_status;
+
+    result.u64 = 0;
+    /*All the speed information can be read from register 17 in one go.*/
+    phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
+
+    /* If the resolve bit 11 isn't set, see if autoneg is turned off
+       (bit 12, reg 0). The resolve bit doesn't get set properly when
+       autoneg is off, so force it */
+    if ((phy_status & (1<<11)) == 0)
+    {
+        int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0);
+        if ((auto_status & (1<<12)) == 0)
+            phy_status |= 1<<11;
+    }
+
+    /* Only return a link if the PHY has finished auto negotiation
+       and set the resolved bit (bit 11) */
+    if (phy_status & (1<<11))
+    {
+        result.s.link_up = 1;
+        result.s.full_duplex = ((phy_status>>13)&1);
+        switch ((phy_status>>14)&3)
+        {
+            case 0: /* 10 Mbps */
+                result.s.speed = 10;
+                break;
+            case 1: /* 100 Mbps */
+                result.s.speed = 100;
+                break;
+            case 2: /* 1 Gbps */
+                result.s.speed = 1000;
+                break;
+            case 3: /* Illegal */
+                result.u64 = 0;
+                break;
+        }
+    }
+    return result;
+}
 
 /**
  * @INTERNAL
- * This function is the board specific method of determining an
+ * Get link state of broadcom PHY
+ */
+static cvmx_helper_link_info_t __get_broadcom_phy_link_state(int phy_addr)
+{
+    cvmx_helper_link_info_t  result;
+    int phy_status;
+
+    result.u64 = 0;
+    /* Below we are going to read SMI/MDIO register 0x19 which works
+       on Broadcom parts */
+    phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19);
+    switch ((phy_status>>8) & 0x7)
+    {
+        case 0:
+            result.u64 = 0;
+            break;
+        case 1:
+            result.s.link_up = 1;
+            result.s.full_duplex = 0;
+            result.s.speed = 10;
+            break;
+        case 2:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 10;
+            break;
+        case 3:
+            result.s.link_up = 1;
+            result.s.full_duplex = 0;
+            result.s.speed = 100;
+            break;
+        case 4:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 100;
+            break;
+        case 5:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 100;
+            break;
+        case 6:
+            result.s.link_up = 1;
+            result.s.full_duplex = 0;
+            result.s.speed = 1000;
+            break;
+        case 7:
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 1000;
+            break;
+    }
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Get link state using inband status
+ */
+static cvmx_helper_link_info_t __get_inband_link_state(int ipd_port)
+{
+    cvmx_helper_link_info_t  result;
+    cvmx_gmxx_rxx_rx_inbnd_t inband_status;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+    result.u64 = 0;
+    inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
+    result.s.link_up = inband_status.s.status;
+    result.s.full_duplex = inband_status.s.duplex;
+    switch (inband_status.s.speed)
+    {
+        case 0: /* 10 Mbps */
+            result.s.speed = 10;
+            break;
+        case 1: /* 100 Mbps */
+            result.s.speed = 100;
+            break;
+        case 2: /* 1 Gbps */
+            result.s.speed = 1000;
+            break;
+        case 3: /* Illegal */
+            result.u64 = 0;
+            break;
+    }
+    return result;
+}
+
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+/**
+ * @INTERNAL
+ * Switch MDIO mux to the specified port.
+ */
+static int __switch_mdio_mux(int ipd_port)
+{
+    /* This method is board specific and doesn't use the device tree
+       information as SE doesn't implement MDIO MUX abstration */
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+        case CVMX_BOARD_TYPE_EBB5600:
+        {
+            static unsigned char qlm_switch_addr = 0;
+            /* Board has 1 management port */
+            if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                return 0;
+            /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */
+            if ((ipd_port >= 0) && (ipd_port < 4))
+            {
+                if (qlm_switch_addr != 0x3)
+                {
+                    qlm_switch_addr = 0x3;  /* QLM1 */
+                    cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
+                    cvmx_wait_usec(11000); /* Let the write complete */
+                }
+                return ipd_port+1 + (1<<8);
+            }
+            else if ((ipd_port >= 16) && (ipd_port < 20))
+            {
+                if (qlm_switch_addr != 0xC)
+                {
+                    qlm_switch_addr = 0xC;  /* QLM3 */
+                    cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
+                    cvmx_wait_usec(11000); /* Let the write complete */
+                }
+                return ipd_port-16+1 + (1<<8);
+            }
+            else
+                return -1;
+        }
+        case CVMX_BOARD_TYPE_EBB6600:
+        {
+            static unsigned char qlm_switch_addr = 0;
+            int old_twsi_switch_reg;
+            /* Board has 2 management ports */
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
+                (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
+            if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */
+            {
+                if (qlm_switch_addr != 2)
+                {
+                    int tries;
+                    qlm_switch_addr = 2;
+                    tries = 3;
+                    do {
+                        old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0);
+                    } while (tries-- > 0 && old_twsi_switch_reg < 0);
+                    /* Set I2C MUX to enable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8);
+                    /* Set selecter to QLM 1 */
+                    cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xff);
+                    /* disable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg);
+                }
+                return 0x101 + ipd_port;
+            }
+            else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 1 */
+            {
+                if (qlm_switch_addr != 1)
+                {
+                    int tries;
+                    qlm_switch_addr = 1;
+                    tries = 3;
+                    do {
+                            old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0);
+                    } while (tries-- > 0 && old_twsi_switch_reg < 0);
+                    /* Set I2C MUX to enable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8);
+                    /* Set selecter to QLM 2 */
+                    cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xf7);
+                    /* disable port expander */
+                    cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg);
+                }
+                return 0x101 + (ipd_port - 16);
+            } else
+                return -1;
+        }
+        case CVMX_BOARD_TYPE_EBB6100:
+        {
+            static char gpio_configured = 0;
+
+            if (!gpio_configured)
+            {
+                cvmx_gpio_cfg(3, 1);
+                gpio_configured = 1;
+            }
+            /* Board has 2 management ports */
+            if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
+                (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
+            if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */
+            {
+                cvmx_gpio_set(1ull << 3);
+                return 0x101 + ipd_port;
+            }
+            else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 0 */
+            {
+                cvmx_gpio_clear(1ull << 3);
+                return 0x101 + (ipd_port - 16);
+            }
+            else
+            {
+                printf("%s: Unknown ipd port 0x%x\n", __func__, ipd_port);
+                return -1;
+            }
+        }
+        default:
+        {
+            cvmx_dprintf("ERROR : unexpected mdio switch for board=%08x\n",
+                         cvmx_sysinfo_get()->board_type);
+            return -1;
+        }
+    }
+    /* should never get here */
+    return -1;
+}
+
+/**
+ * @INTERNAL
+ * This function is used ethernet ports link speed. This functions uses the
+ * device tree information to determine the phy address and type of PHY.
+ * The only supproted PHYs are Marvell and Broadcom.
+ *
+ * @param ipd_port IPD input port associated with the port we want to get link
+ *                 status for.
+ *
+ * @return The ports link status. If the link isn't fully resolved, this must
+ *         return zero.
+ */
+
+cvmx_helper_link_info_t __cvmx_helper_board_link_get_from_dt(int ipd_port)
+{
+    cvmx_helper_link_info_t  result;
+    cvmx_phy_info_t phy_info;
+
+    result.u64 = 0;
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+    {
+        /* The simulator gives you a simulated 1Gbps full duplex link */
+        result.s.link_up = 1;
+        result.s.full_duplex = 1;
+        result.s.speed = 1000;
+        return result;
+    }
+    phy_info = __get_phy_info_from_dt(ipd_port);
+    //cvmx_dprintf("ipd_port=%d phy_addr=%d dc=%d type=%d \n", ipd_port,
+    //             phy_info.phy_addr, phy_info.direct_connect, phy_info.phy_type);
+    if (phy_info.phy_addr < 0) return result;
+
+    if (phy_info.direct_connect == 0)
+        __switch_mdio_mux(ipd_port);
+    switch(phy_info.phy_type)
+    {
+        case BROADCOM_GENERIC_PHY:
+            result = __get_broadcom_phy_link_state(phy_info.phy_addr);
+            break;
+        case MARVELL_GENERIC_PHY:
+            result = __get_marvell_phy_link_state(phy_info.phy_addr);
+            break;
+        default:
+            result = __get_inband_link_state(ipd_port);
+    }
+    return result;
+
+}
+#endif
+
+/**
+ * @INTERNAL
+ * This function invokes  __cvmx_helper_board_link_get_from_dt when device tree
+ * info is available. When the device tree information is not available then
+ * this function is the board specific method of determining an
  * ethernet ports link speed. Most Octeon boards have Marvell PHYs
  * and are handled by the fall through case. This function must be
  * updated for boards that don't have the normal Marvell PHYs.
@@ -329,6 +940,13 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
     int phy_addr;
     int is_broadcom_phy = 0;
 
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+    if (cvmx_sysinfo_get()->fdt_addr)
+    {
+        return __cvmx_helper_board_link_get_from_dt(ipd_port);
+    }
+#endif
+
     /* Give the user a chance to override the processing of this function */
     if (cvmx_override_board_link_get)
         return cvmx_override_board_link_get(ipd_port);
@@ -379,11 +997,16 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
             if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
                 is_broadcom_phy = 1;
             break;
+        case CVMX_BOARD_TYPE_EBB6100:
         case CVMX_BOARD_TYPE_EBB6300:   /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/
+        case CVMX_BOARD_TYPE_EBB6600:   /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/
             if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))
                 && cvmx_helper_board_get_mii_address(ipd_port) >= 0 && cvmx_helper_board_get_mii_address(ipd_port) <= 1)
                 is_broadcom_phy = 1;
             break;
+        case CVMX_BOARD_TYPE_EP6300C:
+            is_broadcom_phy = 1;
+            break;
         case CVMX_BOARD_TYPE_CUST_NB5:
             /* Port 1 on these boards is always Gigabit */
             if (ipd_port == 1)
@@ -412,6 +1035,9 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
                 result.s.speed = 1000;
                 return result;
             }
+        case CVMX_BOARD_TYPE_NIC4E:
+        case CVMX_BOARD_TYPE_NIC2E:
+            is_broadcom_phy = 1;
             break;
 	/* Private vendor-defined boards.  */
 #if defined(OCTEON_VENDOR_LANNER)
@@ -435,128 +1061,27 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
 #endif
 
     phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
+    //cvmx_dprintf("ipd_port=%d phy_addr=%d broadcom=%d\n",
+    //             ipd_port, phy_addr, is_broadcom_phy);
     if (phy_addr != -1)
     {
         if (is_broadcom_phy)
         {
-            /* Below we are going to read SMI/MDIO register 0x19 which works
-                on Broadcom parts */
-            int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19);
-            switch ((phy_status>>8) & 0x7)
-            {
-                case 0:
-                    result.u64 = 0;
-                    break;
-                case 1:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 0;
-                    result.s.speed = 10;
-                    break;
-                case 2:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 10;
-                    break;
-                case 3:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 0;
-                    result.s.speed = 100;
-                    break;
-                case 4:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 100;
-                    break;
-                case 5:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 100;
-                    break;
-                case 6:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 0;
-                    result.s.speed = 1000;
-                    break;
-                case 7:
-                    result.s.link_up = 1;
-                    result.s.full_duplex = 1;
-                    result.s.speed = 1000;
-                    break;
-            }
+            result =  __get_broadcom_phy_link_state(phy_addr);
         }
         else
         {
-            /* This code assumes we are using a Marvell Gigabit PHY. All the
-                speed information can be read from register 17 in one go. Somebody
-                using a different PHY will need to handle it above in the board
-                specific area */
-            int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
-
-            /* If the resolve bit 11 isn't set, see if autoneg is turned off
-                (bit 12, reg 0). The resolve bit doesn't get set properly when
-                autoneg is off, so force it */
-            if ((phy_status & (1<<11)) == 0)
-            {
-                int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0);
-                if ((auto_status & (1<<12)) == 0)
-                    phy_status |= 1<<11;
-            }
-
-            /* Only return a link if the PHY has finished auto negotiation
-                and set the resolved bit (bit 11) */
-            if (phy_status & (1<<11))
-            {
-#if defined(OCTEON_BOARD_CAPK_0100ND)
-                result.s.link_up = (phy_status>>10)&1;
-#else
-                result.s.link_up = 1;
-#endif
-                result.s.full_duplex = ((phy_status>>13)&1);
-                switch ((phy_status>>14)&3)
-                {
-                    case 0: /* 10 Mbps */
-                        result.s.speed = 10;
-                        break;
-                    case 1: /* 100 Mbps */
-                        result.s.speed = 100;
-                        break;
-                    case 2: /* 1 Gbps */
-                        result.s.speed = 1000;
-                        break;
-                    case 3: /* Illegal */
-                        result.u64 = 0;
-                        break;
-                }
-            }
+            /* This code assumes we are using a Marvell Gigabit PHY. */
+            result = __get_marvell_phy_link_state(phy_addr);
         }
     }
-    else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+    else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX)
+             || OCTEON_IS_MODEL(OCTEON_CN50XX))
     {
         /* We don't have a PHY address, so attempt to use in-band status. It is
             really important that boards not supporting in-band status never get
             here. Reading broken in-band status tends to do bad things */
-        cvmx_gmxx_rxx_rx_inbnd_t inband_status;
-        int interface = cvmx_helper_get_interface_num(ipd_port);
-        int index = cvmx_helper_get_interface_index_num(ipd_port);
-        inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
-
-        result.s.link_up = inband_status.s.status;
-        result.s.full_duplex = inband_status.s.duplex;
-        switch (inband_status.s.speed)
-        {
-            case 0: /* 10 Mbps */
-                result.s.speed = 10;
-                break;
-            case 1: /* 100 Mbps */
-                result.s.speed = 100;
-                break;
-            case 2: /* 1 Gbps */
-                result.s.speed = 1000;
-                break;
-            case 3: /* Illegal */
-                result.u64 = 0;
-                break;
-        }
+        result = __get_inband_link_state(ipd_port);
     }
     else
     {
@@ -638,7 +1163,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_
         cvmx_mdio_phy_reg_control_t reg_control;
         cvmx_mdio_phy_reg_status_t reg_status;
         cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
-        cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
         cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
 
         reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
@@ -650,7 +1174,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_
         reg_autoneg_adver.s.advert_100base_tx_half = 0;
         if (reg_status.s.capable_extended_status)
         {
-            reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
             reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000);
             reg_control_1000.s.advert_1000base_t_full = 0;
             reg_control_1000.s.advert_1000base_t_half = 0;
@@ -762,6 +1285,9 @@ int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
         case CVMX_BOARD_TYPE_EBT5810:
             return 1;  /* Two ports on each SPI: 1 hooked to MAC, 1 loopback
                        ** Loopback disabled by default. */
+        case CVMX_BOARD_TYPE_NIC2E:
+            if (interface == 0)
+                return 2;
 #if defined(OCTEON_VENDOR_LANNER)
 	case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
 	    if (interface == 1)
@@ -856,6 +1382,58 @@ int __cvmx_helper_board_hardware_enable(int interface)
  */
 cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
 {
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
+    const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr);
+    int nodeoffset;
+    const void *nodep;
+    int len;
+    uint32_t speed = 0;
+    const char *type = NULL;
+
+    if (fdt_addr)
+    {
+        nodeoffset = fdt_path_offset(fdt_addr, "/soc/uctl");
+        if (nodeoffset < 0)
+            nodeoffset = fdt_path_offset(fdt_addr, "/soc/usbn");
+
+        if (nodeoffset >= 0)
+        {
+            nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-type", &len);
+            if (nodep != NULL && len > 0)
+                type = (const char *)nodep;
+            else
+                type = "unknown";
+            nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-frequency", &len);
+            if (nodep != NULL && len == sizeof(uint32_t))
+                speed = fdt32_to_cpu(*(int *)nodep);
+            else
+                speed = 0;
+            if (!strcmp(type, "crystal"))
+            {
+                if (speed == 0 || speed == 12000000)
+                    return USB_CLOCK_TYPE_CRYSTAL_12;
+                else
+                    printf("Warning: invalid crystal speed for USB clock type in FDT\n");
+            }
+            else if (!strcmp(type, "external"))
+            {
+                switch (speed) {
+                case 12000000:
+                    return USB_CLOCK_TYPE_REF_12;
+                case 24000000:
+                    return USB_CLOCK_TYPE_REF_24;
+                case 0:
+                case 48000000:
+                    return USB_CLOCK_TYPE_REF_48;
+                default:
+                    printf("Warning: invalid USB clock speed of %u hz in FDT\n", speed);
+                }
+            }
+            else
+                printf("Warning: invalid USB reference clock type \"%s\" in FDT\n", type ? type : "NULL");
+        }
+    }
+#endif
     switch (cvmx_sysinfo_get()->board_type)
     {
         case CVMX_BOARD_TYPE_BBGW_REF:
@@ -869,8 +1447,16 @@ cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
 #if defined(OCTEON_BOARD_CAPK_0100ND)
 	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
 #endif
+        case CVMX_BOARD_TYPE_NIC10E_66:
             return USB_CLOCK_TYPE_CRYSTAL_12;
+        case CVMX_BOARD_TYPE_NIC10E:
+            return USB_CLOCK_TYPE_REF_12;
+        default:
+            break;
     }
+    if (OCTEON_IS_MODEL(OCTEON_CN6XXX)	/* Most boards except NIC10e use a 12MHz crystal */
+        || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
+        return USB_CLOCK_TYPE_CRYSTAL_12;
     return USB_CLOCK_TYPE_REF_48;
 }
 
@@ -892,6 +1478,7 @@ int __cvmx_helper_board_usb_get_num_ports(int supported_ports)
     switch (cvmx_sysinfo_get()->board_type)
     {
         case CVMX_BOARD_TYPE_NIC_XLE_4G:
+        case CVMX_BOARD_TYPE_NIC2E:
             return 0;
     }
 

sys/contrib/octeon-sdk/cvmx-helper-board.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,7 +49,7 @@
  * Helper functions to abstract board specific data about
  * network ports from the rest of the cvmx-helper files.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_BOARD_H__
 #define __CVMX_HELPER_BOARD_H__
@@ -66,6 +66,11 @@ typedef enum {
     USB_CLOCK_TYPE_CRYSTAL_12,
 } cvmx_helper_board_usb_clock_types_t;
 
+typedef enum {
+    BROADCOM_GENERIC_PHY,
+    MARVELL_GENERIC_PHY,
+} cvmx_phy_type_t;
+
 typedef enum {
     set_phy_link_flags_autoneg                  = 0x1,
     set_phy_link_flags_flow_control_dont_touch  = 0x0 << 1,

sys/contrib/octeon-sdk/cvmx-helper-cfg.c

@@ -0,0 +1,717 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper Functions for the Configuration Framework
+ *
+ * <hr>$Revision: 0 $<hr>
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-util.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
+#include <asm/octeon/cvmx-helper-ilk.h>
+#include <asm/octeon/cvmx-ilk.h>
+#include <asm/octeon/cvmx-config.h>
+#else
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-ilk.h"
+#include "cvmx-helper-ilk.h"
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "cvmx-config.h"
+#include "executive-config.h"
+#endif
+#endif
+
+#if defined(min)
+#else
+#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
+#endif
+
+/* #define CVMX_HELPER_CFG_DEBUG */
+
+/*
+ * Per physical port
+ */
+struct cvmx_cfg_port_param {
+	int8_t	ccpp_pknd;
+	int8_t	ccpp_bpid;
+	int8_t	ccpp_pko_port_base;
+	int8_t	ccpp_pko_num_ports;
+	uint8_t	ccpp_pko_nqueues;	/*
+					 * When the user explicitly
+					 * assigns queues,
+					 * cvmx_cfg_pko_nqueue_pool[
+					 *     ccpp_pko_nqueues ... 
+					 *     ccpp_pko_nqueues + 
+					 *     ccpp_pko_num_ports - 1]
+					 * are the numbers of PKO queues
+					 * assigned to the PKO ports for
+					 * this physical port.
+					 */
+};
+
+/*
+ * Per pko_port
+ */
+struct cvmx_cfg_pko_port_param {
+	int16_t	ccppp_queue_base;
+	int16_t	ccppp_num_queues;
+};
+
+/*
+ * A map from pko_port to
+ *     interface,
+ *     index, and
+ *     pko engine id
+ */
+struct cvmx_cfg_pko_port_map {
+	int16_t ccppl_interface;
+	int16_t ccppl_index;
+	int16_t ccppl_eid;
+};
+
+/*
+ * This is for looking up pko_base_port and pko_nport for ipd_port
+ */
+struct cvmx_cfg_pko_port_pair {
+	int8_t ccppp_base_port;
+	int8_t ccppp_nports;
+};
+
+static CVMX_SHARED struct cvmx_cfg_port_param cvmx_cfg_port
+    [CVMX_HELPER_CFG_MAX_IFACE][CVMX_HELPER_CFG_MAX_PORT_PER_IFACE] =
+    {[0 ... CVMX_HELPER_CFG_MAX_IFACE - 1] =
+        {[0 ... CVMX_HELPER_CFG_MAX_PORT_PER_IFACE - 1] =
+            {CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE,
+    	     CVMX_HELPER_CFG_INVALID_VALUE}}};
+
+/*
+ * Indexed by the pko_port number
+ */
+static CVMX_SHARED struct cvmx_cfg_pko_port_param cvmx_cfg_pko_port
+    [CVMX_HELPER_CFG_MAX_PKO_PORT] =
+    {[0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] =
+        {CVMX_HELPER_CFG_INVALID_VALUE,
+	 CVMX_HELPER_CFG_INVALID_VALUE}};
+
+static CVMX_SHARED struct cvmx_cfg_pko_port_map cvmx_cfg_pko_port_map
+    [CVMX_HELPER_CFG_MAX_PKO_PORT] = 
+        {[0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] =
+            {CVMX_HELPER_CFG_INVALID_VALUE,
+	     CVMX_HELPER_CFG_INVALID_VALUE,
+             CVMX_HELPER_CFG_INVALID_VALUE}};
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/*
+ * This array assists translation from ipd_port to pko_port.
+ * The ``16'' is the rounded value for the 3rd 4-bit value of
+ * ipd_port, used to differentiate ``interfaces.''
+ */
+static CVMX_SHARED struct cvmx_cfg_pko_port_pair ipd2pko_port_cache[16]
+    [CVMX_HELPER_CFG_MAX_PORT_PER_IFACE] =
+    {[0 ... 15] = 
+        {[0 ... CVMX_HELPER_CFG_MAX_PORT_PER_IFACE - 1] =
+	    {CVMX_HELPER_CFG_INVALID_VALUE,
+	     CVMX_HELPER_CFG_INVALID_VALUE}}};
+
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+
+static CVMX_SHARED int cvmx_cfg_default_pko_nqueues = 1;
+
+/*
+ * A pool for holding the pko_nqueues for the pko_ports assigned to a
+ * physical port.
+ */
+static CVMX_SHARED uint8_t cvmx_cfg_pko_nqueue_pool
+    [CVMX_HELPER_CFG_MAX_PKO_QUEUES] = 
+    {[0 ... CVMX_HELPER_CFG_MAX_PKO_QUEUES - 1] = 1};
+
+#endif
+#endif
+
+/*
+ * Options
+ *
+ * Each array-elem's intial value is also the option's default value.
+ */
+static CVMX_SHARED uint64_t cvmx_cfg_opts[CVMX_HELPER_CFG_OPT_MAX] =
+    {[0 ... CVMX_HELPER_CFG_OPT_MAX - 1] = 1};
+
+/*
+ * MISC
+ */
+static CVMX_SHARED int cvmx_cfg_max_pko_engines; /* # of PKO DMA engines 
+						    allocated */
+int __cvmx_helper_cfg_pknd(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_pknd;
+}
+
+int __cvmx_helper_cfg_bpid(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_bpid;
+}
+
+int __cvmx_helper_cfg_pko_port_base(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_pko_port_base;
+}
+
+int __cvmx_helper_cfg_pko_port_num(int interface, int index)
+{
+    return cvmx_cfg_port[interface][index].ccpp_pko_num_ports;
+}
+
+int __cvmx_helper_cfg_pko_queue_num(int pko_port)
+{
+    return cvmx_cfg_pko_port[pko_port].ccppp_num_queues;
+}
+
+int __cvmx_helper_cfg_pko_queue_base(int pko_port)
+{
+    return cvmx_cfg_pko_port[pko_port].ccppp_queue_base;
+}
+
+int __cvmx_helper_cfg_pko_max_queue(void)
+{
+    int i;
+
+    i = CVMX_HELPER_CFG_MAX_PKO_PORT - 1;
+
+    while (i >= 0)
+    {
+        if (cvmx_cfg_pko_port[i].ccppp_queue_base !=
+	    CVMX_HELPER_CFG_INVALID_VALUE)
+	{
+	    cvmx_helper_cfg_assert(cvmx_cfg_pko_port[i].ccppp_num_queues > 0);
+	    return (cvmx_cfg_pko_port[i].ccppp_queue_base +
+	        cvmx_cfg_pko_port[i].ccppp_num_queues);
+	}
+	i --;
+    }
+
+    cvmx_helper_cfg_assert(0); /* shouldn't get here */
+    
+    return 0;
+}
+
+int __cvmx_helper_cfg_pko_max_engine(void)
+{
+    return cvmx_cfg_max_pko_engines;
+}
+
+int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, uint64_t val)
+{
+    if (opt >= CVMX_HELPER_CFG_OPT_MAX)
+        return -1;
+    
+    cvmx_cfg_opts[opt] = val;
+
+    return 0;
+}
+
+uint64_t cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt)
+{
+    if (opt >= CVMX_HELPER_CFG_OPT_MAX)
+        return (uint64_t)CVMX_HELPER_CFG_INVALID_VALUE;
+
+    return cvmx_cfg_opts[opt];
+}
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+EXPORT_SYMBOL(__cvmx_helper_cfg_init);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pknd);
+EXPORT_SYMBOL(__cvmx_helper_cfg_bpid);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_base);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_num);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_queue_base);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_queue_num);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_max_queue);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_interface);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_index);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_port_eid);
+EXPORT_SYMBOL(__cvmx_helper_cfg_pko_max_engine);
+EXPORT_SYMBOL(cvmx_helper_cfg_opt_get);
+EXPORT_SYMBOL(cvmx_helper_cfg_opt_set);
+EXPORT_SYMBOL(cvmx_helper_cfg_ipd2pko_port_base);
+EXPORT_SYMBOL(cvmx_helper_cfg_ipd2pko_port_num);
+#endif
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+
+#ifdef CVMX_HELPER_CFG_DEBUG
+void cvmx_helper_cfg_show_cfg(void)
+{
+    int i, j;
+
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	cvmx_dprintf(
+	    "cvmx_helper_cfg_show_cfg: interface%d mode %10s nports%4d\n", i,
+	    cvmx_helper_interface_mode_to_string(cvmx_helper_interface_get_mode(i)),
+	    cvmx_helper_interface_enumerate(i));
+
+	for (j = 0; j < cvmx_helper_interface_enumerate(i); j++)
+	{
+	    cvmx_dprintf("\tpknd[%i][%d]%d", i, j,
+	        __cvmx_helper_cfg_pknd(i, j));
+	    cvmx_dprintf(" pko_port_base[%i][%d]%d", i, j,
+	        __cvmx_helper_cfg_pko_port_base(i, j));
+	    cvmx_dprintf(" pko_port_num[%i][%d]%d\n", i, j,
+	        __cvmx_helper_cfg_pko_port_num(i, j));
+	}
+    }
+
+    for (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)
+    {
+	if (__cvmx_helper_cfg_pko_queue_base(i) !=
+	    CVMX_HELPER_CFG_INVALID_VALUE)
+	{
+            cvmx_dprintf("cvmx_helper_cfg_show_cfg: pko_port%d qbase%d nqueues%d "
+	        "interface%d index%d\n", i,
+		__cvmx_helper_cfg_pko_queue_base(i),
+		__cvmx_helper_cfg_pko_queue_num(i),
+		__cvmx_helper_cfg_pko_port_interface(i),
+		__cvmx_helper_cfg_pko_port_index(i));
+        }
+    }
+}
+#endif
+
+/*
+ * initialize cvmx_cfg_pko_port_map
+ */
+static void cvmx_helper_cfg_init_pko_port_map(void)
+{
+    int i, j, k;
+    int pko_eid;
+    int pko_port_base, pko_port_max;
+    cvmx_helper_interface_mode_t mode;
+
+    /*
+     * one pko_eid is allocated to each port except for ILK, NPI, and
+     * LOOP. Each of the three has one eid.
+     */
+    pko_eid = 0;
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	mode = cvmx_helper_interface_get_mode(i);
+        for (j = 0; j < cvmx_helper_interface_enumerate(i); j++)
+	{
+	    pko_port_base = cvmx_cfg_port[i][j].ccpp_pko_port_base;
+	    pko_port_max = pko_port_base +
+	        cvmx_cfg_port[i][j].ccpp_pko_num_ports;
+	    cvmx_helper_cfg_assert(pko_port_base !=
+	        CVMX_HELPER_CFG_INVALID_VALUE);
+	    cvmx_helper_cfg_assert(pko_port_max >= pko_port_base);
+	    for (k = pko_port_base; k < pko_port_max; k++)
+	    {
+	        cvmx_cfg_pko_port_map[k].ccppl_interface = i;
+	        cvmx_cfg_pko_port_map[k].ccppl_index = j;
+	        cvmx_cfg_pko_port_map[k].ccppl_eid = pko_eid;
+	    }
+
+#if 0
+	    /*
+	     * For a physical port that is not configured a PKO port,
+	     * pko_port_base here equals to pko_port_max. In this
+	     * case, the physical port does not take a DMA engine.
+	     */
+	    if (pko_port_base > pko_port_max)
+#endif
+	        if (!(mode == CVMX_HELPER_INTERFACE_MODE_NPI ||
+	            mode == CVMX_HELPER_INTERFACE_MODE_LOOP ||
+	            mode == CVMX_HELPER_INTERFACE_MODE_ILK))
+	            pko_eid ++;
+	}
+
+	if (mode == CVMX_HELPER_INTERFACE_MODE_NPI ||
+	    mode == CVMX_HELPER_INTERFACE_MODE_LOOP ||
+	    mode == CVMX_HELPER_INTERFACE_MODE_ILK)
+	        pko_eid ++;
+    }
+
+    /*
+     * Legal pko_eids [0, 0x13] should not be exhausted.
+     */
+    cvmx_helper_cfg_assert(pko_eid <= 0x14);
+
+    cvmx_cfg_max_pko_engines = pko_eid;
+}
+#endif
+
+int __cvmx_helper_cfg_pko_port_interface(int pko_port)
+{
+    return cvmx_cfg_pko_port_map[pko_port].ccppl_interface;
+}
+
+int __cvmx_helper_cfg_pko_port_index(int pko_port)
+{
+    return cvmx_cfg_pko_port_map[pko_port].ccppl_index;
+}
+
+int __cvmx_helper_cfg_pko_port_eid(int pko_port)
+{
+    return cvmx_cfg_pko_port_map[pko_port].ccppl_eid;
+}
+
+/**
+ * Perform common init tasks for all chips.
+ * @return 1 for the caller to continue init and 0 otherwise.
+ *
+ * Note: ``common'' means this function is executed regardless of
+ * 	- chip, and
+ * 	- CVMX_ENABLE_HELPER_FUNCTIONS.
+ *
+ * This function decides based on these conditions if the
+ * configuration stage of the init process should continue.
+ *
+ * This is only meant to be called by __cvmx_helper_cfg_init().
+ */
+static int __cvmx_helper_cfg_init_common(void)
+{
+    int val;
+
+#ifndef CVMX_ENABLE_HELPER_FUNCTIONS
+    val = 0;
+#else
+    val = (octeon_has_feature(OCTEON_FEATURE_PKND));
+#endif
+
+    return val;
+}
+
+#define IPD2PKO_CACHE_Y(ipd_port)	(ipd_port) >> 8
+#define IPD2PKO_CACHE_X(ipd_port)	(ipd_port) & 0xff
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/*
+ * ipd_port to pko_port translation cache
+ */
+static int __cvmx_helper_cfg_init_ipd2pko_cache(void)
+{
+    int i, j, n;
+    int ipd_y, ipd_x, ipd_port;
+
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	n = cvmx_helper_interface_enumerate(i);
+    
+        for (j = 0; j < n; j++)
+	{
+	    ipd_port = cvmx_helper_get_ipd_port(i, j);
+	    ipd_y = IPD2PKO_CACHE_Y(ipd_port);
+	    ipd_x = IPD2PKO_CACHE_X(ipd_port);
+	    ipd2pko_port_cache[ipd_y]
+	        [(ipd_port & 0x800) ? ((ipd_x >> 4) & 3) : ipd_x] = 
+		(struct cvmx_cfg_pko_port_pair)
+		{__cvmx_helper_cfg_pko_port_base(i, j),
+		 __cvmx_helper_cfg_pko_port_num(i, j)};
+	}
+    }
+
+    return 0;
+}
+
+int cvmx_helper_cfg_ipd2pko_port_base(int ipd_port)
+{
+	int ipd_y, ipd_x;
+
+        ipd_y = IPD2PKO_CACHE_Y(ipd_port);
+	ipd_x = IPD2PKO_CACHE_X(ipd_port);
+
+        return ipd2pko_port_cache[ipd_y]
+	    [(ipd_port & 0x800) ? ((ipd_x >> 4) & 3) : ipd_x].ccppp_base_port;
+}
+
+int cvmx_helper_cfg_ipd2pko_port_num(int ipd_port)
+{
+	int ipd_y, ipd_x;
+
+        ipd_y = IPD2PKO_CACHE_Y(ipd_port);
+	ipd_x = IPD2PKO_CACHE_X(ipd_port);
+
+        return ipd2pko_port_cache[ipd_y]
+	    [(ipd_port & 0x800) ? ((ipd_x >> 4) & 3) : ipd_x].ccppp_nports;
+}
+#endif
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+/**
+ * Return the number of queues assigned to this pko_port by user
+ *
+ * @param pko_port
+ * @return the number of queues for this pko_port
+ *
+ * Note: Called after the pko_port map is set up.
+ */
+static int __cvmx_ucfg_nqueues(int pko_port)
+{
+    int interface, index;
+    int i, k;
+
+    interface = __cvmx_helper_cfg_pko_port_interface(pko_port);
+    index = __cvmx_helper_cfg_pko_port_index(pko_port);
+
+    /*
+     * pko_port belongs to no physical port,
+     * don't assign a queue to it.
+     */
+    if (interface == CVMX_HELPER_CFG_INVALID_VALUE ||
+        index == CVMX_HELPER_CFG_INVALID_VALUE)
+	return 0;
+
+    /*
+     * Assign the default number of queues to those pko_ports not
+     * assigned explicitly.
+     */
+    i = cvmx_cfg_port[interface][index].ccpp_pko_nqueues;
+    if (i == (uint8_t)CVMX_HELPER_CFG_INVALID_VALUE)
+        return cvmx_cfg_default_pko_nqueues;
+
+    /*
+     * The user has assigned nqueues to this pko_port,
+     * recorded in the pool.
+     */
+    k = pko_port - cvmx_cfg_port[interface][index].ccpp_pko_port_base;
+    cvmx_helper_cfg_assert(k < 
+        cvmx_cfg_port[interface][index].ccpp_pko_num_ports);
+    return cvmx_cfg_pko_nqueue_pool[i + k];
+}
+
+#else
+
+/**
+ * Return the number of queues to be assigned to this pko_port
+ *
+ * @param pko_port
+ * @return the number of queues for this pko_port
+ *
+ * Note: This function exists for backward compatibility.
+ * CVMX_PKO_QUEUES_PER_PORT_XXXX defines no of queues per HW port.
+ * pko_port is equivalent in pre-o68 SDK.
+ */
+static int cvmx_helper_cfg_dft_nqueues(int pko_port)
+{
+    cvmx_helper_interface_mode_t mode;
+    int interface;
+    int n;
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE2
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE2 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE3
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE3 1
+#endif
+
+#ifndef CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE4
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE4 1
+#endif
+
+    n = 1;
+    interface = __cvmx_helper_cfg_pko_port_interface(pko_port);
+    if (interface == 0)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE0
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
+#endif
+    }
+    if (interface == 1)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE1
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
+#endif
+    }
+
+    if (interface == 2)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE2
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE2;
+#endif
+    }
+    if (interface == 3)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE3
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE3;
+#endif
+    }
+    if (interface == 4)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_INTERFACE4
+	n = CVMX_PKO_QUEUES_PER_PORT_INTERFACE4;
+#endif
+    }
+
+    mode = cvmx_helper_interface_get_mode(interface);
+    if (mode == CVMX_HELPER_INTERFACE_MODE_LOOP)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_LOOP
+	n = CVMX_PKO_QUEUES_PER_PORT_LOOP;
+#endif
+    }
+    if (mode == CVMX_HELPER_INTERFACE_MODE_NPI)
+    {
+#ifdef CVMX_PKO_QUEUES_PER_PORT_PCI
+	n = CVMX_PKO_QUEUES_PER_PORT_PCI;
+#endif
+    }
+
+    return n;
+}
+#endif /* CVMX_USER_DEFINED_HELPER_CONFIG_INIT */
+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
+
+int __cvmx_helper_cfg_init(void)
+{
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+    struct cvmx_cfg_port_param *pport;
+    int cvmx_cfg_default_pko_nports;
+    int pknd, bpid, pko_port_base;
+    int qbase;
+    int i, j, n;
+
+    cvmx_cfg_default_pko_nports = 1;
+#endif
+    
+    if (!__cvmx_helper_cfg_init_common())
+        return 0;
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+{
+	int cvmx_ucfg_nq;
+	cvmx_ucfg_nq = 0;
+#include "cvmx-helper-cfg-init.c"
+}
+#endif
+
+    /*
+     * per-port parameters
+     */
+    pknd = 0;
+    bpid = 0;
+    pko_port_base = 0;
+    
+    for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++)
+    {
+	n = cvmx_helper_interface_enumerate(i);
+    
+        pport = cvmx_cfg_port[i];
+        for (j = 0; j < n; j++, pport++)
+	{
+	    int t;
+
+	    t = cvmx_cfg_default_pko_nports;
+	    if (pport->ccpp_pko_num_ports != CVMX_HELPER_CFG_INVALID_VALUE)
+	        t = pport->ccpp_pko_num_ports;
+
+            *pport = (struct cvmx_cfg_port_param) {
+		pknd++,
+		bpid++,
+		pko_port_base,
+		t,
+	        pport->ccpp_pko_nqueues};
+	    pko_port_base += t;
+	}
+    }
+    
+    cvmx_helper_cfg_assert(pknd <= CVMX_HELPER_CFG_MAX_PIP_PKND);
+    cvmx_helper_cfg_assert(bpid <= CVMX_HELPER_CFG_MAX_PIP_BPID);
+    cvmx_helper_cfg_assert(pko_port_base <= CVMX_HELPER_CFG_MAX_PKO_PORT);
+    
+    /*
+     * pko_port map
+     */
+    cvmx_helper_cfg_init_pko_port_map();
+
+    /*
+     * per-pko_port parameters
+     */
+    qbase = 0;
+    for (i = 0; i < pko_port_base; i++)
+    {
+#ifdef CVMX_USER_DEFINED_HELPER_CONFIG_INIT
+	n = __cvmx_ucfg_nqueues(i);
+#else
+	n = cvmx_helper_cfg_dft_nqueues(i);
+#endif
+	cvmx_cfg_pko_port[i] = (struct cvmx_cfg_pko_port_param) {qbase, n};
+	qbase += n;
+	cvmx_helper_cfg_assert(qbase <= CVMX_HELPER_CFG_MAX_PKO_QUEUES);
+    }
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+    __cvmx_helper_cfg_init_ipd2pko_cache();
+#endif
+
+#ifdef CVMX_HELPER_CFG_DEBUG
+    cvmx_helper_cfg_show_cfg();
+#endif /* CVMX_HELPER_CFG_DEBUG */
+#endif
+    return 0;
+}

sys/contrib/octeon-sdk/cvmx-helper-cfg.h

@@ -0,0 +1,282 @@
+/***********************license start***************
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Helper Functions for the Configuration Framework
+ *
+ * OCTEON_CN68XX introduces a flexible hw interface configuration
+ * scheme. To cope with this change and the requirements of
+ * configurability for other system resources, e.g., IPD/PIP pknd and
+ * PKO ports and queues, a configuration framework for the SDK is
+ * designed. It has two goals: first to recognize and establish the
+ * default configuration and, second, to allow the user to define key
+ * parameters in a high-level language.
+ *
+ * The helper functions query the QLM setup to help achieving the
+ * first goal.
+ *
+ * The second goal is accomplished by generating
+ * cvmx_helper_cfg_init() from a high-level lanaguage.
+ *
+ * <hr>$Revision: 0 $<hr>
+ */
+
+#ifndef __CVMX_HELPER_CFG_H__
+#define __CVMX_HELPER_CFG_H__
+
+#define CVMX_HELPER_CFG_MAX_IFACE		9
+#define CVMX_HELPER_CFG_MAX_PKO_PORT		128
+#define CVMX_HELPER_CFG_MAX_PIP_BPID       	64
+#define CVMX_HELPER_CFG_MAX_PIP_PKND       	64
+#define CVMX_HELPER_CFG_MAX_PKO_QUEUES     	256
+#define CVMX_HELPER_CFG_MAX_PORT_PER_IFACE 	256
+
+#define CVMX_HELPER_CFG_INVALID_VALUE		-1	/* The default return 
+						   	 * value upon failure
+							 */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define cvmx_helper_cfg_assert(cond)					\
+	do {								\
+	    if (!(cond))						\
+	    {								\
+	        cvmx_dprintf("cvmx_helper_cfg_assert (%s) at %s:%d\n",	\
+		    #cond, __FILE__, __LINE__);				\
+	    }								\
+	} while (0)
+
+/*
+ * Config Options
+ *
+ * These options have to be set via cvmx_helper_cfg_opt_set() before calling the
+ * routines that set up the hw. These routines process the options and set them
+ * correctly to take effect at runtime. 
+ */
+enum cvmx_helper_cfg_option {
+	CVMX_HELPER_CFG_OPT_USE_DWB, /*
+				      * Global option to control if
+				      * the SDK configures units (DMA,
+				      * SSO, and PKO) to send don't
+				      * write back (DWB) requests for
+				      * freed buffers. Set to 1/0 to
+				      * enable/disable DWB.
+				      *
+				      * For programs that fit inside
+				      * L2, sending DWB just causes
+				      * more L2 operations without
+				      * benefit.
+	                              */
+
+	CVMX_HELPER_CFG_OPT_MAX
+};
+typedef enum cvmx_helper_cfg_option cvmx_helper_cfg_option_t;
+
+/*
+ * @INTERNAL
+ * Return configured pknd for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the pknd
+ */
+extern int __cvmx_helper_cfg_pknd(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured bpid for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the bpid
+ */
+extern int __cvmx_helper_cfg_bpid(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured pko_port base for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the pko_port base
+ */
+extern int __cvmx_helper_cfg_pko_port_base(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured number of pko_ports for the port
+ *
+ * @param interface the interface number
+ * @param index the port's index number
+ * @return the number of pko_ports
+ */
+extern int __cvmx_helper_cfg_pko_port_num(int interface, int index);
+
+/*
+ * @INTERNAL
+ * Return the configured pko_queue base for the pko_port
+ *
+ * @param pko_port
+ * @return the pko_queue base
+ */
+extern int __cvmx_helper_cfg_pko_queue_base(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the configured number of pko_queues for the pko_port
+ *
+ * @param pko_port
+ * @return the number of pko_queues
+ */
+extern int __cvmx_helper_cfg_pko_queue_num(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the interface the pko_port is configured for
+ *
+ * @param pko_port
+ * @return the interface for the pko_port
+ */
+extern int __cvmx_helper_cfg_pko_port_interface(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the index of the port the pko_port is configured for
+ *
+ * @param pko_port
+ * @return the index of the port
+ */
+extern int __cvmx_helper_cfg_pko_port_index(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the pko_eid of the pko_port
+ *
+ * @param pko_port
+ * @return the pko_eid
+ */
+extern int __cvmx_helper_cfg_pko_port_eid(int pko_port);
+
+/*
+ * @INTERNAL
+ * Return the max# of pko queues allocated.
+ *
+ * @return the max# of pko queues
+ *
+ * Note: there might be holes in the queue space depending on user
+ * configuration. The function returns the highest queue's index in
+ * use.
+ */
+extern int __cvmx_helper_cfg_pko_max_queue(void);
+
+/*
+ * @INTERNAL
+ * Return the max# of PKO DMA engines allocated.
+ *
+ * @return the max# of DMA engines
+ *
+ * NOTE: the DMA engines are allocated contiguously and starting from
+ * 0.
+ */
+extern int __cvmx_helper_cfg_pko_max_engine(void);
+
+/*
+ * Get the value set for the config option ``opt''.
+ *
+ * @param opt is the config option.
+ * @return the value set for the option
+ */
+extern uint64_t cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt);
+
+/*
+ * Set the value for a config option.
+ *
+ * @param opt is the config option.
+ * @param val is the value to set for the opt.
+ * @return 0 for success and -1 on error
+ *
+ * Note an option here is a config-time parameter and this means that
+ * it has to be set before calling the corresponding setup functions
+ * that actually sets the option in hw.
+ */
+extern int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, uint64_t val);
+
+/*
+ * Retrieve the pko_port base given ipd_port.
+ *
+ * @param ipd_port is the IPD eport
+ * @return the corresponding PKO port base for the physical port
+ * represented by the IPD eport or CVMX_HELPER_CFG_INVALID_VALUE.
+ */
+extern int cvmx_helper_cfg_ipd2pko_port_base(int ipd_port);
+
+/*
+ * Retrieve the number of pko_ports given ipd_port.
+ *
+ * @param ipd_port is the IPD eport
+ * @return the corresponding number of PKO ports for the physical port 
+ *  represented by IPD eport or CVMX_HELPER_CFG_INVALID_VALUE.
+ */
+extern int cvmx_helper_cfg_ipd2pko_port_num(int ipd_port);
+
+/*
+ * @INTERNAL
+ * The init function
+ *
+ * @param none
+ * @return 0 for success.
+ *
+ * Note: this function is meant to be called to set the ``configured
+ * parameters,'' e.g., pknd, bpid, etc. and therefore should be before
+ * any of the corresponding cvmx_helper_cfg_xxxx() functions are
+ * called.
+ */
+
+extern int __cvmx_helper_cfg_init(void);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_HELPER_CFG_H__ */

sys/contrib/octeon-sdk/cvmx-helper-check-defines.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * function properly. It either supplies a default or fails
  * compile if a define is incorrect.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_CHECK_DEFINES_H__
 #define __CVMX_HELPER_CHECK_DEFINES_H__

sys/contrib/octeon-sdk/cvmx-helper-errata.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * chip errata. For the most part, code doesn't need to call
  * these functions directly.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 #include <asm/octeon/cvmx.h>
@@ -106,7 +106,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
     cvmx_gmxx_prtx_cfg_t gmx_cfg;
     int retry_cnt;
     int retry_loop_cnt;
-    int mtu;
     int i;
     cvmx_helper_link_info_t link_info;
 
@@ -195,7 +194,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
         cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
         cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
 
-        mtu = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
         cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
         cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
 
@@ -304,6 +302,12 @@ int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
 void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
 {
     int lane;
+    /* Apply the workaround only once. */
+    cvmx_ciu_qlm_jtgd_t qlm_jtgd;
+    qlm_jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+    if (qlm_jtgd.s.select != 0)
+        return;
+
     cvmx_helper_qlm_jtag_init();
     /* We need to load all four lanes of the QLM, a total of 1072 bits */
     for (lane=0; lane<4; lane++)

sys/contrib/octeon-sdk/cvmx-helper-errata.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -51,7 +51,7 @@
  * chip errata. For the most part, code doesn't need to call
  * these functions directly.
  *
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_ERRATA_H__
 #define __CVMX_HELPER_ERRATA_H__

sys/contrib/octeon-sdk/cvmx-helper-fpa.c

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Helper functions for FPA setup.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #include "cvmx.h"
 #include "cvmx-bootmem.h"

sys/contrib/octeon-sdk/cvmx-helper-fpa.h

@@ -1,5 +1,5 @@
 /***********************license start***************
- * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
  * reserved.
  *
  *
@@ -15,7 +15,7 @@
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
 
- *   * Neither the name of Cavium Networks nor the names of
+ *   * Neither the name of Cavium Inc. nor the names of
  *     its contributors may be used to endorse or promote products
  *     derived from this software without specific prior written
  *     permission.
@@ -26,7 +26,7 @@
  * countries.
 
  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
  *
  * Helper functions for FPA setup.
  *
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
  */
 #ifndef __CVMX_HELPER_H_FPA__
 #define __CVMX_HELPER_H_FPA__

sys/contrib/octeon-sdk/cvmx-helper-ilk.c

@@ -0,0 +1,442 @@
+/***********************license start***************
+ * Copyright (c) 2010  Cavium Inc. (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+
+ *   * Neither the name of Cavium Inc. nor the names of
+ *     its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written
+ *     permission.
+
+ * This Software, including technical data, may be subject to U.S. export  control
+ * laws, including the U.S. Export Administration Act and its  associated
+ * regulations, and may be subject to export or import  regulations in other
+ * countries.
+
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
+ * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
+ * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for ILK initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#include <linux/module.h>
+
+#include <asm/octeon/cvmx.h>
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
+#include <asm/octeon/cvmx-ilk.h>
+#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-qlm.h>
+#include <asm/octeon/cvmx-ilk-defs.h>
+#else
+#if !defined(__FreeBSD__) || !defined(_KERNEL)
+#include "executive-config.h"
+#include "cvmx-config.h"
+#endif
+#include "cvmx.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-ilk.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-pko.h"
+#include "cvmx-qlm.h"
+#endif
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+int __cvmx_helper_ilk_enumerate(int interface)
+{
+    interface -= CVMX_ILK_GBL_BASE;
+    return cvmx_ilk_chans[interface];
+}
+
+/**
+ * @INTERNAL
+ * Probe a ILK interface and determine the number of ports
+ * connected to it. The ILK interface should still be down
+ * after this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_ilk_probe(int interface)
+{
+    int i, j, res = -1;
+    static int pipe_base = 0, pknd_base = 0;
+    static cvmx_ilk_pipe_chan_t *pch = NULL, *tmp;
+    static cvmx_ilk_chan_pknd_t *chpknd = NULL, *tmp1;
+    static cvmx_ilk_cal_entry_t *calent = NULL, *tmp2;
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+        return 0;
+
+    interface -= CVMX_ILK_GBL_BASE;
+    if (interface >= CVMX_NUM_ILK_INTF)
+        return 0;
+
+    /* the configuration should be done only once */
+    if (cvmx_ilk_get_intf_ena (interface))
+        return cvmx_ilk_chans[interface];
+
+    /* configure lanes and enable the link */
+    res = cvmx_ilk_start_interface (interface, cvmx_ilk_lane_mask[interface]);
+    if (res < 0)
+        return 0;
+
+    /* set up the group of pipes available to ilk */
+    if (pipe_base == 0)
+        pipe_base = __cvmx_pko_get_pipe (interface + CVMX_ILK_GBL_BASE, 0);
+
+    if (pipe_base == -1)
+    {
+        pipe_base = 0;
+        return 0;
+    }
+
+    res = cvmx_ilk_set_pipe (interface, pipe_base, cvmx_ilk_chans[interface]);
+    if (res < 0)
+        return 0;
+
+    /* set up pipe to channel mapping */
+    i = pipe_base;
+    if (pch == NULL)
+    {
+        pch = (cvmx_ilk_pipe_chan_t *)
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        kmalloc(CVMX_MAX_ILK_CHANS * sizeof(cvmx_ilk_pipe_chan_t), GFP_KERNEL);
+#else
+        cvmx_bootmem_alloc (CVMX_MAX_ILK_CHANS * sizeof(cvmx_ilk_pipe_chan_t),
+                            sizeof(cvmx_ilk_pipe_chan_t));
+#endif
+        if (pch == NULL)
+            return 0;
+    }
+
+    memset (pch, 0, CVMX_MAX_ILK_CHANS * sizeof(cvmx_ilk_pipe_chan_t));
+    tmp = pch;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp->pipe = i++;
+        tmp->chan = cvmx_ilk_chan_map[interface][j];
+        tmp++;
+    }
+    res = cvmx_ilk_tx_set_channel (interface, pch, cvmx_ilk_chans[interface]);
+    if (res < 0)
+    {
+        res = 0;
+        goto err_free_pch;
+    }
+    pipe_base += cvmx_ilk_chans[interface];
+
+    /* set up channel to pkind mapping */
+    if (pknd_base == 0)
+        pknd_base = cvmx_helper_get_pknd (interface + CVMX_ILK_GBL_BASE, 0);
+
+    i = pknd_base;
+    if (chpknd == NULL)
+    {
+        chpknd = (cvmx_ilk_chan_pknd_t *)
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        kmalloc(CVMX_MAX_ILK_PKNDS * sizeof(cvmx_ilk_chan_pknd_t), GFP_KERNEL);
+#else
+        cvmx_bootmem_alloc (CVMX_MAX_ILK_PKNDS * sizeof(cvmx_ilk_chan_pknd_t),
+                            sizeof(cvmx_ilk_chan_pknd_t));
+#endif
+        if (chpknd == NULL)
+        {
+            pipe_base -= cvmx_ilk_chans[interface];
+            res = 0;
+            goto err_free_pch;
+        }
+    }
+
+    memset (chpknd, 0, CVMX_MAX_ILK_PKNDS * sizeof(cvmx_ilk_chan_pknd_t));
+    tmp1 = chpknd;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp1->chan = cvmx_ilk_chan_map[interface][j];
+        tmp1->pknd = i++;
+        tmp1++;
+    }
+    res = cvmx_ilk_rx_set_pknd (interface, chpknd, cvmx_ilk_chans[interface]);
+    if (res < 0)
+    {
+        pipe_base -= cvmx_ilk_chans[interface];
+        res = 0;
+        goto err_free_chpknd;
+    }
+    pknd_base += cvmx_ilk_chans[interface];
+
+    /* Set up tx calendar */
+    if (calent == NULL)
+    {
+        calent = (cvmx_ilk_cal_entry_t *)
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        kmalloc(CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t), GFP_KERNEL);
+#else
+        cvmx_bootmem_alloc (CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t),
+                            sizeof(cvmx_ilk_cal_entry_t));
+#endif
+        if (calent == NULL)
+        {
+            pipe_base -= cvmx_ilk_chans[interface];
+            pknd_base -= cvmx_ilk_chans[interface];
+            res = 0;
+            goto err_free_chpknd;
+        }
+    }
+
+    memset (calent, 0, CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t));
+    tmp1 = chpknd;
+    tmp2 = calent;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp2->pipe_bpid = tmp1->pknd;
+        tmp2->ent_ctrl = PIPE_BPID;
+        tmp1++;
+        tmp2++;
+    }
+    res = cvmx_ilk_cal_setup_tx (interface, cvmx_ilk_chans[interface],
+                                 calent, 1);
+    if (res < 0)
+    {
+        pipe_base -= cvmx_ilk_chans[interface];
+        pknd_base -= cvmx_ilk_chans[interface];
+        res = 0;
+        goto err_free_calent;
+    }
+
+    /* set up rx calendar. allocated memory can be reused.
+     * this is because max pkind is always less than max pipe */
+    memset (calent, 0, CVMX_MAX_ILK_PIPES * sizeof(cvmx_ilk_cal_entry_t));
+    tmp = pch;
+    tmp2 = calent;
+    for (j = 0; j < cvmx_ilk_chans[interface]; j++)
+    {
+        tmp2->pipe_bpid = tmp->pipe;
+        tmp2->ent_ctrl = PIPE_BPID;
+        tmp++;
+        tmp2++;
+    }
+    res = cvmx_ilk_cal_setup_rx (interface, cvmx_ilk_chans[interface],
+                                 calent, CVMX_ILK_RX_FIFO_WM, 1);
+    if (res < 0)
+    {
+        pipe_base -= cvmx_ilk_chans[interface];
+        pknd_base -= cvmx_ilk_chans[interface];
+        res = 0;
+        goto err_free_calent;
+    }
+    res = __cvmx_helper_ilk_enumerate(interface + CVMX_ILK_GBL_BASE);
+
+    goto out;
+
+err_free_calent:
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    kfree (calent);
+#else
+    /* no free() for cvmx_bootmem_alloc() */
+#endif
+
+err_free_chpknd:
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    kfree (chpknd);
+#else
+    /* no free() for cvmx_bootmem_alloc() */ 
+#endif
+
+err_free_pch:
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    kfree (pch);
+#else
+    /* no free() for cvmx_bootmem_alloc() */ 
+#endif
+out:
+    return res;
+}
+
+/**
+ * @INTERNAL
+ * Bringup and enable ILK interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_ilk_enable(int interface)
+{
+    interface -= CVMX_ILK_GBL_BASE;
+    return cvmx_ilk_enable(interface);
+}
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by ILK link status.
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_ilk_link_get(int ipd_port)
+{
+    cvmx_helper_link_info_t result;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int retry_count = 0;
+    cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
+    cvmx_ilk_rxx_int_t ilk_rxx_int;
+    int lanes = 0;
+
+    result.u64 = 0;
+    interface -= CVMX_ILK_GBL_BASE;
+
+retry:
+    retry_count++;
+    if (retry_count > 10)
+        goto out;
+
+    ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
+    ilk_rxx_int.u64 = cvmx_read_csr (CVMX_ILK_RXX_INT(interface));
+
+    /* Clear all RX status bits */
+    if (ilk_rxx_int.u64)
+        cvmx_write_csr(CVMX_ILK_RXX_INT(interface), ilk_rxx_int.u64);
+
+    if (ilk_rxx_cfg1.s.rx_bdry_lock_ena == 0)
+    {
+        /* We need to start looking for work boundary lock */
+        ilk_rxx_cfg1.s.rx_bdry_lock_ena = cvmx_ilk_get_intf_ln_msk(interface);
+        ilk_rxx_cfg1.s.rx_align_ena = 0;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        //cvmx_dprintf("ILK%d: Looking for word boundary lock\n", interface);
+        goto retry;
+    }
+
+    if (ilk_rxx_cfg1.s.rx_align_ena == 0)
+    {
+        if (ilk_rxx_int.s.word_sync_done)
+        {
+            ilk_rxx_cfg1.s.rx_align_ena = 1;
+            cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+            //printf("ILK%d: Looking for lane alignment\n", interface);
+            goto retry;
+        }
+        goto out;
+    }
+
+    if (ilk_rxx_int.s.lane_align_fail)
+    {
+        ilk_rxx_cfg1.s.rx_bdry_lock_ena = 0;
+        ilk_rxx_cfg1.s.rx_align_ena = 0;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        cvmx_dprintf("ILK%d: Lane alignment failed\n", interface);
+        goto out;
+    }
+
+    if (ilk_rxx_int.s.lane_align_done)
+    {
+        //cvmx_dprintf("ILK%d: Lane alignment complete\n", interface);
+    }
+
+    lanes = cvmx_pop(ilk_rxx_cfg1.s.rx_bdry_lock_ena);
+
+    result.s.link_up = 1;
+    result.s.full_duplex = 1;
+    result.s.speed = cvmx_qlm_get_gbaud_mhz(1+interface) * 64 / 67;
+    result.s.speed *= lanes;
+
+out:
+    /* If the link is down we will force disable the RX path. If it up, we'll
+        set it to match the TX state set by the if_enable call */
+    if (result.s.link_up)
+    {
+        cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
+        ilk_txx_cfg1.u64 = cvmx_read_csr(CVMX_ILK_TXX_CFG1(interface));
+        ilk_rxx_cfg1.s.pkt_ena = ilk_txx_cfg1.s.pkt_ena;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        //cvmx_dprintf("ILK%d: link up, %d Mbps, Full duplex mode, %d lanes\n", interface, result.s.speed, lanes);  
+    }
+    else
+    {
+        ilk_rxx_cfg1.s.pkt_ena = 0;
+        cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
+        //cvmx_dprintf("ILK link down\n");
+    }
+    return result;
+}
+
+/**
+ * @INTERNAL
+ * Set the link state of an IPD/PKO port.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_ilk_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    /* nothing to do */
+
+    return 0;
+}
+
+/**
+ * Display ilk interface statistics.
+ *
+ */
+void __cvmx_helper_ilk_show_stats (void)
+{
+    int i, j;
+    unsigned char *pchans, num_chans;
+    unsigned int chan_tmp[CVMX_MAX_ILK_CHANS];
+    cvmx_ilk_stats_ctrl_t ilk_stats_ctrl;
+
+    for (i = 0; i < CVMX_NUM_ILK_INTF; i++)
+    {
+        cvmx_ilk_get_chan_info (i, &pchans, &num_chans);
+
+        memset (chan_tmp, 0, CVMX_MAX_ILK_CHANS * sizeof (int));
+        for (j = 0; j < num_chans; j++)
+            chan_tmp[j] = pchans[j];
+
+        ilk_stats_ctrl.chan_list = chan_tmp;
+        ilk_stats_ctrl.num_chans = num_chans;
+        ilk_stats_ctrl.clr_on_rd = 0;
+        cvmx_ilk_show_stats (i, &ilk_stats_ctrl);
+    }
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */