Add a driver for the Freescale Fast Ethernet Controller found on various
Freescale SoCs including the i.MX series. This also works for the newer SoCs with the ENET gigabit controller, but doesn't use any of the new hardware features other than enabling gigabit speed.
This commit is contained in:
Ian Lepore
parent
0b89df4a57
commit
dc82313758
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=256806
@ -49,3 +49,6 @@ dev/ofw/ofw_iicbus.c optional fsliic
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# IPU - Image Processing Unit (frame buffer also)
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arm/freescale/imx/imx51_ipuv3.c optional sc
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# Fast Ethernet Controller
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dev/ffec/if_ffec.c optional ffec
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1740
sys/dev/ffec/if_ffec.c
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1740
sys/dev/ffec/if_ffec.c
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File diff suppressed because it is too large
Load Diff
303
sys/dev/ffec/if_ffecreg.h
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303
sys/dev/ffec/if_ffecreg.h
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@ -0,0 +1,303 @@
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/*-
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* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef IF_FFECREG_H
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#define IF_FFECREG_H
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Hardware defines for Freescale Fast Ethernet Controller.
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*/
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/*
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* MAC registers.
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*/
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#define FEC_IER_REG 0x0004
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#define FEC_IEM_REG 0x0008
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#define FEC_IER_HBERR (1 << 31)
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#define FEC_IER_BABR (1 << 30)
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#define FEC_IER_BABT (1 << 29)
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#define FEC_IER_GRA (1 << 28)
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#define FEC_IER_TXF (1 << 27)
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#define FEC_IER_TXB (1 << 26)
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#define FEC_IER_RXF (1 << 25)
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#define FEC_IER_RXB (1 << 24)
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#define FEC_IER_MII (1 << 23)
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#define FEC_IER_EBERR (1 << 22)
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#define FEC_IER_LC (1 << 21)
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#define FEC_IER_RL (1 << 20)
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#define FEC_IER_UN (1 << 19)
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#define FEC_IER_PLR (1 << 18)
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#define FEC_IER_WAKEUP (1 << 17)
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#define FEC_IER_AVAIL (1 << 16)
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#define FEC_IER_TIMER (1 << 15)
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#define FEC_RDAR_REG 0x0010
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#define FEC_RDAR_RDAR (1 << 24)
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#define FEC_TDAR_REG 0x0014
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#define FEC_TDAR_TDAR (1 << 24)
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#define FEC_ECR_REG 0x0024
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#define FEC_ECR_DBSWP (1 << 8)
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#define FEC_ECR_STOPEN (1 << 7)
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#define FEC_ECR_DBGEN (1 << 6)
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#define FEC_ECR_SPEED (1 << 5)
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#define FEC_ECR_EN1588 (1 << 4)
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#define FEC_ECR_SLEEP (1 << 3)
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#define FEC_ECR_MAGICEN (1 << 2)
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#define FEC_ECR_ETHEREN (1 << 1)
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#define FEC_ECR_RESET (1 << 0)
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#define FEC_MMFR_REG 0x0040
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#define FEC_MMFR_ST_SHIFT 30
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#define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT)
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#define FEC_MMFR_OP_SHIFT 28
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#define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT)
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#define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT)
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#define FEC_MMFR_PA_SHIFT 23
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#define FEC_MMFR_PA_MASK (0x1f << FEC_MMFR_PA_SHIFT)
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#define FEC_MMFR_RA_SHIFT 18
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#define FEC_MMFR_RA_MASK (0x1f << FEC_MMFR_RA_SHIFT)
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#define FEC_MMFR_TA_SHIFT 16
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#define FEC_MMFR_TA_VALUE (0x02 << FEC_MMFR_TA_SHIFT)
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#define FEC_MMFR_DATA_SHIFT 0
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#define FEC_MMFR_DATA_MASK (0xffff << FEC_MMFR_DATA_SHIFT)
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#define FEC_MSCR_REG 0x0044
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#define FEC_MSCR_HOLDTIME_SHIFT 8
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#define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT)
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#define FEC_MSCR_DIS_PRE (1 << 7)
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#define FEC_MSCR_MII_SPEED_SHIFT 1
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#define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT)
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#define FEC_MIBC_REG 0x0064
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#define FEC_MIBC_DIS (1 << 31)
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#define FEC_MIBC_IDLE (1 << 30)
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#define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */
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#define FEC_RCR_REG 0x0084
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#define FEC_RCR_GRS (1 << 31)
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#define FEC_RCR_NLC (1 << 30)
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#define FEC_RCR_MAX_FL_SHIFT 16
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#define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT)
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#define FEC_RCR_CFEN (1 << 15)
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#define FEC_RCR_CRCFWD (1 << 14)
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#define FEC_RCR_PAUFWD (1 << 13)
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#define FEC_RCR_PADEN (1 << 12)
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#define FEC_RCR_RMII_10T (1 << 9)
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#define FEC_RCR_RMII_MODE (1 << 8)
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#define FEC_RCR_RGMII_EN (1 << 6)
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#define FEC_RCR_FCE (1 << 5)
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#define FEC_RCR_BC_REJ (1 << 4)
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#define FEC_RCR_PROM (1 << 3)
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#define FEC_RCR_MII_MODE (1 << 2)
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#define FEC_RCR_DRT (1 << 1)
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#define FEC_RCR_LOOP (1 << 0)
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#define FEC_TCR_REG 0x00c4
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#define FEC_TCR_ADDINS (1 << 9)
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#define FEC_TCR_ADDSEL_SHIFT 5
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#define FEC_TCR_ADDSEL_MASK (0x07 << FEC_TCR_ADDSEL_SHIFT)
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#define FEC_TCR_RFC_PAUSE (1 << 4)
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#define FEC_TCR_TFC_PAUSE (1 << 3)
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#define FEC_TCR_FDEN (1 << 2)
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#define FEC_TCR_GTS (1 << 0)
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#define FEC_PALR_REG 0x00e4
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#define FEC_PALR_PADDR1_SHIFT 0
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#define FEC_PALR_PADDR1_MASK (0xffffffff << FEC_PALR_PADDR1_SHIFT)
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#define FEC_PAUR_REG 0x00e8
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#define FEC_PAUR_PADDR2_SHIFT 16
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#define FEC_PAUR_PADDR2_MASK (0xffff << FEC_PAUR_PADDR2_SHIFT)
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#define FEC_PAUR_TYPE_VALUE (0x8808)
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#define FEC_OPD_REG 0x00ec
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#define FEC_OPD_PAUSE_DUR_SHIFT 0
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#define FEC_OPD_PAUSE_DUR_MASK (0xffff << FEC_OPD_PAUSE_DUR_SHIFT)
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#define FEC_IAUR_REG 0x0118
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#define FEC_IALR_REG 0x011c
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#define FEC_GAUR_REG 0x0120
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#define FEC_GALR_REG 0x0124
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#define FEC_TFWR_REG 0x0144
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#define FEC_TFWR_STRFWD (1 << 8)
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#define FEC_TFWR_TWFR_SHIFT 0
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#define FEC_TFWR_TWFR_MASK (0x3f << FEC_TFWR_TWFR_SHIFT)
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#define FEC_TFWR_TWFR_128BYTE (0x02 << FEC_TFWR_TWFR_SHIFT)
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#define FEC_RDSR_REG 0x0180
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#define FEC_TDSR_REG 0x0184
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#define FEC_MRBR_REG 0x0188
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#define FEC_MRBR_R_BUF_SIZE_SHIFT 0
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#define FEC_MRBR_R_BUF_SIZE_MASK (0x3fff << FEC_MRBR_R_BUF_SIZE_SHIFT)
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#define FEC_RSFL_REG 0x0190
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#define FEC_RSEM_REG 0x0194
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#define FEC_RAEM_REG 0x0198
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#define FEC_RAFL_REG 0x019c
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#define FEC_TSEM_REG 0x01a0
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#define FEC_TAEM_REG 0x01a4
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#define FEC_TAFL_REG 0x01a8
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#define FEC_TIPG_REG 0x01ac
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#define FEC_FTRL_REG 0x01b0
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#define FEC_TACC_REG 0x01c0
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#define FEC_TACC_PROCHK (1 << 4)
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#define FEC_TACC_IPCHK (1 << 3)
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#define FEC_TACC_SHIFT16 (1 << 0)
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#define FEC_RACC_REG 0x01c4
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#define FEC_RACC_SHIFT16 (1 << 7)
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#define FEC_RACC_LINEDIS (1 << 6)
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#define FEC_RACC_PRODIS (1 << 2)
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#define FEC_RACC_IPDIS (1 << 1)
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#define FEC_RACC_PADREM (1 << 0)
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/*
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* Statistics registers
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*/
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#define FEC_RMON_T_DROP 0x200
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#define FEC_RMON_T_PACKETS 0x204
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#define FEC_RMON_T_BC_PKT 0x208
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#define FEC_RMON_T_MC_PKT 0x20C
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#define FEC_RMON_T_CRC_ALIGN 0x210
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#define FEC_RMON_T_UNDERSIZE 0x214
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#define FEC_RMON_T_OVERSIZE 0x218
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#define FEC_RMON_T_FRAG 0x21C
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#define FEC_RMON_T_JAB 0x220
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#define FEC_RMON_T_COL 0x224
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#define FEC_RMON_T_P64 0x228
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#define FEC_RMON_T_P65TO127 0x22C
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#define FEC_RMON_T_P128TO255 0x230
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#define FEC_RMON_T_P256TO511 0x234
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#define FEC_RMON_T_P512TO1023 0x238
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#define FEC_RMON_T_P1024TO2047 0x23C
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#define FEC_RMON_T_P_GTE2048 0x240
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#define FEC_RMON_T_OCTECTS 0x240
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#define FEC_IEEE_T_DROP 0x248
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#define FEC_IEEE_T_FRAME_OK 0x24C
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#define FEC_IEEE_T_1COL 0x250
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#define FEC_IEEE_T_MCOL 0x254
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#define FEC_IEEE_T_DEF 0x258
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#define FEC_IEEE_T_LCOL 0x25C
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#define FEC_IEEE_T_EXCOL 0x260
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#define FEC_IEEE_T_MACERR 0x264
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#define FEC_IEEE_T_CSERR 0x268
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#define FEC_IEEE_T_SQE 0x26C
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#define FEC_IEEE_T_FDXFC 0x270
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#define FEC_IEEE_T_OCTETS_OK 0x274
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#define FEC_RMON_R_PACKETS 0x284
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#define FEC_RMON_R_BC_PKT 0x288
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#define FEC_RMON_R_MC_PKT 0x28C
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#define FEC_RMON_R_CRC_ALIGN 0x290
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#define FEC_RMON_R_UNDERSIZE 0x294
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#define FEC_RMON_R_OVERSIZE 0x298
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#define FEC_RMON_R_FRAG 0x29C
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#define FEC_RMON_R_JAB 0x2A0
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#define FEC_RMON_R_RESVD_0 0x2A4
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#define FEC_RMON_R_P64 0x2A8
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#define FEC_RMON_R_P65TO127 0x2AC
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#define FEC_RMON_R_P128TO255 0x2B0
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#define FEC_RMON_R_P256TO511 0x2B4
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#define FEC_RMON_R_P512TO1023 0x2B8
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#define FEC_RMON_R_P1024TO2047 0x2BC
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#define FEC_RMON_R_P_GTE2048 0x2C0
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#define FEC_RMON_R_OCTETS 0x2C4
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#define FEC_IEEE_R_DROP 0x2C8
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#define FEC_IEEE_R_FRAME_OK 0x2CC
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#define FEC_IEEE_R_CRC 0x2D0
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#define FEC_IEEE_R_ALIGN 0x2D4
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#define FEC_IEEE_R_MACERR 0x2D8
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#define FEC_IEEE_R_FDXFC 0x2DC
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#define FEC_IEEE_R_OCTETS_OK 0x2E0
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#define FEC_MIIGSK_CFGR 0x300
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#define FEC_MIIGSK_CFGR_FRCONT (1 << 6) /* Freq: 0=50MHz, 1=5MHz */
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#define FEC_MIIGSK_CFGR_LBMODE (1 << 4) /* loopback mode */
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#define FEC_MIIGSK_CFGR_EMODE (1 << 3) /* echo mode */
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#define FEC_MIIGSK_CFGR_IF_MODE_MASK (0x3 << 0)
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#define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0)
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#define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
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#define FEC_MIIGSK_ENR 0x308
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#define FEC_MIIGSK_ENR_READY (1 << 2)
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#define FEC_MIIGSK_ENR_EN (1 << 1)
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/*
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* A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
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* layout, but the bits in the flags field have different meanings.
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*/
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struct ffec_hwdesc
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{
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uint32_t flags_len;
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uint32_t buf_paddr;
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};
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#define FEC_TXDESC_READY (1 << 31)
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#define FEC_TXDESC_T01 (1 << 30)
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#define FEC_TXDESC_WRAP (1 << 29)
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#define FEC_TXDESC_T02 (1 << 28)
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#define FEC_TXDESC_L (1 << 27)
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#define FEC_TXDESC_TC (1 << 26)
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#define FEC_TXDESC_ABC (1 << 25)
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#define FEC_TXDESC_LEN_MASK (0xffff)
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#define FEC_RXDESC_EMPTY (1 << 31)
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#define FEC_RXDESC_R01 (1 << 30)
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#define FEC_RXDESC_WRAP (1 << 29)
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#define FEC_RXDESC_R02 (1 << 28)
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#define FEC_RXDESC_L (1 << 27)
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#define FEC_RXDESC_M (1 << 24)
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#define FEC_RXDESC_BC (1 << 23)
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#define FEC_RXDESC_MC (1 << 22)
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#define FEC_RXDESC_LG (1 << 21)
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#define FEC_RXDESC_NO (1 << 20)
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#define FEC_RXDESC_CR (1 << 18)
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#define FEC_RXDESC_OV (1 << 17)
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#define FEC_RXDESC_TR (1 << 16)
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#define FEC_RXDESC_LEN_MASK (0xffff)
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#define FEC_RXDESC_ERROR_BITS (FEC_RXDESC_LG | FEC_RXDESC_NO | \
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FEC_RXDESC_OV | FEC_RXDESC_TR)
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/*
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* The hardware imposes alignment restrictions on various objects involved in
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* DMA transfers. These values are expressed in bytes (not bits).
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*/
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#define FEC_DESC_RING_ALIGN 16
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#define FEC_RXBUF_ALIGN 16
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#define FEC_TXBUF_ALIGN 16
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#endif /* IF_FFECREG_H */
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