dwmmc: Add clock support and other improvements
* If compiled with EXT_RESOURCES look up the "biu" and "ciu" clocks in the DT * Don't use custom property "bus-frequency" but the standard one "clock-frequency" * Use the DT property max-frequency and fall back to 200Mhz if it don't exists * Add more mmc caps suported by the controller * Always ack all interrupts * Subclassed driver can supply an update_ios so they can handle update the clocks accordingly * Take care of the DDR bit in update_ios (no functional change since we do not support voltage change for now) * Make use of the FDT bus-width property
This commit is contained in:
parent
2a3d5e3364
commit
dd198e868a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=330037
@ -56,6 +56,10 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#ifdef EXT_RESOURCES
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#include <dev/extres/clk/clk.h>
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#endif
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#include <dev/mmc/host/dwmmc_reg.h>
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#include <dev/mmc/host/dwmmc_var.h>
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@ -341,14 +345,12 @@ dwmmc_intr(void *arg)
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dprintf("%s 0x%08x\n", __func__, reg);
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if (reg & DWMMC_CMD_ERR_FLAGS) {
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WRITE4(sc, SDMMC_RINTSTS, DWMMC_CMD_ERR_FLAGS);
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dprintf("cmd err 0x%08x cmd 0x%08x\n",
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reg, cmd->opcode);
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cmd->error = MMC_ERR_TIMEOUT;
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}
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if (reg & DWMMC_DATA_ERR_FLAGS) {
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WRITE4(sc, SDMMC_RINTSTS, DWMMC_DATA_ERR_FLAGS);
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dprintf("data err 0x%08x cmd 0x%08x\n",
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reg, cmd->opcode);
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cmd->error = MMC_ERR_FAILED;
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@ -361,25 +363,22 @@ dwmmc_intr(void *arg)
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if (reg & SDMMC_INTMASK_CMD_DONE) {
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dwmmc_cmd_done(sc);
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sc->cmd_done = 1;
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WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CMD_DONE);
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}
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if (reg & SDMMC_INTMASK_ACD) {
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if (reg & SDMMC_INTMASK_ACD)
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sc->acd_rcvd = 1;
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WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_ACD);
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}
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if (reg & SDMMC_INTMASK_DTO) {
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if (reg & SDMMC_INTMASK_DTO)
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sc->dto_rcvd = 1;
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WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_DTO);
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}
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if (reg & SDMMC_INTMASK_CD) {
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/* XXX: Handle card detect */
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WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CD);
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}
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}
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/* Ack interrupts */
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WRITE4(sc, SDMMC_RINTSTS, reg);
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if (sc->use_pio) {
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if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) {
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pio_read(sc, cmd);
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@ -411,37 +410,88 @@ parse_fdt(struct dwmmc_softc *sc)
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{
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pcell_t dts_value[3];
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phandle_t node;
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uint32_t bus_hz = 0, bus_width;
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int len;
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#ifdef EXT_RESOURCES
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int error;
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#endif
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if ((node = ofw_bus_get_node(sc->dev)) == -1)
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return (ENXIO);
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/* bus-width */
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if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
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bus_width = 4;
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if (bus_width >= 4)
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sc->host.caps |= MMC_CAP_4_BIT_DATA;
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if (bus_width >= 8)
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sc->host.caps |= MMC_CAP_8_BIT_DATA;
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/* max-frequency */
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if (OF_getencprop(node, "max-frequency", &sc->max_hz, sizeof(uint32_t)) <= 0)
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sc->max_hz = 200000000;
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/* fifo-depth */
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if ((len = OF_getproplen(node, "fifo-depth")) > 0) {
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OF_getencprop(node, "fifo-depth", dts_value, len);
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sc->fifo_depth = dts_value[0];
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}
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/* num-slots */
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/* num-slots (Deprecated) */
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sc->num_slots = 1;
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if ((len = OF_getproplen(node, "num-slots")) > 0) {
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device_printf(sc->dev, "num-slots property is deprecated\n");
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OF_getencprop(node, "num-slots", dts_value, len);
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sc->num_slots = dts_value[0];
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}
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/* clock-frequency */
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if ((len = OF_getproplen(node, "clock-frequency")) > 0) {
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OF_getencprop(node, "clock-frequency", dts_value, len);
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bus_hz = dts_value[0];
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}
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#ifdef EXT_RESOURCES
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/* BIU (Bus Interface Unit clock) is optional */
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error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu);
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if (sc->biu) {
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error = clk_enable(sc->biu);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable biu clock\n");
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goto fail;
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}
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}
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/*
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* We need some platform-specific code to know
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* what the clock is supplied for our device.
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* For now rely on the value specified in FDT.
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* CIU (Controller Interface Unit clock) is mandatory
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* if no clock-frequency property is given
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*/
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error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu);
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if (sc->ciu) {
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error = clk_enable(sc->ciu);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable ciu clock\n");
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goto fail;
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}
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if (bus_hz != 0) {
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error = clk_set_freq(sc->ciu, bus_hz, 0);
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if (error != 0)
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device_printf(sc->dev,
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"cannot set ciu clock to %u\n", bus_hz);
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}
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clk_get_freq(sc->ciu, &sc->bus_hz);
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}
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#endif /* EXT_RESOURCES */
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if (sc->bus_hz == 0) {
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if ((len = OF_getproplen(node, "bus-frequency")) <= 0)
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return (ENXIO);
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OF_getencprop(node, "bus-frequency", dts_value, len);
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sc->bus_hz = dts_value[0];
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device_printf(sc->dev, "No bus speed provided\n");
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goto fail;
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}
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return (0);
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fail:
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return (ENXIO);
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}
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int
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@ -541,9 +591,10 @@ dwmmc_attach(device_t dev)
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WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE);
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sc->host.f_min = 400000;
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sc->host.f_max = min(200000000, sc->bus_hz);
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sc->host.f_max = sc->max_hz;
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sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
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sc->host.caps = MMC_CAP_4_BIT_DATA;
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sc->host.caps |= MMC_CAP_HSPEED;
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sc->host.caps |= MMC_CAP_SIGNALING_330;
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device_add_child(dev, "mmc", -1);
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return (bus_generic_attach(dev));
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@ -608,6 +659,8 @@ dwmmc_update_ios(device_t brdev, device_t reqdev)
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{
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struct dwmmc_softc *sc;
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struct mmc_ios *ios;
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uint32_t reg;
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int ret = 0;
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sc = device_get_softc(brdev);
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ios = &sc->host.ios;
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@ -615,8 +668,6 @@ dwmmc_update_ios(device_t brdev, device_t reqdev)
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dprintf("Setting up clk %u bus_width %d\n",
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ios->clock, ios->bus_width);
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dwmmc_setup_bus(sc, ios->clock);
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if (ios->bus_width == bus_width_8)
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WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);
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else if (ios->bus_width == bus_width_4)
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@ -629,15 +680,22 @@ dwmmc_update_ios(device_t brdev, device_t reqdev)
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WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing);
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}
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/*
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* XXX: take care about DDR bit
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*
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* reg = READ4(sc, SDMMC_UHS_REG);
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* reg |= (SDMMC_UHS_REG_DDR);
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* WRITE4(sc, SDMMC_UHS_REG, reg);
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*/
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/* Set DDR mode */
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reg = READ4(sc, SDMMC_UHS_REG);
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if (ios->timing == bus_timing_uhs_ddr50 ||
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ios->timing == bus_timing_mmc_ddr52 ||
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ios->timing == bus_timing_mmc_hs400)
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reg |= (SDMMC_UHS_REG_DDR);
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else
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reg &= ~(SDMMC_UHS_REG_DDR);
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WRITE4(sc, SDMMC_UHS_REG, reg);
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return (0);
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if (sc->update_ios)
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ret = sc->update_ios(sc, ios);
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dwmmc_setup_bus(sc, ios->clock);
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return (ret);
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}
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static int
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@ -1032,7 +1090,6 @@ dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
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*(int *)result = sc->host.ios.vdd;
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break;
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case MMCBR_IVAR_CAPS:
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sc->host.caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
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*(int *)result = sc->host.caps;
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break;
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case MMCBR_IVAR_MAX_DATA:
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@ -33,6 +33,10 @@
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#ifndef DEV_MMC_HOST_DWMMC_VAR_H
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#define DEV_MMC_HOST_DWMMC_VAR_H
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#ifdef EXT_RESOURCES
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#include <dev/extres/clk/clk.h>
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#endif
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enum {
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HWTYPE_NONE,
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HWTYPE_ALTERA,
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@ -56,6 +60,8 @@ struct dwmmc_softc {
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uint32_t pwren_inverted;
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u_int desc_count;
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int (*update_ios)(struct dwmmc_softc *sc, struct mmc_ios *ios);
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bus_dma_tag_t desc_tag;
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bus_dmamap_t desc_map;
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struct idmac_desc *desc_ring;
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@ -67,11 +73,17 @@ struct dwmmc_softc {
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uint32_t dto_rcvd;
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uint32_t acd_rcvd;
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uint32_t cmd_done;
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uint32_t bus_hz;
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uint64_t bus_hz;
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uint32_t max_hz;
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uint32_t fifo_depth;
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uint32_t num_slots;
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uint32_t sdr_timing;
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uint32_t ddr_timing;
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#ifdef EXT_RESOURCES
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clk_t biu;
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clk_t ciu;
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#endif
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};
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DECLARE_CLASS(dwmmc_driver);
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