MFamd64: Use initializecpu() to set various model-specific registers on
AP startup and AP resume (it was already used for BSP startup and BSP resume). - Split code to do one-time probing of cache properties out of initializecpu() and into initializecpucache(). This is called once on the BSP during boot. - Move enable_sse() into initializecpu(). - Call initializecpu() for AP startup instead of enable_sse() and manually frobbing MSR_EFER to enable PG_NX. - Call initializecpu() when an AP resumes. In theory this will now properly re-enable PG_NX in MSR_EFER when resuming a PAE kernel on APs.
This commit is contained in:
parent
645b112b68
commit
de2b02fc74
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=271409
@ -721,7 +721,7 @@ init_secondary(void)
|
||||
/* set up CPU registers and state */
|
||||
cpu_setregs();
|
||||
|
||||
/* set up SSE/NX registers */
|
||||
/* set up SSE/NX */
|
||||
initializecpu();
|
||||
|
||||
/* set up FPU state on the AP */
|
||||
|
@ -457,7 +457,7 @@ init_winchip(void)
|
||||
fcr &= ~(1ULL << 11);
|
||||
|
||||
/*
|
||||
* Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
|
||||
* Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
|
||||
*/
|
||||
if (CPUID_TO_MODEL(cpu_id) >= 8)
|
||||
fcr |= (1 << 12) | (1 << 19) | (1 << 20);
|
||||
@ -674,20 +674,6 @@ init_transmeta(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize CR4 (Control register 4) to enable SSE instructions.
|
||||
*/
|
||||
void
|
||||
enable_sse(void)
|
||||
{
|
||||
#if defined(CPU_ENABLE_SSE)
|
||||
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
|
||||
load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
|
||||
cpu_fxsr = hw_instruction_sse = 1;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
extern int elf32_nxstack;
|
||||
|
||||
void
|
||||
@ -811,7 +797,17 @@ initializecpu(void)
|
||||
default:
|
||||
break;
|
||||
}
|
||||
enable_sse();
|
||||
#if defined(CPU_ENABLE_SSE)
|
||||
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
|
||||
load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
|
||||
cpu_fxsr = hw_instruction_sse = 1;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
initializecpucache(void)
|
||||
{
|
||||
|
||||
/*
|
||||
* CPUID with %eax = 1, %ebx returns
|
||||
|
@ -2753,6 +2753,7 @@ init386(first)
|
||||
setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
|
||||
GSEL(GCODE_SEL, SEL_KPL));
|
||||
initializecpu(); /* Initialize CPU registers */
|
||||
initializecpucache();
|
||||
|
||||
/* make an initial tss so cpu can get interrupt stack on syscall! */
|
||||
/* Note: -16 is so we can grow the trapframe if we came from vm86 */
|
||||
|
@ -745,25 +745,15 @@ init_secondary(void)
|
||||
/* set up CPU registers and state */
|
||||
cpu_setregs();
|
||||
|
||||
/* set up SSE/NX */
|
||||
initializecpu();
|
||||
|
||||
/* set up FPU state on the AP */
|
||||
npxinit();
|
||||
|
||||
/* set up SSE registers */
|
||||
enable_sse();
|
||||
|
||||
if (cpu_ops.cpu_init)
|
||||
cpu_ops.cpu_init();
|
||||
|
||||
#ifdef PAE
|
||||
/* Enable the PTE no-execute bit. */
|
||||
if ((amd_feature & AMDID_NX) != 0) {
|
||||
uint64_t msr;
|
||||
|
||||
msr = rdmsr(MSR_EFER) | EFER_NXE;
|
||||
wrmsr(MSR_EFER, msr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* A quick check from sanity claus */
|
||||
cpuid = PCPU_GET(cpuid);
|
||||
if (PCPU_GET(apic_id) != lapic_id()) {
|
||||
@ -1528,6 +1518,7 @@ cpususpend_handler(void)
|
||||
} else {
|
||||
npxresume(&susppcbs[cpu]->sp_fpususpend);
|
||||
pmap_init_pat();
|
||||
initializecpu();
|
||||
PCPU_SET(switchtime, 0);
|
||||
PCPU_SET(switchticks, ticks);
|
||||
|
||||
|
@ -99,9 +99,9 @@ void doreti_popl_fs_fault(void) __asm(__STRING(doreti_popl_fs_fault));
|
||||
void dump_add_page(vm_paddr_t);
|
||||
void dump_drop_page(vm_paddr_t);
|
||||
void finishidentcpu(void);
|
||||
void enable_sse(void);
|
||||
void fillw(int /*u_short*/ pat, void *base, size_t cnt);
|
||||
void initializecpu(void);
|
||||
void initializecpucache(void);
|
||||
void i686_pagezero(void *addr);
|
||||
void sse2_pagezero(void *addr);
|
||||
void init_AMD_Elan_sc520(void);
|
||||
|
@ -598,22 +598,13 @@ init_secondary(void)
|
||||
for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
|
||||
invlpg(addr);
|
||||
|
||||
#if 0
|
||||
/* set up SSE/NX */
|
||||
initializecpu();
|
||||
#endif
|
||||
|
||||
/* set up FPU state on the AP */
|
||||
npxinit();
|
||||
#if 0
|
||||
|
||||
/* set up SSE registers */
|
||||
enable_sse();
|
||||
#endif
|
||||
#if 0 && defined(PAE)
|
||||
/* Enable the PTE no-execute bit. */
|
||||
if ((amd_feature & AMDID_NX) != 0) {
|
||||
uint64_t msr;
|
||||
|
||||
msr = rdmsr(MSR_EFER) | EFER_NXE;
|
||||
wrmsr(MSR_EFER, msr);
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
/* A quick check from sanity claus */
|
||||
if (PCPU_GET(apic_id) != lapic_id()) {
|
||||
|
@ -2315,6 +2315,7 @@ init386(first)
|
||||
setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
|
||||
GSEL(GCODE_SEL, SEL_KPL));
|
||||
initializecpu(); /* Initialize CPU registers */
|
||||
initializecpucache();
|
||||
|
||||
/* make an initial tss so cpu can get interrupt stack on syscall! */
|
||||
/* Note: -16 is so we can grow the trapframe if we came from vm86 */
|
||||
|
Loading…
Reference in New Issue
Block a user