Be slightly more paranoid with the TX DMA buffer maximum threshold.
Specifically - never jack the TX FIFO threshold up to the absolute maximum; always leave enough space for two DMA transactions to appear. This is a paranoia from the Linux ath9k driver. It can't hurt. Obtained from: Linux ath9k
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=247092
@ -244,9 +244,23 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
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/* Set overridable ANI methods */
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AH5212(ah)->ah_aniControl = ar5416AniControl;
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/* Default FIFO Trigger levels */
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/*
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* Default FIFO Trigger levels
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*
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* These define how filled the TX FIFO needs to be before
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* the baseband begins to be given some data.
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*
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* To be paranoid, we ensure that the TX trigger level always
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* has at least enough space for two TX DMA to occur.
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* The TX DMA size is currently hard-coded to AR_TXCFG_DMASZ_128B.
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* That means we need to leave at least 256 bytes available in
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* the TX DMA FIFO.
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*/
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#define AR_FTRIG_512B 0x00000080 // 5 bits total
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/* AR9285/AR9271 need to use half the TX FIFOs */
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/*
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* AR9285/AR9271 have half the size TX FIFO compared to
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* other devices
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*/
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if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) {
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AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S);
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AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1);
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@ -255,6 +269,9 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
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AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1);
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}
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#undef AR_FTRIG_512B
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/* And now leave some headspace - 256 bytes */
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AH5212(ah)->ah_maxTxTrigLev -= 4;
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}
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uint32_t
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@ -570,6 +570,10 @@ ar5416InitDMA(struct ath_hal *ah)
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/*
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* let mac dma writes be in 128 byte chunks
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*/
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/*
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* XXX If you change this, you must change the headroom
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* assigned in ah_maxTxTrigLev - see ar5416InitState().
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*/
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OS_REG_WRITE(ah, AR_RXCFG,
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(OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B);
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