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arm64: rockchip: clk: Add MUXRAW macros

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Some clocks in the RK3328 SoC (and possibly others) have registers not in
the CLKSEL_CON range. Add a macros for muxes which lives not in the range
of CLKSEL_CON which just takes a raw offset.
This commit is contained in:
Emmanuel Vadot 2021-09-15 18:25:09 +02:00
parent 731e418bd7
commit deff1fb3dc
1 changed files with 6 additions and 3 deletions
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9
sys/arm64/rockchip/clk/rk_cru.h
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@ -170,7 +170,7 @@
}
/* Complex clock without divider (multiplexer only). */
#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \
#define MUXRAW(_id, _name, _pn, _f, _mo, _ms, _mw) \
{ \
.type = RK_CLK_MUX, \
.clk.mux = &(struct rk_clk_mux_def) { \
@ -179,13 +179,16 @@
.clkdef.parent_names = _pn, \
.clkdef.parent_cnt = nitems(_pn), \
.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
.offset = CRU_CLKSEL_CON(_mo), \
.offset = _mo, \
.shift = _ms, \
.width = _mw, \
.mux_flags = _f, \
.mux_flags = _f, \
}, \
}
#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \
MUXRAW(_id, _name, _pn, _f, CRU_CLKSEL_CON(_mo), _ms, _mw)
/* Complex clock without divider (multiplexer only in GRF). */
#define MUXGRF(_id, _name, _pn, _f, _mo, _ms, _mw) \
{ \