arm64: rockchip: clk: Add MUXRAW macros
Some clocks in the RK3328 SoC (and possibly others) have registers not in the CLKSEL_CON range. Add a macros for muxes which lives not in the range of CLKSEL_CON which just takes a raw offset.
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@ -170,7 +170,7 @@
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/* Complex clock without divider (multiplexer only). */
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#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \
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#define MUXRAW(_id, _name, _pn, _f, _mo, _ms, _mw) \
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{ \
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.type = RK_CLK_MUX, \
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.clk.mux = &(struct rk_clk_mux_def) { \
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@ -179,13 +179,16 @@
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.clkdef.parent_names = _pn, \
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.clkdef.parent_cnt = nitems(_pn), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = CRU_CLKSEL_CON(_mo), \
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.offset = _mo, \
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.shift = _ms, \
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.width = _mw, \
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.mux_flags = _f, \
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.mux_flags = _f, \
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}, \
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}
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#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \
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MUXRAW(_id, _name, _pn, _f, CRU_CLKSEL_CON(_mo), _ms, _mw)
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/* Complex clock without divider (multiplexer only in GRF). */
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#define MUXGRF(_id, _name, _pn, _f, _mo, _ms, _mw) \
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{ \
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