cxgbe(4): Add another setting to the knob that controls congestion.
hw.cxgbe.cong_drop=2 will generate backpressure *and* drop frames for queues that are congested. MFC after: 2 weeks Sponsored by: Chelsio Communications
This commit is contained in:
parent
c387ff0045
commit
df275ae509
@ -31,7 +31,7 @@
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.\"
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.\"
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.\" $FreeBSD$
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.\" $FreeBSD$
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.\"
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.\"
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.Dd November 10, 2021
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.Dd September 12, 2022
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.Dt CXGBE 4
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.Dt CXGBE 4
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.Os
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.Os
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.Sh NAME
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.Sh NAME
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@ -277,6 +277,7 @@ Controls the hardware response to congestion.
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0 instructs the hardware to backpressure its pipeline on congestion.
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0 instructs the hardware to backpressure its pipeline on congestion.
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This usually results in the port emitting PAUSE frames.
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This usually results in the port emitting PAUSE frames.
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1 instructs the hardware to drop frames destined for congested queues.
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1 instructs the hardware to drop frames destined for congested queues.
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2 instructs the hardware to both backpressure the pipeline and drop frames.
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.It Va hw.cxgbe.pause_settings
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.It Va hw.cxgbe.pause_settings
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PAUSE frame settings.
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PAUSE frame settings.
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Bit 0 is rx_pause, bit 1 is tx_pause, bit 2 is pause_autoneg.
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Bit 0 is rx_pause, bit 1 is tx_pause, bit 2 is pause_autoneg.
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@ -428,7 +428,7 @@ struct sge_iq {
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int8_t intr_pktc_idx; /* packet count threshold index */
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int8_t intr_pktc_idx; /* packet count threshold index */
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uint8_t gen; /* generation bit */
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uint8_t gen; /* generation bit */
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uint8_t intr_params; /* interrupt holdoff parameters */
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uint8_t intr_params; /* interrupt holdoff parameters */
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int8_t cong; /* congestion settings */
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int8_t cong_drop; /* congestion drop settings for the queue */
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uint16_t qsize; /* size (# of entries) of the queue */
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uint16_t qsize; /* size (# of entries) of the queue */
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uint16_t sidx; /* index of the entry with the status page */
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uint16_t sidx; /* index of the entry with the status page */
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uint16_t cidx; /* consumer index */
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uint16_t cidx; /* consumer index */
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@ -1384,7 +1384,7 @@ struct mbuf *alloc_wr_mbuf(int, int);
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int parse_pkt(struct mbuf **, bool);
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int parse_pkt(struct mbuf **, bool);
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void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
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void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
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void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
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void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
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int tnl_cong(struct port_info *, int);
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int t4_sge_set_conm_context(struct adapter *, int, int, int);
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void t4_register_an_handler(an_handler_t);
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void t4_register_an_handler(an_handler_t);
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void t4_register_fw_msg_handler(int, fw_msg_handler_t);
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void t4_register_fw_msg_handler(int, fw_msg_handler_t);
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void t4_register_cpl_handler(int, cpl_handler_t);
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void t4_register_cpl_handler(int, cpl_handler_t);
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@ -276,14 +276,17 @@ free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
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}
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}
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static int
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static int
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alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
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alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
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{
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{
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int rc, cntxt_id, i;
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int rc, cntxt_id;
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__be32 v;
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__be32 v;
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struct adapter *sc = vi->adapter;
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struct adapter *sc = vi->adapter;
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struct port_info *pi = vi->pi;
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struct sge_params *sp = &sc->params.sge;
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struct sge_params *sp = &sc->params.sge;
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struct netmap_adapter *na = NA(vi->ifp);
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struct netmap_adapter *na = NA(vi->ifp);
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struct fw_iq_cmd c;
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struct fw_iq_cmd c;
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const int cong_drop = nm_cong_drop;
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const int cong_map = pi->rx_e_chan_map;
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MPASS(na != NULL);
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MPASS(na != NULL);
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MPASS(nm_rxq->iq_desc != NULL);
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MPASS(nm_rxq->iq_desc != NULL);
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@ -313,15 +316,15 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
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V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
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V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
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V_FW_IQ_CMD_VIID(vi->viid) |
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V_FW_IQ_CMD_VIID(vi->viid) |
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V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
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V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
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c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
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c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
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F_FW_IQ_CMD_IQGTSMODE |
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F_FW_IQ_CMD_IQGTSMODE |
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V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
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V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
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V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
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V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
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c.iqsize = htobe16(vi->qsize_rxq);
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c.iqsize = htobe16(vi->qsize_rxq);
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c.iqaddr = htobe64(nm_rxq->iq_ba);
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c.iqaddr = htobe64(nm_rxq->iq_ba);
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if (cong >= 0) {
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if (cong_drop != -1) {
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c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
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c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
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V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
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V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | F_FW_IQ_CMD_FL0CONGCIF |
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F_FW_IQ_CMD_FL0CONGEN);
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F_FW_IQ_CMD_FL0CONGEN);
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}
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}
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c.iqns_to_fl0congen |=
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c.iqns_to_fl0congen |=
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@ -373,29 +376,9 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
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nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
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nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
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sc->chip_params->sge_fl_db;
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sc->chip_params->sge_fl_db;
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if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
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if (chip_id(sc) >= CHELSIO_T5 && cong_drop != -1) {
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uint32_t param, val;
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t4_sge_set_conm_context(sc, nm_rxq->iq_cntxt_id, cong_drop,
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cong_map);
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param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
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V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
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V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
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if (cong == 0)
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val = 1 << 19;
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else {
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val = 2 << 19;
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for (i = 0; i < 4; i++) {
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if (cong & (1 << i))
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val |= 1 << (i << 2);
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}
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}
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rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
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if (rc != 0) {
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/* report error but carry on */
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device_printf(sc->dev,
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"failed to set congestion manager context for "
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"ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
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}
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}
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}
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t4_write_reg(sc, sc->sge_gts_reg,
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t4_write_reg(sc, sc->sge_gts_reg,
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@ -749,7 +732,7 @@ cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
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if (!nm_kring_pending_on(kring))
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if (!nm_kring_pending_on(kring))
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continue;
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continue;
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alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop));
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alloc_nm_rxq_hwq(vi, nm_rxq);
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nm_rxq->fl_hwidx = hwidx;
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nm_rxq->fl_hwidx = hwidx;
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slot = netmap_reset(na, NR_RX, i, 0);
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slot = netmap_reset(na, NR_RX, i, 0);
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MPASS(slot != NULL); /* XXXNM: error check, not assert */
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MPASS(slot != NULL); /* XXXNM: error check, not assert */
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@ -124,10 +124,11 @@ SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
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* -1: no congestion feedback (not recommended).
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* -1: no congestion feedback (not recommended).
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* 0: backpressure the channel instead of dropping packets right away.
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* 0: backpressure the channel instead of dropping packets right away.
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* 1: no backpressure, drop packets for the congested queue immediately.
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* 1: no backpressure, drop packets for the congested queue immediately.
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* 2: both backpressure and drop.
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*/
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*/
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static int cong_drop = 0;
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static int cong_drop = 0;
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SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
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SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
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"Congestion control for RX queues (0 = backpressure, 1 = drop");
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"Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both");
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/*
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/*
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* Deliver multiple frames in the same free list buffer if they fit.
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* Deliver multiple frames in the same free list buffer if they fit.
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@ -554,7 +555,7 @@ t4_sge_modload(void)
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spg_len = len;
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spg_len = len;
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}
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}
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if (cong_drop < -1 || cong_drop > 1) {
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if (cong_drop < -1 || cong_drop > 2) {
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printf("Invalid hw.cxgbe.cong_drop value (%d),"
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printf("Invalid hw.cxgbe.cong_drop value (%d),"
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" using 0 instead.\n", cong_drop);
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" using 0 instead.\n", cong_drop);
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cong_drop = 0;
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cong_drop = 0;
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@ -3382,7 +3383,7 @@ init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
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iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
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iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
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iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
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iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
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iq->intr_idx = intr_idx;
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iq->intr_idx = intr_idx;
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iq->cong = cong;
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iq->cong_drop = cong;
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}
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}
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static inline void
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static inline void
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@ -3548,9 +3549,10 @@ free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
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static int
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static int
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alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
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alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
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{
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{
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int rc, i, cntxt_id;
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int rc, cntxt_id, cong_map;
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struct fw_iq_cmd c;
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struct fw_iq_cmd c;
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struct adapter *sc = vi->adapter;
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struct adapter *sc = vi->adapter;
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struct port_info *pi = vi->pi;
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__be32 v = 0;
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__be32 v = 0;
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MPASS (!(iq->flags & IQ_HW_ALLOCATED));
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MPASS (!(iq->flags & IQ_HW_ALLOCATED));
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@ -3582,15 +3584,17 @@ alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
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V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
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V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
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V_FW_IQ_CMD_VIID(vi->viid) |
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V_FW_IQ_CMD_VIID(vi->viid) |
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V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
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V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
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c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
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c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
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F_FW_IQ_CMD_IQGTSMODE |
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F_FW_IQ_CMD_IQGTSMODE |
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V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
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V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
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V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
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V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
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c.iqsize = htobe16(iq->qsize);
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c.iqsize = htobe16(iq->qsize);
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c.iqaddr = htobe64(iq->ba);
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c.iqaddr = htobe64(iq->ba);
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c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype));
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c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype));
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if (iq->cong >= 0)
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if (iq->cong_drop != -1) {
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cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0;
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c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
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c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
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}
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if (fl) {
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if (fl) {
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bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len);
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bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len);
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@ -3600,9 +3604,9 @@ alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
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(fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
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(fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
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(fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
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(fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
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0));
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0));
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if (iq->cong >= 0) {
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if (iq->cong_drop != -1) {
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c.iqns_to_fl0congen |=
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c.iqns_to_fl0congen |=
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htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(iq->cong) |
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htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) |
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F_FW_IQ_CMD_FL0CONGCIF |
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F_FW_IQ_CMD_FL0CONGCIF |
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F_FW_IQ_CMD_FL0CONGEN);
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F_FW_IQ_CMD_FL0CONGEN);
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}
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}
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@ -3636,6 +3640,8 @@ alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
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if (fl) {
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if (fl) {
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u_int qid;
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u_int qid;
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#ifdef INVARIANTS
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#ifdef INVARIANTS
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int i;
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MPASS(!(fl->flags & FL_BUF_RESUME));
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MPASS(!(fl->flags & FL_BUF_RESUME));
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for (i = 0; i < fl->sidx * 8; i++)
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for (i = 0; i < fl->sidx * 8; i++)
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MPASS(fl->sdesc[i].cl == NULL);
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MPASS(fl->sdesc[i].cl == NULL);
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@ -3675,28 +3681,10 @@ alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
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FL_UNLOCK(fl);
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FL_UNLOCK(fl);
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}
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}
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if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && iq->cong >= 0) {
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if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) &&
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uint32_t param, val;
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iq->cong_drop != -1) {
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t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop,
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param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
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cong_map);
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V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
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V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
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if (iq->cong == 0)
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val = 1 << 19;
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else {
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val = 2 << 19;
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for (i = 0; i < 4; i++) {
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if (iq->cong & (1 << i))
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val |= 1 << (i << 2);
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}
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}
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rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
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if (rc != 0) {
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/* report error but carry on */
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CH_ERR(sc, "failed to set congestion manager context "
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"for ingress queue %d: %d\n", iq->cntxt_id, rc);
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}
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}
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}
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/* Enable IQ interrupts */
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/* Enable IQ interrupts */
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@ -3920,15 +3908,57 @@ free_ctrlq(struct adapter *sc, int idx)
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}
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}
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int
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int
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tnl_cong(struct port_info *pi, int drop)
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t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop,
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int cong_map)
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{
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{
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const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log;
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uint32_t param, val;
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uint16_t ch_map;
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int cong_mode, rc, i;
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if (drop == -1)
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if (chip_id(sc) < CHELSIO_T5)
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return (-1);
|
return (ENOTSUP);
|
||||||
else if (drop == 1)
|
|
||||||
return (0);
|
/* Convert the driver knob to the mode understood by the firmware. */
|
||||||
else
|
switch (cong_drop) {
|
||||||
return (pi->rx_e_chan_map);
|
case -1:
|
||||||
|
cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE;
|
||||||
|
break;
|
||||||
|
case 0:
|
||||||
|
cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
cong_mode = X_CONMCTXT_CNGTPMODE_BOTH;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
MPASS(0);
|
||||||
|
CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n",
|
||||||
|
cong_drop, cntxt_id);
|
||||||
|
return (EINVAL);
|
||||||
|
}
|
||||||
|
|
||||||
|
param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
|
||||||
|
V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
|
||||||
|
V_FW_PARAMS_PARAM_YZ(cntxt_id);
|
||||||
|
val = V_CONMCTXT_CNGTPMODE(cong_mode);
|
||||||
|
if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL ||
|
||||||
|
cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) {
|
||||||
|
for (i = 0, ch_map = 0; i < 4; i++) {
|
||||||
|
if (cong_map & (1 << i))
|
||||||
|
ch_map |= 1 << (i << cng_ch_bits_log);
|
||||||
|
}
|
||||||
|
val |= V_CONMCTXT_CNGCHMAP(ch_map);
|
||||||
|
}
|
||||||
|
rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
|
||||||
|
if (rc != 0) {
|
||||||
|
CH_ERR(sc, "failed to set congestion manager context "
|
||||||
|
"for ingress queue %d: %d\n", cntxt_id, rc);
|
||||||
|
}
|
||||||
|
|
||||||
|
return (rc);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -3960,7 +3990,7 @@ alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx,
|
|||||||
"rx queue");
|
"rx queue");
|
||||||
|
|
||||||
init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq,
|
init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq,
|
||||||
intr_idx, tnl_cong(vi->pi, cong_drop), IQ_ETH);
|
intr_idx, cong_drop, IQ_ETH);
|
||||||
#if defined(INET) || defined(INET6)
|
#if defined(INET) || defined(INET6)
|
||||||
if (ifp->if_capenable & IFCAP_LRO)
|
if (ifp->if_capenable & IFCAP_LRO)
|
||||||
rxq->iq.flags |= IQ_LRO_ENABLED;
|
rxq->iq.flags |= IQ_LRO_ENABLED;
|
||||||
|
Loading…
Reference in New Issue
Block a user