UltraSPARC-IV CPUs seem to be affected by a not publicly documented
erratum causing them to trigger stray vector interrupts accompanied by a state in which they even fault on locked TLB entries. Just retrying the instruction in that case gets the CPU back on track though. OpenSolaris also just ignores a certain number of stray vector interrupts. While at it, implement the stray vector interrupt handling for SPARC64-VI which use these for indicating uncorrectable errors in interrupt packets.
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=223721
@ -585,7 +585,8 @@ END(tl0_sfsr_trap)
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andcc %g1, IRSR_BUSY, %g0
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bnz,a,pt %xcc, intr_vector
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nop
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sir
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ba,a,pt %xcc, intr_vector_stray
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nop
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.align 32
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.endm
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@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/intr_machdep.h>
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#include <machine/ktr.h>
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#include <machine/pstate.h>
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#include <machine/ver.h>
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#include "assym.s"
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@ -153,6 +154,29 @@ ENTRY(intr_vector)
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retry
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END(intr_vector)
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ENTRY(intr_vector_stray)
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/*
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* SPARC64-VI trigger stray vector interrupts in order to indicate
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* uncorrectable errors in interrupt packets, which still need to be
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* acknowledged though.
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* US-IV occasionally trigger stray vector interrupts for reasons
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* unknown accompanied by a state in which they even fault on locked
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* TLB entries so we can't even log these here. Just retrying the
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* instruction in that case gets the CPU back on track.
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*/
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rdpr %ver, %g1
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srlx %g1, VER_IMPL_SHIFT, %g1
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sll %g1, VER_IMPL_SIZE, %g1
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srl %g1, VER_IMPL_SIZE, %g1
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cmp %g1, CPU_IMPL_SPARC64VI
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bne,a,pn %icc, 1f
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nop
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stxa %g0, [%g0] ASI_INTR_RECEIVE
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membar #Sync
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1: retry
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END(intr_vector_stray)
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ENTRY(intr_fast)
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save %sp, -CCFSZ, %sp
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