UltraSPARC-IV CPUs seem to be affected by a not publicly documented

erratum causing them to trigger stray vector interrupts accompanied by a
state in which they even fault on locked TLB entries. Just retrying the
instruction in that case gets the CPU back on track though. OpenSolaris
also just ignores a certain number of stray vector interrupts.
While at it, implement the stray vector interrupt handling for SPARC64-VI
which use these for indicating uncorrectable errors in interrupt packets.

sys/sparc64/sparc64/exception.S

@@ -585,7 +585,8 @@ END(tl0_sfsr_trap)
 	andcc	%g1, IRSR_BUSY, %g0
 	bnz,a,pt %xcc, intr_vector
 	 nop
-	sir
+	ba,a,pt	%xcc, intr_vector_stray
+	 nop
 	.align	32
 	.endm
 

sys/sparc64/sparc64/interrupt.S

@@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/intr_machdep.h>
 #include <machine/ktr.h>
 #include <machine/pstate.h>
+#include <machine/ver.h>
 
 #include "assym.s"
 
@@ -153,6 +154,29 @@ ENTRY(intr_vector)
 	retry
 END(intr_vector)
 
+ENTRY(intr_vector_stray)
+	/*
+	 * SPARC64-VI trigger stray vector interrupts in order to indicate
+	 * uncorrectable errors in interrupt packets, which still need to be
+	 * acknowledged though.
+	 * US-IV occasionally trigger stray vector interrupts for reasons
+	 * unknown accompanied by a state in which they even fault on locked
+	 * TLB entries so we can't even log these here.  Just retrying the
+	 * instruction in that case gets the CPU back on track.
+	 */
+	rdpr	%ver, %g1
+	srlx	%g1, VER_IMPL_SHIFT, %g1
+	sll	%g1, VER_IMPL_SIZE, %g1
+	srl	%g1, VER_IMPL_SIZE, %g1
+	cmp	%g1, CPU_IMPL_SPARC64VI
+	bne,a,pn %icc, 1f
+	 nop
+	stxa	%g0, [%g0] ASI_INTR_RECEIVE
+	membar	#Sync
+
+1:	retry
+END(intr_vector_stray)
+
 ENTRY(intr_fast)
 	save	%sp, -CCFSZ, %sp