Add driver for Rockchip PCIe root complex found in RK3399 SOC.
Unfortunately, there are some limitations: - memory aperture of his controller is only 16MiB, so it is nearly unusable for graphic cards - every attempt to generate type 1 config cycle always causes trap. These config cycles are disabled now and we don't support cards with PCIe switch. - in some cases, attempt to do config cycle to (probably) not-yet ready card also causes trap. This cannot be detected at runtime, but it seems like very rare issue. MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D22724
This commit is contained in:
parent
cf69fe66d4
commit
dfd1d0fcab
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=355755
1411
sys/arm64/rockchip/rk_pcie.c
Normal file
1411
sys/arm64/rockchip/rk_pcie.c
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File diff suppressed because it is too large
Load Diff
369
sys/arm64/rockchip/rk_pcie_phy.c
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369
sys/arm64/rockchip/rk_pcie_phy.c
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@ -0,0 +1,369 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Rockchip PHY TYPEC
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/phy/phy.h>
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#include <dev/extres/phy/phy_internal.h>
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#include <dev/extres/syscon/syscon.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "syscon_if.h"
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#define GRF_HIWORD_SHIFT 16
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#define GRF_SOC_CON_5_PCIE 0xE214
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#define CON_5_PCIE_IDLE_OFF(x) (1 <<(((x) & 0x3) + 3))
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#define GRF_SOC_CON8 0xE220
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#define GRF_SOC_STATUS1 0xE2A4
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/* PHY config registers - write */
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#define PHY_CFG_CLK_TEST 0x10
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#define CLK_TEST_SEPE_RATE (1 << 3)
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#define PHY_CFG_CLK_SCC 0x12
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#define CLK_SCC_PLL_100M (1 << 3)
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/* PHY config registers - read */
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#define PHY_CFG_PLL_LOCK 0x10
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#define CLK_PLL_LOCKED (1 << 1)
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#define PHY_CFG_SCC_LOCK 0x12
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#define CLK_SCC_100M_GATE (1 << 2)
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#define STATUS1_PLL_LOCKED (1 << 9)
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static struct ofw_compat_data compat_data[] = {
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{"rockchip,rk3399-pcie-phy", 1},
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{NULL, 0}
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};
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struct rk_pcie_phy_softc {
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device_t dev;
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struct syscon *syscon;
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struct mtx mtx;
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clk_t clk_ref;
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hwreset_t hwreset_phy;
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int enable_count;
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};
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#define PHY_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define PHY_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define PHY_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
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device_get_nameunit(_sc->dev), "rk_pcie_phyc", MTX_DEF)
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#define PHY_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
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#define PHY_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
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#define PHY_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
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#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))
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#define WR4(sc, reg, mask, val) \
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SYSCON_WRITE_4((sc)->syscon, (reg), ((mask) << GRF_HIWORD_SHIFT) | (val))
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#define MAX_LANE 4
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static void
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cfg_write(struct rk_pcie_phy_softc *sc, uint32_t reg, uint32_t data)
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{
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/* setup register address and data first */
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WR4(sc, GRF_SOC_CON8, 0x7FF,
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(reg & 0x3F) << 1 | (data & 0x0F) << 7);
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/* dummy readback for sync */
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RD4(sc, GRF_SOC_CON8);
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/* Do write pulse */
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WR4(sc, GRF_SOC_CON8, 1, 1);
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RD4(sc, GRF_SOC_CON8);
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DELAY(10);
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WR4(sc, GRF_SOC_CON8, 1, 0);
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RD4(sc, GRF_SOC_CON8);
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DELAY(10);
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}
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static uint32_t
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cfg_read(struct rk_pcie_phy_softc *sc, uint32_t reg)
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{
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uint32_t val;
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WR4(sc, GRF_SOC_CON8, 0x3FF, reg << 1);
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RD4(sc, GRF_SOC_CON8);
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DELAY(10);
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val = RD4(sc, GRF_SOC_STATUS1);
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return ((val >> 8) & 0x0f);
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}
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static int
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rk_pcie_phy_up(struct rk_pcie_phy_softc *sc, int id)
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{
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uint32_t val;
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int i, rv;
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PHY_LOCK(sc);
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sc->enable_count++;
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if (sc->enable_count != 1) {
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PHY_UNLOCK(sc);
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return (0);
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}
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rv = hwreset_deassert(sc->hwreset_phy);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot deassert 'phy' reset\n");
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PHY_UNLOCK(sc);
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return (rv);
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}
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/* Un-idle all lanes */
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for (i = 0; i < MAX_LANE; i++)
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WR4(sc, GRF_SOC_CON_5_PCIE, CON_5_PCIE_IDLE_OFF(i), 0);
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/* Wait for PLL lock */
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for (i = 100; i > 0; i--) {
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val = cfg_read(sc, PHY_CFG_PLL_LOCK);
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if (val & CLK_PLL_LOCKED)
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break;
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DELAY(1000);
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}
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if (i <= 0) {
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device_printf(sc->dev, "PLL lock timeouted, 0x%02X\n", val);
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PHY_UNLOCK(sc);
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return (ETIMEDOUT);
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}
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/* Switch PLL to stable 5GHz, rate adjustment is done by divider */
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cfg_write(sc, PHY_CFG_CLK_TEST, CLK_TEST_SEPE_RATE);
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/* Enable 100MHz output for PCIe ref clock */
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cfg_write(sc, PHY_CFG_CLK_SCC, CLK_SCC_PLL_100M);
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/* Wait for ungating of ref clock */
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for (i = 100; i > 0; i--) {
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val = cfg_read(sc, PHY_CFG_SCC_LOCK);
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if ((val & CLK_SCC_100M_GATE) == 0)
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break;
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DELAY(1000);
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}
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if (i <= 0) {
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device_printf(sc->dev, "PLL output enable timeouted\n");
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PHY_UNLOCK(sc);
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return (ETIMEDOUT);
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}
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/* Wait for PLL relock (to 5GHz) */
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for (i = 100; i > 0; i--) {
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val = cfg_read(sc, PHY_CFG_PLL_LOCK);
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if (val & CLK_PLL_LOCKED)
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break;
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DELAY(1000);
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}
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if (i <= 0) {
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device_printf(sc->dev, "PLL relock timeouted\n");
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PHY_UNLOCK(sc);
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return (ETIMEDOUT);
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}
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PHY_UNLOCK(sc);
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return (rv);
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}
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static int
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rk_pcie_phy_down(struct rk_pcie_phy_softc *sc, int id)
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{
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int rv;
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PHY_LOCK(sc);
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rv = 0;
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if (sc->enable_count <= 0)
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panic("unpaired enable/disable");
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sc->enable_count--;
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/* Idle given lane */
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WR4(sc, GRF_SOC_CON_5_PCIE,
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CON_5_PCIE_IDLE_OFF(id),
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CON_5_PCIE_IDLE_OFF(id));
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if (sc->enable_count == 0) {
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rv = hwreset_assert(sc->hwreset_phy);
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if (rv != 0)
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device_printf(sc->dev, "Cannot assert 'phy' reset\n");
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}
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PHY_UNLOCK(sc);
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return (rv);
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}
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static int
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rk_pcie_phy_enable(struct phynode *phynode, bool enable)
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{
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struct rk_pcie_phy_softc *sc;
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device_t dev;
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intptr_t phy;
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int rv;
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dev = phynode_get_device(phynode);
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phy = phynode_get_id(phynode);
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sc = device_get_softc(dev);
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if (enable)
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rv = rk_pcie_phy_up(sc, (int)phy);
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else
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rv = rk_pcie_phy_down(sc, (int) phy);
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return (rv);
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}
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/* Phy class and methods. */
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static int rk_pcie_phy_enable(struct phynode *phynode, bool enable);
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static phynode_method_t rk_pcie_phy_phynode_methods[] = {
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PHYNODEMETHOD(phynode_enable, rk_pcie_phy_enable),
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PHYNODEMETHOD_END
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};
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DEFINE_CLASS_1( rk_pcie_phy_phynode, rk_pcie_phy_phynode_class,
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rk_pcie_phy_phynode_methods, 0, phynode_class);
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static int
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rk_pcie_phy_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Rockchip RK3399 PCIe PHY");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rk_pcie_phy_attach(device_t dev)
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{
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struct rk_pcie_phy_softc *sc;
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struct phynode_init_def phy_init;
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struct phynode *phynode;
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phandle_t node;
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int i, rv;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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PHY_LOCK_INIT(sc);
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if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||
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sc->syscon == NULL) {
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device_printf(dev, "cannot get syscon for device\n");
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rv = ENXIO;
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goto fail;
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}
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rv = clk_get_by_ofw_name(sc->dev, 0, "refclk", &sc->clk_ref);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'refclk' clock\n");
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rv = ENXIO;
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goto fail;
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}
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rv = hwreset_get_by_ofw_name(sc->dev, 0, "phy", &sc->hwreset_phy);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'phy' reset\n");
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rv = ENXIO;
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goto fail;
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}
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rv = hwreset_assert(sc->hwreset_phy);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot assert 'phy' reset\n");
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rv = ENXIO;
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goto fail;
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}
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rv = clk_enable(sc->clk_ref);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot enable 'ref' clock\n");
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rv = ENXIO;
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goto fail;
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}
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for (i = 0; i < MAX_LANE; i++) {
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phy_init.id = i;
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phy_init.ofw_node = node;
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phynode = phynode_create(dev, &rk_pcie_phy_phynode_class,
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&phy_init);
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if (phynode == NULL) {
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device_printf(dev, "Cannot create phy[%d]\n", i);
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rv = ENXIO;
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goto fail;
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}
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if (phynode_register(phynode) == NULL) {
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device_printf(dev, "Cannot register phy[%d]\n", i);
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rv = ENXIO;
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goto fail;
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}
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}
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return (0);
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fail:
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return (rv);
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}
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static device_method_t rk_pcie_phy_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, rk_pcie_phy_probe),
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DEVMETHOD(device_attach, rk_pcie_phy_attach),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(rk_pcie_phy, rk_pcie_phy_driver, rk_pcie_phy_methods,
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sizeof(struct rk_pcie_phy_softc));
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static devclass_t rk_pcie_phy_devclass;
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EARLY_DRIVER_MODULE(rk_pcie_phy, simplebus, rk_pcie_phy_driver,
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rk_pcie_phy_devclass, NULL, NULL,
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BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
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@ -311,6 +311,8 @@ arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399
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arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
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arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399
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arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399
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arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399
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arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399
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dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
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dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
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