Update the SATA support code to work more correctly with
real SATA disks now that I can test it. Add support for the SiI 3112 SATA chip using memory mapped I/O. Update the support for the SiI 0680 to use the memio interface as well. Sponsored by: David Leimbach <leimy2k@mac.com> (3112 based controller) Sponsored by: FreeBSD Systems (www.FreeBSDsystems.com) (SATA disks)
This commit is contained in:
Søren Schmidt
parent
fedbfbbbc6
commit
e158f2b820
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=117155
@ -93,6 +93,8 @@ static int ata_promise_mio_dmastop(struct ata_channel *);
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static int ata_serverworks_chipinit(device_t);
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static void ata_serverworks_setmode(struct ata_device *, int);
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static int ata_sii_chipinit(device_t);
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static int ata_sii_mio_allocate(device_t, struct ata_channel *);
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static void ata_sii_intr(void *);
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static void ata_cmd_intr(void *);
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static void ata_sii_setmode(struct ata_device *, int);
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static void ata_cmd_setmode(struct ata_device *, int);
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@ -838,11 +840,6 @@ ata_intel_new_setmode(struct ata_device *atadev, int mode)
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mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
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if (mode >= ATA_SA150) {
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atadev->mode = mode;
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return;
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}
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if (ctlr->chip->max_dma && mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
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ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
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mode = ATA_UDMA2;
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@ -854,7 +851,10 @@ ata_intel_new_setmode(struct ata_device *atadev, int mode)
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ata_prtdev(atadev, "%s setting %s on %s chip\n",
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(error) ? "failed" : "success",
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ata_mode2str(mode), ctlr->chip->text);
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if (!error) {
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if (error)
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return;
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if (ctlr->chip->max_dma < ATA_SA150) {
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if (mode >= ATA_UDMA0) {
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pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
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pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
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@ -894,8 +894,8 @@ ata_intel_new_setmode(struct ata_device *atadev, int mode)
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}
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pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
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pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
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atadev->mode = mode;
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}
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atadev->mode = mode;
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}
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/*
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@ -1244,11 +1244,6 @@ ata_promise_setmode(struct ata_device *atadev, int mode)
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break;
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}
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if (mode >= ATA_SA150) {
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atadev->mode = mode;
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return;
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}
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error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
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ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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@ -1458,11 +1453,12 @@ ata_sii_ident(device_t dev)
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_SII0680, 0x00, 0, SII_SETCLK, ATA_UDMA6, "SiI 0680" },
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{ ATA_CMD649, 0x00, 0, SII_INTR|SII_ENINTR, ATA_UDMA5, "CMD 649" },
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{ ATA_CMD648, 0x00, 0, SII_INTR|SII_ENINTR, ATA_UDMA4, "CMD 648" },
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{ ATA_CMD646, 0x07, 0, SII_ENINTR, ATA_UDMA2, "CMD 646U2" },
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{ ATA_CMD646, 0x00, 0, SII_ENINTR, ATA_WDMA2, "CMD 646" },
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{{ ATA_SII3112, 0x00, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
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{ ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
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{ ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
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{ ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
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{ ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
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{ ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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@ -1487,37 +1483,104 @@ ata_sii_chipinit(device_t dev)
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device_printf(dev, "unable to map interrupt\n");
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return ENXIO;
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}
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if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
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ctlr->chip->cfg2 & SII_INTR ?
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ata_cmd_intr : ata_generic_intr,
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ctlr, &ctlr->handle))) {
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device_printf(dev, "unable to setup interrupt\n");
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return ENXIO;
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}
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if (ctlr->chip->cfg2 & SII_ENINTR)
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pci_write_config(dev, 0x71, 0x01, 1);
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if (ctlr->chip->cfg1 == SIIMEMIO) {
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if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
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ata_sii_intr, ctlr, &ctlr->handle))) {
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device_printf(dev, "unable to setup interrupt\n");
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return ENXIO;
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}
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rid = 0x24;
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if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
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0, ~0, 1, RF_ACTIVE)))
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return ENXIO;
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if (ctlr->chip->cfg2 & SII_SETCLK) {
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if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
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pci_write_config(dev, 0x8a,
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(pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
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if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
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device_printf(dev, "%s could not set ATA133 clock\n",
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ctlr->chip->text);
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if (ctlr->chip->cfg2 & SIISETCLK) {
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if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
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pci_write_config(dev, 0x8a,
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(pci_read_config(dev, 0x8a, 1) & 0x0F)|0x10,1);
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if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
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device_printf(dev, "%s could not set ATA133 clock\n",
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ctlr->chip->text);
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}
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ctlr->allocate = ata_sii_mio_allocate;
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ctlr->setmode = ata_sii_setmode;
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}
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else
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ctlr->setmode = ata_cmd_setmode;
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else {
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if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
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ctlr->chip->cfg2 & SIIINTR ?
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ata_cmd_intr : ata_generic_intr,
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ctlr, &ctlr->handle))) {
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device_printf(dev, "unable to setup interrupt\n");
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return ENXIO;
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}
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if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
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device_printf(dev, "secondary channel disabled\n");
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ctlr->channels = 1;
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}
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if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
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device_printf(dev, "HW has secondary channel disabled\n");
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ctlr->channels = 1;
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}
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/* enable interrupt as BIOS might not */
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pci_write_config(dev, 0x71, 0x01, 1);
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ctlr->setmode = ata_cmd_setmode;
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}
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return 0;
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}
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static int
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ata_sii_mio_allocate(device_t dev, struct ata_channel *ch)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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int i;
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for (i = ATA_DATA; i <= ATA_STATUS; i++) {
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ch->r_io[i].res = ctlr->r_io2;
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ch->r_io[i].offset = 0x80 + i + (ch->unit << 6);
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}
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ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
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ch->r_io[ATA_ALTSTAT].offset = 0x8a + (ch->unit << 6);
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ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_io2;
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ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (ch->unit << 3);
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ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_io2;
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ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (ch->unit << 3);
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ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
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ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (ch->unit << 3);
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ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
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ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (ch->unit << 6);
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ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
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if (ctlr->chip->max_dma >= ATA_SA150)
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ch->flags |= ATA_NO_SLAVE;
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ctlr->dmainit(ch);
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return 0;
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}
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static void
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ata_sii_intr(void *data)
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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u_int8_t dmastat;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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for (unit = 0; unit < 2; unit++) {
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
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if (ch->dma->flags & ATA_DMA_ACTIVE) {
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if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
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ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
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DELAY(1);
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}
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ctlr->interrupt[unit].function(ch);
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}
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}
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}
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static void
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ata_cmd_intr(void *data)
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{
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@ -1551,7 +1614,7 @@ ata_sii_setmode(struct ata_device *atadev, int mode)
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{
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device_t parent = device_get_parent(atadev->channel->dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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int devno = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
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int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
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int mreg = atadev->channel->unit ? 0x84 : 0x80;
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int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
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int mval = pci_read_config(parent, mreg, 1) & ~mask;
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@ -1559,7 +1622,8 @@ ata_sii_setmode(struct ata_device *atadev, int mode)
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mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
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mode = ata_check_80pin(atadev, mode);
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if (ctlr->chip->max_dma < ATA_SA150)
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mode = ata_check_80pin(atadev, mode);
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error = ata_command(atadev, ATA_C_SETFEATURES, 0, mode,
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ATA_C_F_SETXFER, ATA_WAIT_READY);
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@ -1567,20 +1631,24 @@ ata_sii_setmode(struct ata_device *atadev, int mode)
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ata_prtdev(atadev, "%s setting %s on %s chip\n",
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(error) ? "failed" : "success",
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ata_mode2str(mode), ctlr->chip->text);
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if (!error) {
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if (error)
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return;
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if (ctlr->chip->max_dma < ATA_SA150) {
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if (mode >= ATA_UDMA0) {
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u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
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u_int8_t ureg = 0xac + devno;
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u_int8_t ureg = 0xac + rego;
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pci_write_config(parent, mreg,
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mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
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pci_write_config(parent, ureg,
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(pci_read_config(parent, ureg, 1) & 0x3f) |
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(pci_read_config(parent, ureg, 1) & ~0x3f) |
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udmatimings[mode & ATA_MODE_MASK], 1);
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}
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else if (mode >= ATA_WDMA0) {
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u_int8_t dreg = 0xa8 + devno;
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u_int8_t dreg = 0xa8 + rego;
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u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
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pci_write_config(parent, mreg,
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@ -1589,15 +1657,15 @@ ata_sii_setmode(struct ata_device *atadev, int mode)
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}
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else {
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u_int8_t preg = 0xa4 + devno;
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u_int8_t preg = 0xa4 + rego;
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u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
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pci_write_config(parent, mreg,
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mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
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pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
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}
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atadev->mode = mode;
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}
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atadev->mode = mode;
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}
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static void
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@ -152,18 +152,13 @@ ata_pci_attach(device_t dev)
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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}
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#endif
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/* is busmastering supported and configured ? */
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/* if busmastering configured get the I/O resource */
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if ((cmd & PCIM_CMD_BUSMASTEREN) == PCIM_CMD_BUSMASTEREN) {
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int rid = ATA_BMADDR_RID;
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if (!ctlr->r_io2) {
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if (!(ctlr->r_io1 = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
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0, ~0, 1, RF_ACTIVE)))
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device_printf(dev, "Busmastering DMA not configured\n");
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}
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ctlr->r_io1 = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
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0, ~0, 1, RF_ACTIVE);
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}
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else
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device_printf(dev, "Busmastering DMA not supported\n");
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ctlr->chipinit(dev);
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@ -154,6 +154,7 @@ struct ata_pci_controller {
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#define ATA_SILICON_IMAGE_ID 0x1095
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#define ATA_SII0680 0x06801095
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#define ATA_SII3112 0x31121095
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#define ATA_CMD646 0x06461095
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#define ATA_CMD648 0x06481095
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#define ATA_CMD649 0x06491095
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@ -242,9 +243,9 @@ struct ata_pci_controller {
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#define SWKS66 1
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#define SWKS100 2
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#define SII_INTR 0x01
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#define SII_SETCLK 0x02
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#define SII_ENINTR 0x04
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#define SIIMEMIO 1
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#define SIIINTR 0x01
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#define SIISETCLK 0x02
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#define SIS_SOUTH 1
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#define SIS133NEW 2
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