From e1a5a8a74add9e8b580df228e15048a8e6329763 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 7 Oct 2013 16:33:16 +0000 Subject: [PATCH] Add support for assembling and disassembling Intel Random Number Generator extensions (e.g. the 'rdrand' mnemonic) to our copy of binutils. Approved by: re (kib) Obtained from: OpenBSD, via pfg MFC after: 1 week --- contrib/binutils/opcodes/i386-dis.c | 22 +++++++++++++++------- contrib/binutils/opcodes/i386-opc.h | 3 ++- contrib/binutils/opcodes/i386-opc.tbl | 18 ++++++++++++++++++ contrib/binutils/opcodes/i386-tbl.h | 5 +++++ 4 files changed, 40 insertions(+), 8 deletions(-) diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c index eb33089a407f..a13421304568 100644 --- a/contrib/binutils/opcodes/i386-dis.c +++ b/contrib/binutils/opcodes/i386-dis.c @@ -6438,14 +6438,22 @@ VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) static void OP_VMX (int bytemode, int sizeflag) { - used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ)); - if (prefixes & PREFIX_DATA) - strcpy (obuf, "vmclear"); - else if (prefixes & PREFIX_REPZ) - strcpy (obuf, "vmxon"); + if (modrm.mod == 3) + { + strcpy (obuf, "rdrand"); + OP_E (v_mode, sizeflag); + } else - strcpy (obuf, "vmptrld"); - OP_E (bytemode, sizeflag); + { + used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ)); + if (prefixes & PREFIX_DATA) + strcpy (obuf, "vmclear"); + else if (prefixes & PREFIX_REPZ) + strcpy (obuf, "vmxon"); + else + strcpy (obuf, "vmptrld"); + OP_E (bytemode, sizeflag); + } } static void diff --git a/contrib/binutils/opcodes/i386-opc.h b/contrib/binutils/opcodes/i386-opc.h index 27c1dab2aaea..8d6fd8a15f95 100644 --- a/contrib/binutils/opcodes/i386-opc.h +++ b/contrib/binutils/opcodes/i386-opc.h @@ -79,6 +79,7 @@ typedef struct template #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ #define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */ +#define CpuRdRnd 0x20000000 /* Intel Random Number Generator extensions */ /* SSE4.1/4.2 Instructions required */ #define CpuSSE4 (CpuSSE4_1|CpuSSE4_2) @@ -87,7 +88,7 @@ typedef struct template #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \ - |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL) + |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd) /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of diff --git a/contrib/binutils/opcodes/i386-opc.tbl b/contrib/binutils/opcodes/i386-opc.tbl index 6cb72199fd48..ea188ddca8f0 100644 --- a/contrib/binutils/opcodes/i386-opc.tbl +++ b/contrib/binutils/opcodes/i386-opc.tbl @@ -1502,3 +1502,21 @@ xrstor, 1, 0xfae, 0x5, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, // INVPCID invpcid, 2, 0x660f3882, None, CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } invpcid, 2, 0x660f3882, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } + +// Intel AES extensions +aesdec, 2, 0x660f38de, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM } +aesdeclast, 2, 0x660f38df, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM } +aesenc, 2, 0x660f38dc, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM } +aesenclast, 2, 0x660f38dd, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM } +aesimc, 2, 0x660f38db, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM } +aeskeygenassist, 3, 0x660f3adf, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM } + +// Intel Carry-less Multiplication extensions +pclmulqdq, 3, 0x660f3a44, None, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM } +pclmullqlqdq, 2, 0x660f3a44, 0x0, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM } +pclmulhqlqdq, 2, 0x660f3a44, 0x1, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM } +pclmullqhqdq, 2, 0x660f3a44, 0x10, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM } +pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM } + +// Intel Random Number Generator extensions +rdrand, 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } diff --git a/contrib/binutils/opcodes/i386-tbl.h b/contrib/binutils/opcodes/i386-tbl.h index c42f56591bc3..ec19f109ae40 100644 --- a/contrib/binutils/opcodes/i386-tbl.h +++ b/contrib/binutils/opcodes/i386-tbl.h @@ -4374,6 +4374,11 @@ const template i386_optab[] = Modrm|IgnoreSize|NoSuf|ImmExt, { RegXMM|LLongMem, RegXMM } }, + + /* Intel Random Number Generator extensions */ + {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd, + Modrm|NoSuf, + { Reg16|Reg32|Reg64 } }, { NULL, 0, 0, 0, 0, 0, { 0 } } };