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gicv3_its: Flush cache after allocating ITT memory

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It has to be zeroed before committing it to device.
We do that by allocating it with M_ZERO, but there was no
memory barrier or cache flush to ensure its sees it zeroed.
This fixes MSIX on LS1028A SoC.

Submitted by: Kornel Duleba <mindal@semihalf.com>
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Alstom Group
Differential Revision: https://reviews.freebsd.org/D30033
This commit is contained in:
Marcin Wojtas 2021-04-29 11:39:09 +02:00
parent 2f32a971b7
commit e245ee2774
1 changed files with 4 additions and 0 deletions
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4
sys/arm64/arm64/gicv3_its.c
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@ -1197,6 +1197,10 @@ its_device_get(device_t dev, device_t child, u_int nvecs)
return (NULL);
}
/* Make sure device sees zeroed ITT. */
if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0)
cpu_dcache_wb_range(its_dev->itt, its_dev->itt_size);
mtx_lock_spin(&sc->sc_its_dev_lock);
TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
mtx_unlock_spin(&sc->sc_its_dev_lock);