gicv3_its: Flush cache after allocating ITT memory
It has to be zeroed before committing it to device. We do that by allocating it with M_ZERO, but there was no memory barrier or cache flush to ensure its sees it zeroed. This fixes MSIX on LS1028A SoC. Submitted by: Kornel Duleba <mindal@semihalf.com> Reviewed by: andrew Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D30033
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@ -1197,6 +1197,10 @@ its_device_get(device_t dev, device_t child, u_int nvecs)
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return (NULL);
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return (NULL);
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}
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}
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/* Make sure device sees zeroed ITT. */
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if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0)
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cpu_dcache_wb_range(its_dev->itt, its_dev->itt_size);
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mtx_lock_spin(&sc->sc_its_dev_lock);
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mtx_lock_spin(&sc->sc_its_dev_lock);
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TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
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TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
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mtx_unlock_spin(&sc->sc_its_dev_lock);
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mtx_unlock_spin(&sc->sc_its_dev_lock);
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