sfxge(4): support EVQ timer workaround via MCDI
Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. MFC after: 1 week Differential Revision: https://reviews.freebsd.org/6675
This commit is contained in:
parent
57dbe10e6d
commit
e26f5dac7f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=301237
@ -86,6 +86,52 @@ ef10_ev_mcdi(
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__in_opt void *arg);
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static __checkReturn efx_rc_t
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efx_mcdi_set_evq_tmr(
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__in efx_nic_t *enp,
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__in uint32_t instance,
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__in uint32_t mode,
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__in uint32_t timer_ns)
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{
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efx_mcdi_req_t req;
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uint8_t payload[MAX(MC_CMD_SET_EVQ_TMR_IN_LEN,
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MC_CMD_SET_EVQ_TMR_OUT_LEN)];
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efx_rc_t rc;
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(void) memset(payload, 0, sizeof (payload));
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req.emr_cmd = MC_CMD_SET_EVQ_TMR;
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req.emr_in_buf = payload;
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req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
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req.emr_out_buf = payload;
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req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
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MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
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MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
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MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
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MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
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efx_mcdi_execute(enp, &req);
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if (req.emr_rc != 0) {
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rc = req.emr_rc;
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goto fail1;
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}
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if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
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rc = EMSGSIZE;
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goto fail2;
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}
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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static __checkReturn efx_rc_t
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efx_mcdi_init_evq(
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__in efx_nic_t *enp,
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@ -437,9 +483,19 @@ ef10_ev_qmoderate(
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efx_nic_t *enp = eep->ee_enp;
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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efx_dword_t dword;
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uint32_t timer_val, mode;
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uint32_t timer_ns, timer_val, mode;
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efx_rc_t rc;
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/* Check that hardware and MCDI use the same timer MODE values */
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EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
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MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
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EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
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MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
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EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
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MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
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EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
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MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
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if (us > encp->enc_evq_timer_max_us) {
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rc = EINVAL;
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goto fail1;
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@ -447,37 +503,46 @@ ef10_ev_qmoderate(
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/* If the value is zero then disable the timer */
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if (us == 0) {
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timer_val = 0;
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timer_ns = 0;
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mode = FFE_CZ_TIMER_MODE_DIS;
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} else {
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timer_ns = us * 1000u;
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mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
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}
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if (encp->enc_bug61265_workaround) {
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rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, timer_ns);
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if (rc != 0)
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goto fail2;
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} else {
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/* Calculate the timer value in quanta */
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timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
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timer_val = timer_ns / encp->enc_evq_timer_quantum_ns;
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/* Moderation value is base 0 so we need to deduct 1 */
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if (timer_val > 0)
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timer_val--;
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mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
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}
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if (encp->enc_bug35388_workaround) {
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EFX_POPULATE_DWORD_3(dword,
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ERF_DD_EVQ_IND_TIMER_FLAGS,
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EFE_DD_EVQ_IND_TIMER_FLAGS,
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ERF_DD_EVQ_IND_TIMER_MODE, mode,
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ERF_DD_EVQ_IND_TIMER_VAL, timer_val);
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EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
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eep->ee_index, &dword, 0);
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} else {
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EFX_POPULATE_DWORD_2(dword,
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ERF_DZ_TC_TIMER_MODE, mode,
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ERF_DZ_TC_TIMER_VAL, timer_val);
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EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
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eep->ee_index, &dword, 0);
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if (encp->enc_bug35388_workaround) {
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EFX_POPULATE_DWORD_3(dword,
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ERF_DD_EVQ_IND_TIMER_FLAGS,
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EFE_DD_EVQ_IND_TIMER_FLAGS,
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ERF_DD_EVQ_IND_TIMER_MODE, mode,
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ERF_DD_EVQ_IND_TIMER_VAL, timer_val);
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EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
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eep->ee_index, &dword, 0);
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} else {
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EFX_POPULATE_DWORD_2(dword,
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ERF_DZ_TC_TIMER_MODE, mode,
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ERF_DZ_TC_TIMER_VAL, timer_val);
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EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
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eep->ee_index, &dword, 0);
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}
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}
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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@ -1129,6 +1129,7 @@ typedef struct efx_nic_cfg_s {
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boolean_t enc_bug26807_workaround;
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boolean_t enc_bug35388_workaround;
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boolean_t enc_bug41750_workaround;
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boolean_t enc_bug61265_workaround;
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boolean_t enc_rx_batching_enabled;
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/* Maximum number of descriptors completed in an rx event. */
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uint32_t enc_rx_batch_max;
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@ -291,6 +291,8 @@ hunt_board_cfg(
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FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
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}
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encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
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/* Check capabilities of running datapath firmware */
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if ((rc = ef10_get_datapath_caps(enp)) != 0)
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goto fail12;
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@ -227,6 +227,23 @@ medford_board_cfg(
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epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
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epp->ep_adv_cap_mask = els.els_adv_cap_mask;
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/*
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* Enable firmware workarounds for hardware errata.
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* Expected responses are:
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* - 0 (zero):
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* Success: workaround enabled or disabled as requested.
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* - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
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* Firmware does not support the MC_CMD_WORKAROUND request.
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* (assume that the workaround is not supported).
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* - MC_CMD_ERR_ENOENT (reported as ENOENT):
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* Firmware does not support the requested workaround.
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* - MC_CMD_ERR_EPERM (reported as EACCES):
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* Unprivileged function cannot enable/disable workarounds.
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*
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* See efx_mcdi_request_errcode() for MCDI error translations.
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*/
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if (EFX_PCI_FUNCTION_IS_VF(encp)) {
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/*
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* Interrupt testing does not work for VFs. See bug50084.
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@ -238,9 +255,23 @@ medford_board_cfg(
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/* Chained multicast is always enabled on Medford */
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encp->enc_bug26807_workaround = B_TRUE;
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/*
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* If the bug61265 workaround is enabled, then interrupt holdoff timers
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* cannot be controlled by timer table writes, so MCDI must be used
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* (timer table writes can still be used for wakeup timers).
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*/
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rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
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NULL);
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if ((rc == 0) || (rc == EACCES))
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encp->enc_bug61265_workaround = B_TRUE;
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else if ((rc == ENOTSUP) || (rc == ENOENT))
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encp->enc_bug61265_workaround = B_FALSE;
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else
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goto fail8;
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/* Get clock frequencies (in MHz). */
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if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
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goto fail8;
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goto fail9;
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/*
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* The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
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@ -252,14 +283,14 @@ medford_board_cfg(
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/* Check capabilities of running datapath firmware */
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if ((rc = ef10_get_datapath_caps(enp)) != 0)
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goto fail9;
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goto fail10;
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/* Alignment for receive packet DMA buffers */
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encp->enc_rx_buf_align_start = 1;
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/* Get the RX DMA end padding alignment configuration */
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if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0)
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goto fail10;
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goto fail11;
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encp->enc_rx_buf_align_end = end_padding;
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/* Alignment for WPTR updates */
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@ -288,13 +319,13 @@ medford_board_cfg(
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* can result in time-of-check/time-of-use bugs.
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*/
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if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
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goto fail11;
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goto fail12;
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encp->enc_privilege_mask = mask;
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/* Get interrupt vector limits */
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if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
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if (EFX_PCI_FUNCTION_IS_PF(encp))
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goto fail12;
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goto fail13;
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/* Ignore error (cannot query vector limits from a VF). */
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base = 0;
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@ -317,12 +348,14 @@ medford_board_cfg(
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rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
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if (rc != 0)
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goto fail13;
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goto fail14;
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encp->enc_required_pcie_bandwidth_mbps = bandwidth;
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encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
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return (0);
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fail14:
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EFSYS_PROBE(fail14);
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fail13:
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EFSYS_PROBE(fail13);
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fail12:
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