cxgbe(4): Allow for different pad and pack boundaries for different
adapters. Set the pack boundary for T5 cards to be the same as the PCIe max payload size. The chip likes it this way. In this revision the driver allocate rx buffers that align on both boundaries. This is not a strict requirement and a followup commit will switch the driver to a more relaxed allocation strategy. MFC after: 2 weeks
This commit is contained in:
Navdeep Parhar
parent
dbfbf4a8af
commit
e3207e1973
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=275539
@ -148,7 +148,7 @@ enum {
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#else
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SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
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#endif
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CL_METADATA_SIZE = CACHE_LINE_SIZE,
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CL_METADATA_SIZE = 256, /* same as MSIZE for now */
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SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
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TX_SGL_SEGS = 36,
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@ -695,6 +695,7 @@ struct sge {
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struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
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struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
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int pad_boundary;
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int pack_boundary;
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int8_t safe_hwidx1; /* may not have room for metadata */
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int8_t safe_hwidx2; /* with room for metadata and maybe more */
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@ -120,19 +120,10 @@ TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
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/*
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* Start next frame in a packed buffer at this boundary.
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* -1: driver should figure out a good value.
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* T4:
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* ---
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* if fl_pad != 0
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* value specified here will be overridden by fl_pad.
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* else
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* power of 2 from 32 to 4096 (both inclusive) is a valid value here.
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* T5:
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* ---
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* 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
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* T4: driver will ignore this and use the same value as fl_pad above.
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* T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
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*/
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static int fl_pack = -1;
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static int t4_fl_pack;
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static int t5_fl_pack;
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TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
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/*
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@ -175,8 +166,7 @@ static int service_iq(struct sge_iq *, int);
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static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
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static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
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static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
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static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int,
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char *);
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static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
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static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t,
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char *);
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static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
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@ -264,15 +254,6 @@ static counter_u64_t extfree_rels;
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void
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t4_sge_modload(void)
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{
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int pad;
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/* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */
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#if defined(__i386__) || defined(__amd64__)
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pad = max(cpu_clflush_line_size, 16);
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#else
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pad = max(CACHE_LINE_SIZE, 16);
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#endif
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pad = min(pad, 4096);
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if (fl_pktshift < 0 || fl_pktshift > 7) {
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printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
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@ -280,35 +261,6 @@ t4_sge_modload(void)
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fl_pktshift = 2;
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}
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if (fl_pad != 0 &&
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(fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) {
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if (fl_pad != -1) {
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printf("Invalid hw.cxgbe.fl_pad value (%d),"
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" using %d instead.\n", fl_pad, max(pad, 32));
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}
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fl_pad = max(pad, 32);
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}
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/*
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* T4 has the same pad and pack boundary. If a pad boundary is set,
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* pack boundary must be set to the same value. Otherwise take the
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* specified value or auto-calculate something reasonable.
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*/
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if (fl_pad)
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t4_fl_pack = fl_pad;
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else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack))
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t4_fl_pack = max(pad, 32);
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else
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t4_fl_pack = fl_pack;
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/* T5's pack boundary is independent of the pad boundary. */
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if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
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!powerof2(fl_pack))
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t5_fl_pack = max(pad, CACHE_LINE_SIZE);
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else
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t5_fl_pack = fl_pack;
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if (spg_len != 64 && spg_len != 128) {
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int len;
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@ -366,6 +318,71 @@ t4_init_sge_cpl_handlers(struct adapter *sc)
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t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
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}
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static inline void
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setup_pad_and_pack_boundaries(struct adapter *sc)
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{
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uint32_t v, m;
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int pad, pack;
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pad = fl_pad;
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if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
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/*
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* If there is any chance that we might use buffer packing and
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* the chip is a T4, then pick 64 as the pad/pack boundary. Set
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* it to 32 in all other cases.
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*/
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pad = is_t4(sc) && buffer_packing ? 64 : 32;
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/*
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* For fl_pad = 0 we'll still write a reasonable value to the
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* register but all the freelists will opt out of padding.
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* We'll complain here only if the user tried to set it to a
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* value greater than 0 that was invalid.
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*/
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if (fl_pad > 0) {
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device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
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" (%d), using %d instead.\n", fl_pad, pad);
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}
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}
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m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
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v = V_INGPADBOUNDARY(ilog2(pad) - 5);
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t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
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if (is_t4(sc)) {
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if (fl_pack != -1 && fl_pack != pad) {
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/* Complain but carry on. */
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device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
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" using %d instead.\n", fl_pack, pad);
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}
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return;
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}
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pack = fl_pack;
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if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
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!powerof2(fl_pack)) {
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pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
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MPASS(powerof2(pack));
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if (pack < 16)
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pack = 16;
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if (pack == 32)
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pack = 64;
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if (pack > 4096)
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pack = 4096;
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if (fl_pack != -1) {
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device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
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" (%d), using %d instead.\n", fl_pack, pack);
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}
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}
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m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
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if (pack == 16)
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v = V_INGPACKBOUNDARY(0);
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else
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v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
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MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
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t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
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}
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/*
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* adap->params.vpd.cclk must be set up before this is called.
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*/
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@ -398,24 +415,9 @@ t4_tweak_chip_settings(struct adapter *sc)
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m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
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v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
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V_EGRSTATUSPAGESIZE(spg_len == 128);
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if (is_t4(sc) && (fl_pad || buffer_packing)) {
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/* t4_fl_pack has the correct value even when fl_pad = 0 */
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m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
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v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5);
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} else if (is_t5(sc) && fl_pad) {
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m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
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v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5);
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}
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t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
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if (is_t5(sc) && buffer_packing) {
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m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
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if (t5_fl_pack == 16)
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v = V_INGPACKBOUNDARY(0);
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else
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v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5);
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t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
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}
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setup_pad_and_pack_boundaries(sc);
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v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
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V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
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@ -486,15 +488,25 @@ t4_tweak_chip_settings(struct adapter *sc)
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}
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/*
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* SGE wants the buffer to be at least 64B and then a multiple of the pad
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* boundary or 16, whichever is greater.
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* SGE wants the buffer to be at least 64B and then a multiple of 16. If
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* padding and packing are enabled, the buffer's start and end need to be
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* correctly aligned as well. We'll just make sure that the size is a multiple
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* of the alignment, it is up to other parts .
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*/
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static inline int
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hwsz_ok(int hwsz)
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hwsz_ok(struct adapter *sc, int hwsz)
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{
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int mask = max(fl_pad, 16) - 1;
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int align = 16;
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if (fl_pad) {
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MPASS(sc->sge.pad_boundary > align);
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align = sc->sge.pad_boundary;
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}
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if (buffer_packing && sc->sge.pack_boundary > align)
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align = sc->sge.pack_boundary;
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align--; /* now a mask */
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return (hwsz >= 64 && (hwsz & align) == 0);
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return (hwsz >= 64 && (hwsz & mask) == 0);
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}
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/*
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@ -521,33 +533,22 @@ t4_read_chip_settings(struct adapter *sc)
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m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
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v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
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V_EGRSTATUSPAGESIZE(spg_len == 128);
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if (is_t4(sc) && (fl_pad || buffer_packing)) {
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m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
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v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5);
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} else if (is_t5(sc) && fl_pad) {
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m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
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v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5);
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}
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r = t4_read_reg(sc, A_SGE_CONTROL);
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if ((r & m) != v) {
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device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
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rc = EINVAL;
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}
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s->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5);
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if (is_t5(sc) && buffer_packing) {
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m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
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if (t5_fl_pack == 16)
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v = V_INGPACKBOUNDARY(0);
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else
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v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5);
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if (is_t4(sc))
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s->pack_boundary = s->pad_boundary;
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else {
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r = t4_read_reg(sc, A_SGE_CONTROL2);
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if ((r & m) != v) {
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device_printf(sc->dev,
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"invalid SGE_CONTROL2(0x%x)\n", r);
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rc = EINVAL;
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}
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if (G_INGPACKBOUNDARY(r) == 0)
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s->pack_boundary = 16;
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else
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s->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
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}
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s->pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack;
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v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
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V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
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@ -568,13 +569,22 @@ t4_read_chip_settings(struct adapter *sc)
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for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
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r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
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hwb->size = r;
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hwb->zidx = hwsz_ok(r) ? -1 : -2;
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hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
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hwb->next = -1;
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}
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/*
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* Create a sorted list in decreasing order of hw buffer sizes (and so
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* increasing order of spare area) for each software zone.
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*
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* If padding is enabled then the start and end of the buffer must align
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* to the pad boundary; if packing is enabled then they must align with
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* the pack boundary as well. Allocations from the cluster zones are
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* aligned to min(size, 4K), so the buffer starts at that alignment and
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* ends at hwb->size alignment. If mbuf inlining is allowed the
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* starting alignment will be reduced to MSIZE and the driver will
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* exercise appropriate caution when deciding on the best buffer layout
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* to use.
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*/
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n = 0; /* no usable buffer size to begin with */
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swz = &s->sw_zone_info[0];
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@ -586,6 +596,15 @@ t4_read_chip_settings(struct adapter *sc)
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swz->zone = m_getzone(swz->size);
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swz->type = m_gettype(swz->size);
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if (swz->size < PAGE_SIZE) {
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MPASS(powerof2(swz->size));
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if (fl_pad && (swz->size % sc->sge.pad_boundary != 0))
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continue;
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if (buffer_packing &&
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(swz->size % sc->sge.pack_boundary != 0))
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continue;
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}
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if (swz->size == safest_rx_cluster)
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safe_swz = swz;
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@ -593,6 +612,12 @@ t4_read_chip_settings(struct adapter *sc)
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for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
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if (hwb->zidx != -1 || hwb->size > swz->size)
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continue;
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#ifdef INVARIANTS
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if (fl_pad)
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MPASS(hwb->size % sc->sge.pad_boundary == 0);
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if (buffer_packing)
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MPASS(hwb->size % sc->sge.pack_boundary == 0);
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#endif
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hwb->zidx = i;
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if (head == -1)
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head = tail = j;
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@ -640,14 +665,17 @@ t4_read_chip_settings(struct adapter *sc)
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int spare;
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hwb = &s->hw_buf_info[i];
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#ifdef INVARIANTS
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if (fl_pad)
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MPASS(hwb->size % sc->sge.pad_boundary == 0);
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if (buffer_packing)
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MPASS(hwb->size % sc->sge.pack_boundary == 0);
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#endif
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spare = safe_swz->size - hwb->size;
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if (spare < CL_METADATA_SIZE)
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continue;
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if (s->safe_hwidx2 == -1 ||
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spare == CL_METADATA_SIZE + MSIZE)
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if (spare >= CL_METADATA_SIZE) {
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s->safe_hwidx2 = i;
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if (spare >= CL_METADATA_SIZE + MSIZE)
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break;
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}
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}
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}
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@ -745,17 +773,6 @@ t4_create_dma_tag(struct adapter *sc)
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return (rc);
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}
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static inline int
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enable_buffer_packing(struct adapter *sc)
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{
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if (sc->flags & BUF_PACKING_OK &&
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((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */
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(is_t4(sc) && buffer_packing == 1)))
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return (1);
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return (0);
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}
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void
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t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
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struct sysctl_oid_list *children)
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@ -769,7 +786,7 @@ t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
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NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)");
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SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
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NULL, fl_pad, "payload pad boundary (bytes)");
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NULL, sc->sge.pad_boundary, "payload pad boundary (bytes)");
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SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
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NULL, spg_len, "status page size (bytes)");
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@ -777,10 +794,6 @@ t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
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SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
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NULL, cong_drop, "congestion drop setting");
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SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD,
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NULL, enable_buffer_packing(sc),
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"pack multiple frames in one fl buffer");
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SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
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NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)");
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}
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@ -958,7 +971,6 @@ mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
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#ifdef TCP_OFFLOAD
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}
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#endif
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payload = roundup2(payload, fl_pad);
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return (payload);
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}
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@ -983,7 +995,7 @@ t4_setup_port_queues(struct port_info *pi)
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struct ifnet *ifp = pi->ifp;
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struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev);
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struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
|
||||
int maxp, pack, mtu = ifp->if_mtu;
|
||||
int maxp, mtu = ifp->if_mtu;
|
||||
|
||||
/* Interrupt vector to start from (when using multiple vectors) */
|
||||
intr_idx = first_vector(pi);
|
||||
@ -994,7 +1006,6 @@ t4_setup_port_queues(struct port_info *pi)
|
||||
* b) allocate queue iff it will take direct interrupts.
|
||||
*/
|
||||
maxp = mtu_to_max_payload(sc, mtu, 0);
|
||||
pack = enable_buffer_packing(sc);
|
||||
if (pi->flags & INTR_RXQ) {
|
||||
oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
|
||||
CTLFLAG_RD, NULL, "rx queues");
|
||||
@ -1005,7 +1016,7 @@ t4_setup_port_queues(struct port_info *pi)
|
||||
|
||||
snprintf(name, sizeof(name), "%s rxq%d-fl",
|
||||
device_get_nameunit(pi->dev), i);
|
||||
init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, pack, name);
|
||||
init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, name);
|
||||
|
||||
if (pi->flags & INTR_RXQ) {
|
||||
rxq->iq.flags |= IQ_INTR;
|
||||
@ -1029,7 +1040,7 @@ t4_setup_port_queues(struct port_info *pi)
|
||||
|
||||
snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
|
||||
device_get_nameunit(pi->dev), i);
|
||||
init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, pack, name);
|
||||
init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, name);
|
||||
|
||||
if (pi->flags & INTR_OFLD_RXQ) {
|
||||
ofld_rxq->iq.flags |= IQ_INTR;
|
||||
@ -1572,8 +1583,14 @@ get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int total, int flags)
|
||||
caddr_t payload;
|
||||
|
||||
len = min(total, hwb->size - fl->rx_offset);
|
||||
padded_len = roundup2(len, fl->buf_boundary);
|
||||
payload = sd->cl + cll->region1 + fl->rx_offset;
|
||||
if (fl->flags & FL_BUF_PACKING) {
|
||||
padded_len = roundup2(len, fl->buf_boundary);
|
||||
MPASS(fl->rx_offset + padded_len <= hwb->size);
|
||||
} else {
|
||||
padded_len = hwb->size;
|
||||
MPASS(fl->rx_offset == 0); /* not packing */
|
||||
}
|
||||
|
||||
if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
|
||||
|
||||
@ -2121,14 +2138,15 @@ init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
|
||||
}
|
||||
|
||||
static inline void
|
||||
init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, int pack,
|
||||
char *name)
|
||||
init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
|
||||
{
|
||||
|
||||
fl->qsize = qsize;
|
||||
fl->sidx = qsize - spg_len / EQ_ESIZE;
|
||||
strlcpy(fl->lockname, name, sizeof(fl->lockname));
|
||||
if (pack)
|
||||
if (sc->flags & BUF_PACKING_OK &&
|
||||
((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
|
||||
(is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
|
||||
fl->flags |= FL_BUF_PACKING;
|
||||
find_best_refill_source(sc, fl, maxp);
|
||||
find_safe_refill_source(sc, fl);
|
||||
@ -2277,11 +2295,13 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
|
||||
|
||||
if (fl->flags & FL_BUF_PACKING) {
|
||||
fl->lowat = roundup2(sc->sge.fl_starve_threshold2, 8);
|
||||
fl->buf_boundary = max(fl_pad, sc->sge.pack_boundary);
|
||||
fl->buf_boundary = sc->sge.pack_boundary;
|
||||
} else {
|
||||
fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8);
|
||||
fl->buf_boundary = fl_pad;
|
||||
fl->buf_boundary = 16;
|
||||
}
|
||||
if (fl_pad && fl->buf_boundary < sc->sge.pad_boundary)
|
||||
fl->buf_boundary = sc->sge.pad_boundary;
|
||||
|
||||
c.iqns_to_fl0congen |=
|
||||
htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
|
||||
@ -2452,6 +2472,10 @@ add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
|
||||
SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
|
||||
CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
|
||||
"SGE context id of the freelist");
|
||||
SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
|
||||
fl_pad ? 1 : 0, "padding enabled");
|
||||
SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
|
||||
fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
|
||||
SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
|
||||
0, "consumer index");
|
||||
if (fl->flags & FL_BUF_PACKING) {
|
||||
@ -4367,6 +4391,17 @@ find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
|
||||
|
||||
if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
|
||||
break;
|
||||
|
||||
/*
|
||||
* Do not inline mbufs if doing so would violate the pad/pack
|
||||
* boundary alignment requirement.
|
||||
*/
|
||||
if (fl_pad && (MSIZE % sc->sge.pad_boundary) != 0)
|
||||
continue;
|
||||
if (fl->flags & FL_BUF_PACKING &&
|
||||
(MSIZE % sc->sge.pack_boundary) != 0)
|
||||
continue;
|
||||
|
||||
if (spare < CL_METADATA_SIZE + MSIZE)
|
||||
continue;
|
||||
n = (spare - CL_METADATA_SIZE) / MSIZE;
|
||||
@ -4449,7 +4484,9 @@ find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
|
||||
spare = swz->size - hwb->size;
|
||||
fl->cll_alt.hwidx = hwidx;
|
||||
fl->cll_alt.zidx = hwb->zidx;
|
||||
if (allow_mbufs_in_cluster)
|
||||
if (allow_mbufs_in_cluster &&
|
||||
(fl_pad == 0 || (MSIZE % sc->sge.pad_boundary) == 0) &&
|
||||
(!(fl->flags & FL_BUF_PACKING) || (MSIZE % sc->sge.pack_boundary) == 0))
|
||||
fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
|
||||
else
|
||||
fl->cll_alt.region1 = 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user