From e34425be268c4eb0a080a74c4ebbf3cd737cb75f Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 12 Jun 2018 11:47:21 +0000 Subject: [PATCH] arm64: rockchip: Correctly set armclk Parent needs to be the same frequency as the armclk, not twice the freq. The real divider is incremented by one so write it with - 1 The rate can be at index 0 Pointy Hat To: myself --- sys/arm64/rockchip/clk/rk_clk_armclk.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sys/arm64/rockchip/clk/rk_clk_armclk.c b/sys/arm64/rockchip/clk/rk_clk_armclk.c index 57a3141edff2..421772ca2d3b 100644 --- a/sys/arm64/rockchip/clk/rk_clk_armclk.c +++ b/sys/arm64/rockchip/clk/rk_clk_armclk.c @@ -154,12 +154,13 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, if (sc->rates[i].freq == *fout) { best = sc->rates[i].freq; div = sc->rates[i].div; - best_p = best * (div + 1); + best_p = best * div; rate = i; + break; } } - if (rate == 0) + if (rate == sc->nrates) return (0); err = clknode_set_freq(p_main, best_p, 0, 1); @@ -177,7 +178,7 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, DEVICE_LOCK(clk); READ4(clk, sc->muxdiv_offset, &val); val &= ~sc->div_mask; - val |= div << sc->div_shift; + val |= (div - 1) << sc->div_shift; WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_ARMCLK_MASK); DEVICE_UNLOCK(clk);