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Pull in r292758 from upstream llvm trunk (by Sanjay Patel):

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[x86] avoid crashing with illegal vector type (PR31672)

  https://llvm.org/bugs/show_bug.cgi?id=31672

This fixes an assertion while building graphics/gegl3.

PR:		216166
This commit is contained in:
Dimitry Andric 2017-01-22 18:31:49 +00:00
parent daf78e69a8
commit e353c0d2f9
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/clang400-import/; revision=312643
1 changed files with 26 additions and 14 deletions
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40
contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -28788,10 +28788,12 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
/// If a vector select has an operand that is -1 or 0, simplify the select to a
/// bitwise logic operation.
static SDValue combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
/// If a vector select has an operand that is -1 or 0, try to simplify the
/// select to a bitwise logic operation.
static SDValue
combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
SDValue Cond = N->getOperand(0);
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
@ -28853,18 +28855,28 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
}
}
if (!TValIsAllOnes && !FValIsAllZeros)
// vselect Cond, 111..., 000... -> Cond
if (TValIsAllOnes && FValIsAllZeros)
return DAG.getBitcast(VT, Cond);
if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(CondVT))
return SDValue();
SDValue Ret;
if (TValIsAllOnes && FValIsAllZeros)
Ret = Cond;
else if (TValIsAllOnes)
Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
else if (FValIsAllZeros)
Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond, DAG.getBitcast(CondVT, LHS));
// vselect Cond, 111..., X -> or Cond, X
if (TValIsAllOnes) {
SDValue CastRHS = DAG.getBitcast(CondVT, RHS);
SDValue Or = DAG.getNode(ISD::OR, DL, CondVT, Cond, CastRHS);
return DAG.getBitcast(VT, Or);
}
return DAG.getBitcast(VT, Ret);
// vselect Cond, X, 000... -> and Cond, X
if (FValIsAllZeros) {
SDValue CastLHS = DAG.getBitcast(CondVT, LHS);
SDValue And = DAG.getNode(ISD::AND, DL, CondVT, Cond, CastLHS);
return DAG.getBitcast(VT, And);
}
return SDValue();
}
static SDValue combineSelectOfTwoConstants(SDNode *N, SelectionDAG &DAG) {
@ -29353,7 +29365,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
}
}
if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, Subtarget))
if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DCI, Subtarget))
return V;
// If this is a *dynamic* select (non-constant condition) and we can match