Fix newer Xircom CBE2-100 cards that were reporting
dc0: MII without any PHY! We have to enable the connection to the MII first. Doing so fixes the problem cards without breaking the older, working cards. Bad card provided by: deischen
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@ -2212,6 +2212,20 @@ dc_attach(device_t dev)
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sc->dc_pmode = DC_PMODE_MII;
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}
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/*
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* Setup General Purpose port mode and data so the tulip can talk
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* to the MII. This needs to be done before mii_phy_probe so that
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* we can actually see them.
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*/
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if (DC_IS_XIRCOM(sc)) {
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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}
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error = mii_phy_probe(dev, &sc->dc_miibus,
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dc_ifmedia_upd, dc_ifmedia_sts);
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@ -2239,19 +2253,6 @@ dc_attach(device_t dev)
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goto fail;
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}
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if (DC_IS_XIRCOM(sc)) {
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/*
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* setup General Purpose Port mode and data so the tulip
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* can talk to the MII.
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*/
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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}
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if (DC_IS_ADMTEK(sc)) {
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/*
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* Set automatic TX underrun recovery for the ADMtek chips
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@ -2212,6 +2212,20 @@ dc_attach(device_t dev)
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sc->dc_pmode = DC_PMODE_MII;
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}
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/*
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* Setup General Purpose port mode and data so the tulip can talk
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* to the MII. This needs to be done before mii_phy_probe so that
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* we can actually see them.
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*/
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if (DC_IS_XIRCOM(sc)) {
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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}
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error = mii_phy_probe(dev, &sc->dc_miibus,
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dc_ifmedia_upd, dc_ifmedia_sts);
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@ -2239,19 +2253,6 @@ dc_attach(device_t dev)
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goto fail;
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}
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if (DC_IS_XIRCOM(sc)) {
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/*
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* setup General Purpose Port mode and data so the tulip
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* can talk to the MII.
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*/
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
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DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
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DELAY(10);
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}
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if (DC_IS_ADMTEK(sc)) {
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/*
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* Set automatic TX underrun recovery for the ADMtek chips
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