pci: Implement new memory and io space allocator for PCI.
Cleanup code and move initializing bridge into separate function. Add checking of PCI mode (RC or endpoint). Obtained from: Semihalf
This commit is contained in:
Grzegorz Bernacki
parent
d65cdf4b9d
commit
e3ac97538c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=240489
@ -1,6 +1,7 @@
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/*-
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* Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
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* Copyright (c) 2010 The FreeBSD Foundation
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* Copyright (c) 2010-2012 Semihalf
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* All rights reserved.
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*
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* Developed by Semihalf.
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@ -89,18 +90,19 @@ __FBSDID("$FreeBSD$");
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#define PCIE_REG_STATUS 0x1A04
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#define PCIE_REG_IRQ_MASK 0x1910
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#define STATUS_LINK_DOWN 1
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#define STATUS_BUS_OFFS 8
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#define STATUS_BUS_MASK (0xFF << STATUS_BUS_OFFS)
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#define STATUS_DEV_OFFS 16
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#define STATUS_DEV_MASK (0x1F << STATUS_DEV_OFFS)
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#define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
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#define PCIE_CONTROL_HOT_RESET (1 << 24)
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#define P2P_CONF_BUS_OFFS 16
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#define P2P_CONF_BUS_MASK (0xFF << P2P_CONF_BUS_OFFS)
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#define P2P_CONF_DEV_OFFS 24
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#define P2P_CONF_DEV_MASK (0x1F << P2P_CONF_DEV_OFFS)
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#define PCIE_LINK_TIMEOUT 1000000
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#define PCI_VENDORID_MRVL 0x11AB
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#define PCIE_STATUS_LINK_DOWN 1
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#define PCIE_STATUS_DEV_OFFS 16
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/* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
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#define PCI_MIN_IO_ALLOC 4
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#define PCI_MIN_MEM_ALLOC 16
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#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
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struct mv_pcib_softc {
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device_t sc_dev;
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@ -108,15 +110,16 @@ struct mv_pcib_softc {
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struct rman sc_mem_rman;
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bus_addr_t sc_mem_base;
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bus_addr_t sc_mem_size;
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bus_addr_t sc_mem_alloc; /* Next allocation. */
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int sc_mem_win_target;
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uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
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(PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
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int sc_win_target;
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int sc_mem_win_attr;
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struct rman sc_io_rman;
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bus_addr_t sc_io_base;
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bus_addr_t sc_io_size;
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bus_addr_t sc_io_alloc; /* Next allocation. */
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int sc_io_win_target;
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uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE /
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(PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
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int sc_io_win_attr;
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struct resource *sc_res;
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@ -127,6 +130,7 @@ struct mv_pcib_softc {
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int sc_busnr; /* Host bridge bus number */
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int sc_devnr; /* Host bridge device number */
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int sc_type;
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int sc_mode; /* Endpoint / Root Complex */
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struct fdt_pci_intr sc_intr_info;
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};
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@ -143,7 +147,8 @@ static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
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static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
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static int mv_pcib_intr_info(phandle_t, struct mv_pcib_softc *);
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static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
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static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
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static int mv_pcib_mem_init(struct mv_pcib_softc *);
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/* Forward prototypes */
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static int mv_pcib_probe(device_t);
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@ -185,7 +190,7 @@ static device_method_t mv_pcib_methods[] = {
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DEVMETHOD(pcib_read_config, mv_pcib_read_config),
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DEVMETHOD(pcib_write_config, mv_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
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/* OFW bus interface */
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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@ -230,39 +235,29 @@ mv_pcib_attach(device_t self)
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{
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struct mv_pcib_softc *sc;
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phandle_t node, parnode;
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uint32_t val;
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uint32_t val, unit;
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int err;
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sc = device_get_softc(self);
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sc->sc_dev = self;
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unit = fdt_get_unit(self);
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node = ofw_bus_get_node(self);
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parnode = OF_parent(node);
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if (fdt_is_compatible(node, "mrvl,pcie")) {
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sc->sc_type = MV_TYPE_PCIE;
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sc->sc_mem_win_target = MV_WIN_PCIE_TARGET(0);
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sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(0);
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sc->sc_io_win_target = MV_WIN_PCIE_TARGET(0);
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sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(0);
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#ifdef SOC_MV_ORION
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sc->sc_win_target = MV_WIN_PCIE_TARGET(unit);
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sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit);
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sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit);
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} else if (fdt_is_compatible(node, "mrvl,pci")) {
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sc->sc_type = MV_TYPE_PCI;
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sc->sc_mem_win_target = MV_WIN_PCI_TARGET;
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sc->sc_win_target = MV_WIN_PCI_TARGET;
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sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
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sc->sc_io_win_target = MV_WIN_PCI_TARGET;
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sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
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#endif
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} else
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return (ENXIO);
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/*
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* Get PCI interrupt info.
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*/
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if (mv_pcib_intr_info(node, sc) != 0) {
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device_printf(self, "could not retrieve interrupt info\n");
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return (ENXIO);
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}
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/*
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* Retrieve our mem-mapped registers range.
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*/
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@ -276,6 +271,19 @@ mv_pcib_attach(device_t self)
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sc->sc_bst = rman_get_bustag(sc->sc_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_res);
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val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
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sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
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MV_MODE_ENDPOINT);
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/*
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* Get PCI interrupt info.
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*/
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if ((sc->sc_mode == MV_MODE_ROOT) &&
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(mv_pcib_intr_info(node, sc) != 0)) {
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device_printf(self, "could not retrieve interrupt info\n");
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return (ENXIO);
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}
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/*
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* Configure decode windows for PCI(E) access.
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*/
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@ -285,18 +293,87 @@ mv_pcib_attach(device_t self)
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mv_pcib_hw_cfginit();
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/*
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* Enable PCI bridge.
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* Enable PCIE device.
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*/
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val = mv_pcib_hw_cfgread(sc, sc->sc_busnr, sc->sc_devnr, 0,
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PCIR_COMMAND, 2);
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val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
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PCIM_CMD_PORTEN;
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mv_pcib_hw_cfgwrite(sc, sc->sc_busnr, sc->sc_devnr, 0,
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PCIR_COMMAND, val, 2);
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mv_pcib_enable(sc, unit);
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sc->sc_mem_alloc = sc->sc_mem_base;
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sc->sc_io_alloc = sc->sc_io_base;
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/*
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* Memory management.
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*/
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err = mv_pcib_mem_init(sc);
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if (err)
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return (err);
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if (sc->sc_mode == MV_MODE_ROOT) {
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err = mv_pcib_init(sc, sc->sc_busnr,
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mv_pcib_maxslots(sc->sc_dev));
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if (err)
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goto error;
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device_add_child(self, "pci", -1);
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} else {
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sc->sc_devnr = 1;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
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device_add_child(self, "pci_ep", -1);
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}
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return (bus_generic_attach(self));
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error:
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/* XXX SYS_RES_ should be released here */
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rman_fini(&sc->sc_mem_rman);
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rman_fini(&sc->sc_io_rman);
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return (err);
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}
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static void
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mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
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{
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uint32_t val;
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#if !defined(SOC_MV_ARMADAXP)
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int timeout;
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/*
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* Check if PCIE device is enabled.
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*/
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if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) {
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write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
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~(CPU_CONTROL_PCIE_DISABLE(unit)));
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timeout = PCIE_LINK_TIMEOUT;
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val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
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PCIE_REG_STATUS);
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while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
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DELAY(1000);
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timeout -= 1000;
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val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
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PCIE_REG_STATUS);
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}
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}
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#endif
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if (sc->sc_mode == MV_MODE_ROOT) {
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/*
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* Enable PCI bridge.
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*/
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val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
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val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
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PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
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}
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}
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static int
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mv_pcib_mem_init(struct mv_pcib_softc *sc)
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{
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int err;
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/*
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* Memory management.
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*/
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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err = rman_init(&sc->sc_mem_rman);
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if (err)
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@ -319,29 +396,106 @@ mv_pcib_attach(device_t self)
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if (err)
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goto error;
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err = mv_pcib_init(sc, sc->sc_busnr, mv_pcib_maxslots(sc->sc_dev));
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if (err)
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goto error;
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device_add_child(self, "pci", -1);
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return (bus_generic_attach(self));
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return (0);
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error:
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/* XXX SYS_RES_ should be released here */
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rman_fini(&sc->sc_mem_rman);
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rman_fini(&sc->sc_io_rman);
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return (err);
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}
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static inline uint32_t
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pcib_bit_get(uint32_t *map, uint32_t bit)
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{
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uint32_t n = bit / BITS_PER_UINT32;
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bit = bit % BITS_PER_UINT32;
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return (map[n] & (1 << bit));
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}
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static inline void
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pcib_bit_set(uint32_t *map, uint32_t bit)
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{
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uint32_t n = bit / BITS_PER_UINT32;
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bit = bit % BITS_PER_UINT32;
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map[n] |= (1 << bit);
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}
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static inline uint32_t
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pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
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{
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uint32_t i;
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for (i = start; i < start + bits; i++)
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if (pcib_bit_get(map, i))
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return (0);
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return (1);
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}
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static inline void
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pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
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{
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uint32_t i;
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for (i = start; i < start + bits; i++)
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pcib_bit_set(map, i);
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}
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/*
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* The idea of this allocator is taken from ARM No-Cache memory
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* management code (sys/arm/arm/vm_machdep.c).
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*/
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static bus_addr_t
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pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
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{
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uint32_t bits, bits_limit, i, *map, min_alloc, size;
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bus_addr_t addr = 0;
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bus_addr_t base;
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if (smask & 1) {
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base = sc->sc_io_base;
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min_alloc = PCI_MIN_IO_ALLOC;
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bits_limit = sc->sc_io_size / min_alloc;
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map = sc->sc_io_map;
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smask &= ~0x3;
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} else {
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base = sc->sc_mem_base;
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min_alloc = PCI_MIN_MEM_ALLOC;
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bits_limit = sc->sc_mem_size / min_alloc;
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map = sc->sc_mem_map;
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smask &= ~0xF;
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}
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size = ~smask + 1;
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bits = size / min_alloc;
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for (i = 0; i + bits <= bits_limit; i += bits)
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if (pcib_map_check(map, i, bits)) {
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pcib_map_set(map, i, bits);
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addr = base + (i * min_alloc);
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return (addr);
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}
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return (addr);
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}
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static int
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mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
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int barno)
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{
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bus_addr_t *allocp, limit;
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uint32_t addr, bar, mask, size;
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uint32_t addr, bar;
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int reg, width;
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reg = PCIR_BAR(barno);
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/*
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* Need to init the BAR register with 0xffffffff before correct
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* value can be read.
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*/
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mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
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bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
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if (bar == 0)
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return (1);
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@ -349,37 +503,13 @@ mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
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/* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
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width = ((bar & 7) == 4) ? 2 : 1;
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mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
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size = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
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/* Get BAR type and size */
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if (bar & 1) {
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/* I/O port */
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allocp = &sc->sc_io_alloc;
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limit = sc->sc_io_base + sc->sc_io_size;
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size &= ~0x3;
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if ((size & 0xffff0000) == 0)
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size |= 0xffff0000;
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} else {
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/* Memory */
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allocp = &sc->sc_mem_alloc;
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limit = sc->sc_mem_base + sc->sc_mem_size;
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size &= ~0xF;
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}
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mask = ~size;
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size = mask + 1;
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/* Sanity check (must be a power of 2) */
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if (size & mask)
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return (width);
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addr = (*allocp + mask) & ~mask;
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if ((*allocp = addr + size) > limit)
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addr = pcib_alloc(sc, bar);
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if (!addr)
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return (-1);
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if (bootverbose)
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printf("PCI %u:%u:%u: reg %x: size=%08x: addr=%08x\n",
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bus, slot, func, reg, size, addr);
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printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
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bus, slot, func, reg, bar, addr);
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mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
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if (width == 2)
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@ -528,10 +658,20 @@ mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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rm = &sc->sc_mem_rman;
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break;
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default:
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return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
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return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
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type, rid, start, end, count, flags));
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};
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if ((start == 0UL) && (end == ~0UL)) {
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start = sc->sc_mem_base;
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end = sc->sc_mem_base + sc->sc_mem_size - 1;
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count = sc->sc_mem_size;
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}
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if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
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(end > sc->sc_mem_base + sc->sc_mem_size - 1))
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return (NULL);
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res = rman_reserve_resource(rm, start, end, count, flags, child);
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if (res == NULL)
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return (NULL);
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@ -696,8 +836,9 @@ mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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{
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struct mv_pcib_softc *sc = device_get_softc(dev);
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/* Skip self */
|
||||
if (bus == sc->sc_busnr && slot == sc->sc_devnr)
|
||||
/* Return ~0 if link is inactive or trying to read from Root */
|
||||
if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
|
||||
PCIE_STATUS_LINK_DOWN) || (slot == 0))
|
||||
return (~0U);
|
||||
|
||||
return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
|
||||
@ -709,8 +850,9 @@ mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
||||
{
|
||||
struct mv_pcib_softc *sc = device_get_softc(dev);
|
||||
|
||||
/* Skip self */
|
||||
if (bus == sc->sc_busnr && slot == sc->sc_devnr)
|
||||
/* Return if link is inactive or trying to write to Root */
|
||||
if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
|
||||
PCIE_STATUS_LINK_DOWN) || (slot == 0))
|
||||
return;
|
||||
|
||||
mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
|
||||
@ -749,15 +891,16 @@ mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
|
||||
}
|
||||
|
||||
/* Configure CPU decoding windows */
|
||||
error = decode_win_cpu_set(sc->sc_io_win_target,
|
||||
sc->sc_io_win_attr, io_space.base_parent, io_space.len, -1);
|
||||
error = decode_win_cpu_set(sc->sc_win_target,
|
||||
sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
|
||||
if (error < 0) {
|
||||
device_printf(dev, "could not set up CPU decode "
|
||||
"window for PCI IO\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
error = decode_win_cpu_set(sc->sc_mem_win_target,
|
||||
sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, -1);
|
||||
error = decode_win_cpu_set(sc->sc_win_target,
|
||||
sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
|
||||
mem_space.base_parent);
|
||||
if (error < 0) {
|
||||
device_printf(dev, "could not set up CPU decode "
|
||||
"windows for PCI MEM\n");
|
||||
@ -784,22 +927,3 @@ mv_pcib_intr_info(phandle_t node, struct mv_pcib_softc *sc)
|
||||
return (0);
|
||||
}
|
||||
|
||||
#if 0
|
||||
control = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
|
||||
PCIE_REG_CONTROL);
|
||||
|
||||
/*
|
||||
* If this PCI-E port (controller) is configured (by the
|
||||
* underlying firmware) with lane width other than 1x, there
|
||||
* are auxiliary resources defined for aggregating more width
|
||||
* on our lane. Skip all such entries as they are not
|
||||
* standalone ports and must not have a device object
|
||||
* instantiated.
|
||||
*/
|
||||
if ((control & PCIE_CTRL_LINK1X) == 0)
|
||||
while (info->op_base &&
|
||||
info->op_type == MV_TYPE_PCIE_AGGR_LANE)
|
||||
info++;
|
||||
|
||||
mv_pcib_add_child(driver, parent, sc);
|
||||
#endif
|
||||
|
||||
@ -257,15 +257,16 @@
|
||||
#define MV_WIN_PCIE_TARGET(n) 4
|
||||
#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
|
||||
#define MV_WIN_PCIE_IO_ATTR(n) 0x51
|
||||
#define MV_WIN_PCI_TARGET 3
|
||||
#define MV_WIN_PCI_MEM_ATTR 0x59
|
||||
#define MV_WIN_PCI_IO_ATTR 0x51
|
||||
#elif defined(SOC_MV_LOKIPLUS)
|
||||
#define MV_WIN_PCIE_TARGET(n) (3 + (n))
|
||||
#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
|
||||
#define MV_WIN_PCIE_IO_ATTR(n) 0x51
|
||||
#endif
|
||||
|
||||
#define MV_WIN_PCI_TARGET 3
|
||||
#define MV_WIN_PCI_MEM_ATTR 0x59
|
||||
#define MV_WIN_PCI_IO_ATTR 0x51
|
||||
|
||||
#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
|
||||
(n) + 1) + 0x1820)
|
||||
#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user