ichiic/ig4: completely disengage from smbus
MFC after: 5 weeks
This commit is contained in:
Andriy Gapon
parent
0112b52b61
commit
e3d255499a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=308219
@ -37,7 +37,7 @@
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__FBSDID("$FreeBSD$");
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/*
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* Intel fourth generation mobile cpus integrated I2C device, smbus driver.
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* Intel fourth generation mobile cpus integrated I2C deviceer.
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*
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* See ig4_reg.h for datasheet reference and notes.
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* See ig4_var.h for locking semantics.
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@ -60,7 +60,6 @@ __FBSDID("$FreeBSD$");
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/smbus/smbconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/iicbus/iiconf.h>
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@ -236,18 +235,13 @@ data_read(ig4iic_softc_t *sc)
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* the target address for when the controller later issues a START.
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*/
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static void
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set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op)
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set_slave_addr(ig4iic_softc_t *sc, uint8_t slave)
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{
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uint32_t tar;
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uint32_t ctl;
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int use_10bit;
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use_10bit = sc->use_10bit;
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if (trans_op & SMB_TRANS_7BIT)
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use_10bit = 0;
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if (trans_op & SMB_TRANS_10BIT)
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use_10bit = 1;
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use_10bit = 0;
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if (sc->slave_valid && sc->last_slave == slave &&
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sc->use_10bit == use_10bit) {
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return;
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@ -290,209 +284,13 @@ set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op)
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sc->last_slave = slave;
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}
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/*
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* Issue START with byte command, possible count, and a variable length
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* read or write buffer, then possible turn-around read. The read also
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* has a possible count received.
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*
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* For SMBUS -
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*
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* Quick: START+ADDR+RD/WR STOP
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*
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* Normal: START+ADDR+WR CMD DATA..DATA STOP
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*
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* START+ADDR+RD CMD
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* RESTART+ADDR RDATA..RDATA STOP
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* (can also be used for I2C transactions)
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*
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* Process Call: START+ADDR+WR CMD DATAL DATAH
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* RESTART+ADDR+RD RDATAL RDATAH STOP
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*
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* Block: START+ADDR+RD CMD
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* RESTART+ADDR+RD RCOUNT DATA... STOP
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*
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* START+ADDR+WR CMD
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* RESTART+ADDR+WR WCOUNT DATA... STOP
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*
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* For I2C - basically, no *COUNT fields, possibly no *CMD field. If the
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* sender needs to issue a 2-byte command it will incorporate it
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* into the write buffer and also set NOCMD.
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*
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* Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically
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* by the controller at the beginning of a command sequence or on a data
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* direction turn-around, and we only need to tell it when to issue the STOP.
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*/
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static int
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smb_transaction(ig4iic_softc_t *sc, char cmd, int op,
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char *wbuf, int wcount, char *rbuf, int rcount, int *actualp)
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{
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int error;
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int unit;
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uint32_t last;
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/*
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* Debugging - dump registers
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*/
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if (ig4_dump) {
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unit = device_get_unit(sc->dev);
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if (ig4_dump & (1 << unit)) {
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ig4_dump &= ~(1 << unit);
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ig4iic_dump(sc);
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}
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}
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/*
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* Issue START or RESTART with next data byte, clear any previous
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* abort condition that may have been holding the txfifo in reset.
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*/
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last = IG4_DATA_RESTART;
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reg_read(sc, IG4_REG_CLR_TX_ABORT);
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if (actualp)
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*actualp = 0;
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/*
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* Issue command if not told otherwise (smbus).
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*/
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if ((op & SMB_TRANS_NOCMD) == 0) {
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error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
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if (error)
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goto done;
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last |= (u_char)cmd;
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if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
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last |= IG4_DATA_STOP;
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reg_write(sc, IG4_REG_DATA_CMD, last);
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last = 0;
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}
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/*
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* Clean out any previously received data.
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*/
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if (sc->rpos != sc->rnext &&
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(op & SMB_TRANS_NOREPORT) == 0) {
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device_printf(sc->dev,
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"discarding %d bytes of spurious data\n",
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sc->rnext - sc->rpos);
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}
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sc->rpos = 0;
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sc->rnext = 0;
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/*
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* If writing and not told otherwise, issue the write count (smbus).
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*/
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if (wcount && (op & SMB_TRANS_NOCNT) == 0) {
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error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
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if (error)
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goto done;
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last |= (u_char)cmd;
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reg_write(sc, IG4_REG_DATA_CMD, last);
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last = 0;
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}
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/*
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* Bulk write (i2c)
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*/
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while (wcount) {
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error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
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if (error)
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goto done;
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last |= (u_char)*wbuf;
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if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
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last |= IG4_DATA_STOP;
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reg_write(sc, IG4_REG_DATA_CMD, last);
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--wcount;
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++wbuf;
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last = 0;
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}
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/*
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* Issue reads to xmit FIFO (strange, I know) to tell the controller
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* to clock in data. At the moment just issue one read ahead to
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* pipeline the incoming data.
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*
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* NOTE: In the case of NOCMD and wcount == 0 we still issue a
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* RESTART here, even if the data direction has not changed
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* from the previous CHAINing call. This we force the RESTART.
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* (A new START is issued automatically by the controller in
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* the other nominal cases such as a data direction change or
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* a previous STOP was issued).
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*
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* If this will be the last byte read we must also issue the STOP
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* at the end of the read.
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*/
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if (rcount) {
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last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD;
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if (rcount == 1 &&
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(op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) ==
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SMB_TRANS_NOCNT) {
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last |= IG4_DATA_STOP;
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}
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reg_write(sc, IG4_REG_DATA_CMD, last);
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last = IG4_DATA_COMMAND_RD;
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}
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/*
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* Bulk read (i2c) and count field handling (smbus)
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*/
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while (rcount) {
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/*
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* Maintain a pipeline by queueing the allowance for the next
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* read before waiting for the current read.
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*/
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if (rcount > 1) {
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if (op & SMB_TRANS_NOCNT)
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last = (rcount == 2) ? IG4_DATA_STOP : 0;
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else
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last = 0;
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reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD |
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last);
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}
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error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);
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if (error) {
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if ((op & SMB_TRANS_NOREPORT) == 0) {
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device_printf(sc->dev,
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"rx timeout addr 0x%02x\n",
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sc->last_slave);
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}
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goto done;
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}
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last = data_read(sc);
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if (op & SMB_TRANS_NOCNT) {
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*rbuf = (u_char)last;
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++rbuf;
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--rcount;
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if (actualp)
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++*actualp;
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} else {
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/*
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* Handle count field (smbus), which is not part of
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* the rcount'ed buffer. The first read data in a
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* bulk transfer is the count.
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*
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* XXX if rcount is loaded as 0 how do I generate a
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* STOP now without issuing another RD or WR?
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*/
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if (rcount > (u_char)last)
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rcount = (u_char)last;
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op |= SMB_TRANS_NOCNT;
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}
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}
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error = 0;
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done:
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/* XXX wait for xmit buffer to become empty */
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last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
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return (error);
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}
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/*
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* IICBUS API FUNCTIONS
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*/
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static int
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ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave)
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{
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/* XXX 10-bit address support? */
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set_slave_addr(sc, slave >> 1, 0);
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set_slave_addr(sc, slave >> 1);
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return (0);
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}
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@ -706,7 +504,7 @@ ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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/* TODO handle speed configuration? */
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if (oldaddr != NULL)
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*oldaddr = sc->last_slave << 1;
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set_slave_addr(sc, addr >> 1, 0);
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set_slave_addr(sc, addr >> 1);
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if (addr == IIC_UNKNOWN)
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sc->slave_valid = false;
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@ -716,8 +514,6 @@ ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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}
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/*
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* SMBUS API FUNCTIONS
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*
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* Called from ig4iic_pci_attach/detach()
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*/
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int
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@ -836,7 +632,6 @@ ig4iic_start(void *xdev)
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config_intrhook_disestablish(&sc->enum_hook);
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/* Attach us to the smbus */
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error = bus_generic_attach(sc->dev);
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if (error) {
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device_printf(sc->dev,
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@ -844,8 +639,6 @@ ig4iic_start(void *xdev)
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}
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}
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int
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ig4iic_detach(ig4iic_softc_t *sc)
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{
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@ -874,276 +667,6 @@ ig4iic_detach(ig4iic_softc_t *sc)
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return (0);
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}
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int
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ig4iic_smb_callback(device_t dev, int index, void *data)
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{
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int error;
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switch (index) {
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case SMB_REQUEST_BUS:
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error = 0;
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break;
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case SMB_RELEASE_BUS:
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error = 0;
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break;
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default:
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error = SMB_EABORT;
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break;
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}
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return (error);
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}
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/*
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* Quick command. i.e. START + cmd + R/W + STOP and no data. It is
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* unclear to me how I could implement this with the intel i2c controller
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* because the controller sends STARTs and STOPs automatically with data.
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*/
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int
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ig4iic_smb_quick(device_t dev, u_char slave, int how)
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{
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return (SMB_ENOTSUPP);
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}
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/*
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* Incremental send byte without stop (?). It is unclear why the slave
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* address is specified if this presumably is used in combination with
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* ig4iic_smb_quick().
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*
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* (Also, how would this work anyway? Issue the last byte with writeb()?)
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*/
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int
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ig4iic_smb_sendb(device_t dev, u_char slave, char byte)
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{
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ig4iic_softc_t *sc = device_get_softc(dev);
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uint32_t cmd;
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int error;
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sx_xlock(&sc->call_lock);
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mtx_lock(&sc->io_lock);
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set_slave_addr(sc, slave, 0);
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cmd = byte;
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if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) {
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reg_write(sc, IG4_REG_DATA_CMD, cmd);
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error = 0;
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} else {
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error = SMB_ETIMEOUT;
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}
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mtx_unlock(&sc->io_lock);
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sx_xunlock(&sc->call_lock);
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return (error);
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}
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/*
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* Incremental receive byte without stop (?). It is unclear why the slave
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* address is specified if this presumably is used in combination with
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* ig4iic_smb_quick().
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*/
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int
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ig4iic_smb_recvb(device_t dev, u_char slave, char *byte)
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{
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ig4iic_softc_t *sc = device_get_softc(dev);
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int error;
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sx_xlock(&sc->call_lock);
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mtx_lock(&sc->io_lock);
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set_slave_addr(sc, slave, 0);
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reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD);
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if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) {
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*byte = data_read(sc);
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error = 0;
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} else {
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*byte = 0;
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error = SMB_ETIMEOUT;
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}
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mtx_unlock(&sc->io_lock);
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sx_xunlock(&sc->call_lock);
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return (error);
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}
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/*
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* Write command and single byte in transaction.
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*/
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int
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ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte)
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{
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ig4iic_softc_t *sc = device_get_softc(dev);
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int error;
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sx_xlock(&sc->call_lock);
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mtx_lock(&sc->io_lock);
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set_slave_addr(sc, slave, 0);
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error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
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&byte, 1, NULL, 0, NULL);
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mtx_unlock(&sc->io_lock);
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sx_xunlock(&sc->call_lock);
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return (error);
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}
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/*
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* Write command and single word in transaction.
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*/
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int
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ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word)
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{
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ig4iic_softc_t *sc = device_get_softc(dev);
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char buf[2];
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int error;
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sx_xlock(&sc->call_lock);
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mtx_lock(&sc->io_lock);
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set_slave_addr(sc, slave, 0);
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buf[0] = word & 0xFF;
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buf[1] = word >> 8;
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error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
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buf, 2, NULL, 0, NULL);
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mtx_unlock(&sc->io_lock);
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sx_xunlock(&sc->call_lock);
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return (error);
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}
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/*
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* write command and read single byte in transaction.
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*/
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int
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ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte)
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{
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ig4iic_softc_t *sc = device_get_softc(dev);
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int error;
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sx_xlock(&sc->call_lock);
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mtx_lock(&sc->io_lock);
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set_slave_addr(sc, slave, 0);
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error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
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NULL, 0, byte, 1, NULL);
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mtx_unlock(&sc->io_lock);
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sx_xunlock(&sc->call_lock);
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return (error);
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}
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/*
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* write command and read word in transaction.
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*/
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int
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ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word)
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{
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ig4iic_softc_t *sc = device_get_softc(dev);
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char buf[2];
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int error;
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sx_xlock(&sc->call_lock);
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mtx_lock(&sc->io_lock);
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set_slave_addr(sc, slave, 0);
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if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
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NULL, 0, buf, 2, NULL)) == 0) {
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*word = (u_char)buf[0] | ((u_char)buf[1] << 8);
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}
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mtx_unlock(&sc->io_lock);
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sx_xunlock(&sc->call_lock);
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return (error);
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}
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/*
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* write command and word and read word in transaction
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*/
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int
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ig4iic_smb_pcall(device_t dev, u_char slave, char cmd,
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short sdata, short *rdata)
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{
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ig4iic_softc_t *sc = device_get_softc(dev);
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char rbuf[2];
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char wbuf[2];
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int error;
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sx_xlock(&sc->call_lock);
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mtx_lock(&sc->io_lock);
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set_slave_addr(sc, slave, 0);
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wbuf[0] = sdata & 0xFF;
|
||||
wbuf[1] = sdata >> 8;
|
||||
if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
|
||||
wbuf, 2, rbuf, 2, NULL)) == 0) {
|
||||
*rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8);
|
||||
}
|
||||
|
||||
mtx_unlock(&sc->io_lock);
|
||||
sx_xunlock(&sc->call_lock);
|
||||
return (error);
|
||||
}
|
||||
|
||||
int
|
||||
ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd,
|
||||
u_char wcount, char *buf)
|
||||
{
|
||||
ig4iic_softc_t *sc = device_get_softc(dev);
|
||||
int error;
|
||||
|
||||
sx_xlock(&sc->call_lock);
|
||||
mtx_lock(&sc->io_lock);
|
||||
|
||||
set_slave_addr(sc, slave, 0);
|
||||
error = smb_transaction(sc, cmd, 0,
|
||||
buf, wcount, NULL, 0, NULL);
|
||||
|
||||
mtx_unlock(&sc->io_lock);
|
||||
sx_xunlock(&sc->call_lock);
|
||||
return (error);
|
||||
}
|
||||
|
||||
int
|
||||
ig4iic_smb_bread(device_t dev, u_char slave, char cmd,
|
||||
u_char *countp_char, char *buf)
|
||||
{
|
||||
ig4iic_softc_t *sc = device_get_softc(dev);
|
||||
int rcount = *countp_char;
|
||||
int error;
|
||||
|
||||
sx_xlock(&sc->call_lock);
|
||||
mtx_lock(&sc->io_lock);
|
||||
|
||||
set_slave_addr(sc, slave, 0);
|
||||
error = smb_transaction(sc, cmd, 0,
|
||||
NULL, 0, buf, rcount, &rcount);
|
||||
*countp_char = rcount;
|
||||
|
||||
mtx_unlock(&sc->io_lock);
|
||||
sx_xunlock(&sc->call_lock);
|
||||
return (error);
|
||||
}
|
||||
|
||||
int
|
||||
ig4iic_smb_trans(device_t dev, int slave, char cmd, int op,
|
||||
char *wbuf, int wcount, char *rbuf, int rcount,
|
||||
int *actualp)
|
||||
{
|
||||
ig4iic_softc_t *sc = device_get_softc(dev);
|
||||
int error;
|
||||
|
||||
sx_xlock(&sc->call_lock);
|
||||
mtx_lock(&sc->io_lock);
|
||||
|
||||
set_slave_addr(sc, slave, op);
|
||||
error = smb_transaction(sc, cmd, op,
|
||||
wbuf, wcount, rbuf, rcount, actualp);
|
||||
|
||||
mtx_unlock(&sc->io_lock);
|
||||
sx_xunlock(&sc->call_lock);
|
||||
return (error);
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt Operation, see ig4_var.h for locking semantics.
|
||||
*/
|
||||
|
||||
@ -37,7 +37,7 @@
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* Intel fourth generation mobile cpus integrated I2C device, smbus driver.
|
||||
* Intel fourth generation mobile cpus integrated I2C device.
|
||||
*
|
||||
* See ig4_reg.h for datasheet reference and notes.
|
||||
*/
|
||||
@ -59,11 +59,8 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/smbus/smbconf.h>
|
||||
#include <dev/iicbus/iiconf.h>
|
||||
|
||||
#include "smbus_if.h"
|
||||
|
||||
#include <dev/ichiic/ig4_reg.h>
|
||||
#include <dev/ichiic/ig4_var.h>
|
||||
|
||||
@ -167,20 +164,6 @@ static device_method_t ig4iic_pci_methods[] = {
|
||||
DEVMETHOD(device_attach, ig4iic_pci_attach),
|
||||
DEVMETHOD(device_detach, ig4iic_pci_detach),
|
||||
|
||||
/* SMBus methods from ig4_smb.c */
|
||||
DEVMETHOD(smbus_callback, ig4iic_smb_callback),
|
||||
DEVMETHOD(smbus_quick, ig4iic_smb_quick),
|
||||
DEVMETHOD(smbus_sendb, ig4iic_smb_sendb),
|
||||
DEVMETHOD(smbus_recvb, ig4iic_smb_recvb),
|
||||
DEVMETHOD(smbus_writeb, ig4iic_smb_writeb),
|
||||
DEVMETHOD(smbus_writew, ig4iic_smb_writew),
|
||||
DEVMETHOD(smbus_readb, ig4iic_smb_readb),
|
||||
DEVMETHOD(smbus_readw, ig4iic_smb_readw),
|
||||
DEVMETHOD(smbus_pcall, ig4iic_smb_pcall),
|
||||
DEVMETHOD(smbus_bwrite, ig4iic_smb_bwrite),
|
||||
DEVMETHOD(smbus_bread, ig4iic_smb_bread),
|
||||
DEVMETHOD(smbus_trans, ig4iic_smb_trans),
|
||||
|
||||
DEVMETHOD(iicbus_transfer, ig4iic_transfer),
|
||||
DEVMETHOD(iicbus_reset, ig4iic_reset),
|
||||
DEVMETHOD(iicbus_callback, iicbus_null_callback),
|
||||
@ -199,6 +182,5 @@ static devclass_t ig4iic_pci_devclass;
|
||||
DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0,
|
||||
SI_ORDER_ANY);
|
||||
MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
|
||||
MODULE_DEPEND(ig4iic, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
|
||||
MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
|
||||
MODULE_VERSION(ig4iic, 1);
|
||||
|
||||
@ -47,14 +47,14 @@
|
||||
* I am also using the linux driver code as a reference to help resolve any
|
||||
* issues that come. These will be specifically documented in the code.
|
||||
*
|
||||
* Please see protocol notes in section 5.21. This controller is an I2C
|
||||
* master only and cannot act as a slave. The IO voltage should be set by
|
||||
* the BIOS. Standard (100Kb/s) and Fast (400Kb/s) and fast mode plus
|
||||
* (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT supported.
|
||||
* This controller is an I2C master only and cannot act as a slave. The IO
|
||||
* voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s)
|
||||
* and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT
|
||||
* supported.
|
||||
*/
|
||||
|
||||
#ifndef _BUS_SMBUS_INTELGEN4_IG4_REG_H_
|
||||
#define _BUS_SMBUS_INTELGEN4_IG4_REG_H_
|
||||
#ifndef _ICHIIC_IG4_REG_H_
|
||||
#define _ICHIIC_IG4_REG_H_
|
||||
|
||||
/*
|
||||
* 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through
|
||||
@ -619,4 +619,4 @@
|
||||
#define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F)
|
||||
#define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F)
|
||||
|
||||
#endif
|
||||
#endif /* _ICHIIC_IG4_REG_H_ */
|
||||
|
||||
@ -35,13 +35,12 @@
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _BUS_SMBUS_INTELGEN4_IG4_VAR_H_
|
||||
#define _BUS_SMBUS_INTELGEN4_IG4_VAR_H_
|
||||
#ifndef _ICHIIC_IG4_VAR_H_
|
||||
#define _ICHIIC_IG4_VAR_H_
|
||||
|
||||
#include "bus_if.h"
|
||||
#include "device_if.h"
|
||||
#include "pci_if.h"
|
||||
#include "smbus_if.h"
|
||||
#include "iicbus_if.h"
|
||||
|
||||
#define IG4_RBUFSIZE 128
|
||||
@ -75,12 +74,12 @@ struct ig4iic_softc {
|
||||
/*
|
||||
* Locking semantics:
|
||||
*
|
||||
* Functions implementing the smbus interface that interact
|
||||
* Functions implementing the icbus interface that interact
|
||||
* with the controller acquire an exclusive lock on call_lock
|
||||
* to prevent interleaving of calls to the interface and a lock on
|
||||
* io_lock right afterwards, to synchronize controller I/O activity.
|
||||
*
|
||||
* The interrupt handler can only read data while no ig4iic_smb_* call
|
||||
*
|
||||
* The interrupt handler can only read data while no iicbus call
|
||||
* is in progress or while io_lock is dropped during mtx_sleep in
|
||||
* wait_status and set_controller. It is safe to drop io_lock in those
|
||||
* places, because the interrupt handler only accesses those registers:
|
||||
@ -91,7 +90,7 @@ struct ig4iic_softc {
|
||||
*
|
||||
* Locking outside of those places is required to make the content
|
||||
* of rpos/rnext predictable (e.g. whenever data_read is called and in
|
||||
* smb_transaction).
|
||||
* ig4iic_transfer).
|
||||
*/
|
||||
struct sx call_lock;
|
||||
struct mtx io_lock;
|
||||
@ -103,20 +102,8 @@ typedef struct ig4iic_softc ig4iic_softc_t;
|
||||
int ig4iic_attach(ig4iic_softc_t *sc);
|
||||
int ig4iic_detach(ig4iic_softc_t *sc);
|
||||
|
||||
/* SMBus methods */
|
||||
extern smbus_callback_t ig4iic_smb_callback;
|
||||
extern smbus_quick_t ig4iic_smb_quick;
|
||||
extern smbus_sendb_t ig4iic_smb_sendb;
|
||||
extern smbus_recvb_t ig4iic_smb_recvb;
|
||||
extern smbus_writeb_t ig4iic_smb_writeb;
|
||||
extern smbus_writew_t ig4iic_smb_writew;
|
||||
extern smbus_readb_t ig4iic_smb_readb;
|
||||
extern smbus_readw_t ig4iic_smb_readw;
|
||||
extern smbus_pcall_t ig4iic_smb_pcall;
|
||||
extern smbus_bwrite_t ig4iic_smb_bwrite;
|
||||
extern smbus_bread_t ig4iic_smb_bread;
|
||||
extern smbus_trans_t ig4iic_smb_trans;
|
||||
/* iicbus methods */
|
||||
extern iicbus_transfer_t ig4iic_transfer;
|
||||
extern iicbus_reset_t ig4iic_reset;
|
||||
|
||||
#endif
|
||||
#endif /* _ICHIIC_IG4_VAR_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user