* Handle the three other timer interrupts for now, from the AR724x
later. If the interrupts are ACKed even if they're not masked, we get the interrupts again later. Grr. * The AR724x and later chips want the interrupt bits cleared by writing the relevant bit to it, NOT by writing all but the current interrupt to it. Tested: * AR9344, DB120 reference board TODO: * Test ar724x and later chips to ensure no regressions have occured.
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2020-12-20 02:59:44 +00:00
svn path=/head/; revision=263228
@ -362,9 +362,9 @@ apb_filter(void *arg)
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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/* Ack/clear the irq on status register for AR724x */
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/* ACK/clear the given interrupt */
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ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS,
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reg & ~(1 << irq));
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(1 << irq));
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break;
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default:
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/* fallthrough */
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@ -385,7 +385,7 @@ apb_filter(void *arg)
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continue;
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}
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/* Ignore timer interrupts */
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if (irq != 0)
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if (irq != 0 && irq != 8 && irq != 9 && irq != 10)
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printf("Stray APB IRQ %d\n", irq);
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continue;
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}
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