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Don't disable CPU cache in init_486dlc. If BIOS supports Cyrix 486,

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BIOS enables CPU cache and other registers.  If BIOS does not supports
it, CPU cache is disabled at reset time.

This commit closes PR/3292.

PR:		3292
This commit is contained in:
KATO Takenori 1997-04-19 05:25:19 +00:00
parent 4dfa17296a
commit e747d90dbf
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=25015
2 changed files with 2 additions and 6 deletions
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4
sys/amd64/amd64/initcpu.c
View File

@ -26,7 +26,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
* $Id: initcpu.c,v 1.1 1997/03/22 19:00:36 kato Exp $ * $Id: initcpu.c,v 1.2 1997/03/24 07:23:05 kato Exp $
*/ */
#include "opt_cpu.h" #include "opt_cpu.h"
@ -100,8 +100,6 @@ init_486dlc(void)
eflags = read_eflags(); eflags = read_eflags();
disable_intr(); disable_intr();
load_cr0(rcr0() | CR0_CD | CR0_NW);
invd(); invd();
ccr0 = read_cyrix_reg(CCR0); ccr0 = read_cyrix_reg(CCR0);

4
sys/i386/i386/initcpu.c
View File

@ -26,7 +26,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
* $Id: initcpu.c,v 1.1 1997/03/22 19:00:36 kato Exp $ * $Id: initcpu.c,v 1.2 1997/03/24 07:23:05 kato Exp $
*/ */
#include "opt_cpu.h" #include "opt_cpu.h"
@ -100,8 +100,6 @@ init_486dlc(void)
eflags = read_eflags(); eflags = read_eflags();
disable_intr(); disable_intr();
load_cr0(rcr0() | CR0_CD | CR0_NW);
invd(); invd();
ccr0 = read_cyrix_reg(CCR0); ccr0 = read_cyrix_reg(CCR0);