From e8e57bc572653b5479fd48e0d0b8863d487e12b3 Mon Sep 17 00:00:00 2001 From: grehan Date: Mon, 9 Feb 2004 07:04:01 +0000 Subject: [PATCH] Disable branch-target instruction cache on MPC7457 as outlined in Motorola processor errata. Submitted by: Suleiman Souhlal --- sys/powerpc/powerpc/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sys/powerpc/powerpc/cpu.c b/sys/powerpc/powerpc/cpu.c index b1459a43e4d1..1c5fa2a2b301 100644 --- a/sys/powerpc/powerpc/cpu.c +++ b/sys/powerpc/powerpc/cpu.c @@ -177,8 +177,9 @@ cpu_setup(u_int cpuid) case MPC7457: case MPC7455: case MPC7450: - /* Disable BTIC on 7450 Rev 2.0 or earlier */ - if ((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) + /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */ + if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) + || (pvr >> 16) == MPC7457) hid0 &= ~HID0_BTIC; /* Select NAP mode. */ hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);