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Add the ath0 EEPROM hints required to detect the on-chip wifi.

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This allows the on-chip wifi to work; however it's not yet fully
tested.

ath0: Vendor=0x168c, Device=0x0031
ath0: Vendor=0x168c, Device=0x0031
ath0: <Atheros AR934x> at mem 0x18100000-0x1811ffff irq 0 on nexus0
...
ath0: [HT] enabling HT modes
ath0: [HT] enabling short-GI in 20MHz mode
ath0: [HT] 1 stream STBC receive enabled
ath0: [HT] 1 stream STBC transmit enabled
ath0: [HT] 2 RX streams; 2 TX streams

Tested:

* DB120 development board
This commit is contained in:
Adrian Chadd 2014-02-14 04:03:17 +00:00
parent 14a5dc1780
commit e9330c7b33
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=261869
1 changed files with 10 additions and 0 deletions
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10
sys/mips/conf/DB120.hints
View File

@ -50,6 +50,16 @@ hint.arge.1.media=1000
hint.arge.1.fduplex=1
hint.arge.1.miimode=1 # GMII
# ath0: Where the ART is - last 64k in the flash
hint.ath.0.eepromaddr=0x1fff0000
hint.ath.0.eepromsize=16384
# ath1: it's different; it's a PCIe attached device, so
# we instead need to teach the PCIe bridge code about it
# (ie, the 'early pci fixup' stuff that programs the PCIe
# host registers on the NIC) and then we teach ath where
# to find it.
# flash layout:
#
# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)