d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Import ioat(4) driver

Browse Source 
I/OAT is also referred to as Crystal Beach DMA and is a Platform Storage
Extension (PSE) on some Intel server platforms.

This driver currently supports DMA descriptors only and is part of a
larger effort to upstream an interconnect between multiple systems using
the Non-Transparent Bridge (NTB) PSE.

For now, this driver is only built on AMD64 platforms.  It may be ported
to work on i386 later, if that is desired.  The hardware is exclusive to
x86.

Further documentation on ioat(4), including API documentation and usage,
can be found in the new manual page.

Bring in a test tool, ioatcontrol(8), in tools/tools/ioat.  The test
tool is not hooked up to the build and is not intended for end users.

Submitted by:	jimharris, Carl Delsey <carl.r.delsey@intel.com>
Reviewed by:	jimharris (reviewed my changes)
Approved by:	markj (mentor)
Relnotes:	yes
Sponsored by:	Intel
Sponsored by:	EMC / Isilon Storage Division
Differential Revision:	https://reviews.freebsd.org/D3456
This commit is contained in:
Conrad Meyer 2015-08-24 19:32:03 +00:00
parent 3166be0fb4
commit e974f91c38
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=287117
15 changed files with 2267 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
share/man/man4/Makefile
View File

@ -207,6 +207,7 @@ MAN= aac.4 \
intpm.4 \
intro.4 \
${_io.4} \
${_ioat.4} \
ip.4 \
ip6.4 \
ipfirewall.4 \
@ -800,6 +801,7 @@ _xnb.4= xnb.4
.if ${MACHINE_CPUARCH} == "amd64"
_if_ntb.4= if_ntb.4
_ioat.4= ioat.4
_ntb.4= ntb.4
_ntb_hw.4= ntb_hw.4
_qlxge.4= qlxge.4

153
share/man/man4/ioat.4 Normal file
View File

@ -0,0 +1,153 @@
.\" Copyright (c) 2015 EMC / Isilon Storage Division
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd August 24, 2015
.Dt IOAT 4
.Os
.Sh NAME
.Nm I/OAT
.Nd Intel I/O Acceleration Technology
.Sh SYNOPSIS
.Cd "device ioat"
In
.Xr loader.conf 5 :
.Pp
.Cd hw.ioat.force_legacy_interrupts=0
.Pp
In
.Xr loader.conf 5 or
.Xr sysctl.conf 5 :
.Pp
.Cd hw.ioat.enable_ioat_test=0
.Cd hw.ioat.debug_level=0
(only critical errors; maximum of 3)
.Pp
.Ft typedef void
.Fn (*bus_dmaengine_callback_t) "void *arg"
.Pp
.Ft bus_dmaengine_t
.Fn ioat_get_dmaengine "uint32_t channel_index"
.Ft void
.Fn ioat_acquire "bus_dmaengine_t dmaengine"
.Ft void
.Fn ioat_release "bus_dmaengine_t dmaengine"
.Ft struct bus_dmadesc *
.Fo ioat_copy
.Fa "bus_dmaengine_t dmaengine"
.Fa "bus_addr_t dst"
.Fa "bus_addr_t src"
.Fa "bus_size_t len"
.Fa "bus_dmaengine_callback_t callback_fn"
.Fa "void *callback_arg"
.Fa "uint32_t flags"
.Fc
.Ft struct bus_dmadesc *
.Fo ioat_null
.Fa "bus_dmaengine_t dmaengine"
.Fa "bus_dmaengine_callback_t callback_fn"
.Fa "void *callback_arg"
.Fa "uint32_t flags"
.Fc
.Sh DESCRIPTION
The
.Nm
driver provides a kernel API to a variety of DMA engines on some Intel server
platforms.
.Pp
There is a number of DMA channels per CPU package.
(Typically 4 or 8.)
Each may be used independently.
Operations on a single channel proceed sequentially.
.Pp
Copy operations may be used to offload memory copies to the DMA engines.
.Pp
Null operations do nothing, but may be used to test the interrupt and callback
mechanism.
.Pp
All operations can optionally trigger an interrupt at completion with the
.Ar DMA_EN_INT
flag.
For example, a user might submit multiple operations to the same channel and
only enable an interrupt and callback for the last operation.
.Sh USAGE
A typical user will lookup the DMA engine object for a given channel with
.Fn ioat_get_dmaengine .
When the user wants to offload a copy, they will first
.Fn ioat_acquire
the
.Ar bus_dmaengine_t
object for exclusive access to enqueue operations on that channel.
Then, they will submit one or more operations using
.Fn ioat_copy
or
.Fn ioat_null .
Finally, they will
.Fn ioat_release
the
.Ar bus_dmaengine_t
to drop their exclusive access to the channel.
The routine they provided for the
.Fa callback_fn
argument will be invoked with the provided
.Fa callback_arg
when the operation is complete.
.Pp
For an example of usage, see
.Pa src/sys/dev/ioat/ioat_test.c .
.Sh FILES
.Bl -tag -compat
.It Pa /dev/ioat_test
test device for
.Xr ioatcontrol 8
.El
.Sh SEE ALSO
.Xr ioatcontrol 8
.Sh HISTORY
The
.Nm
driver first appeared in
.Fx 11.0 .
.Sh AUTHORS
The
.Nm
driver was developed by
.An \&Jim Harris Aq Mt jimharris@FreeBSD.org ,
and
.An \&Carl Delsey Aq Mt carl.r.delsey@intel.com .
This manual page was written by
.An \&Conrad Meyer Aq Mt cem@FreeBSD.org .
.Sh CAVEATS
Copy operation takes bus addresses as parameters, not virtual addresses.
.Pp
Copies larger than max transfer size (1MB) are not supported.
Future versions will likely support this by breaking up the transfer into
smaller sizes.
.Sh BUGS
The
.Nm
driver only supports copy and null operations at this time.
The driver does not yet support advanced DMA modes, such as XOR, that some
I/OAT devices support.

1
sys/amd64/conf/NOTES
View File

@ -553,6 +553,7 @@ device tpm
device padlock_rng # VIA Padlock RNG
device rdrand_rng # Intel Bull Mountain RNG
device aesni # AES-NI OpenCrypto module
device ioat # Intel I/OAT DMA engine
#
# Laptop/Notebook options:

2
sys/conf/files.amd64
View File

@ -205,6 +205,8 @@ dev/if_ndis/if_ndis_pccard.c optional ndis pccard
dev/if_ndis/if_ndis_pci.c optional ndis cardbus | ndis pci
dev/if_ndis/if_ndis_usb.c optional ndis usb
dev/io/iodev.c optional io
dev/ioat/ioat.c optional ioat pci
dev/ioat/ioat_test.c optional ioat pci
dev/ipmi/ipmi.c optional ipmi
dev/ipmi/ipmi_acpi.c optional ipmi acpi
dev/ipmi/ipmi_isa.c optional ipmi isa

1009
sys/dev/ioat/ioat.c Normal file
View File

File diff suppressed because it is too large Load Diff

77
sys/dev/ioat/ioat.h Normal file
View File

@ -0,0 +1,77 @@
/*-
* Copyright (C) 2012 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
__FBSDID("$FreeBSD$");
#ifndef __IOAT_H__
#define __IOAT_H__
#include <sys/param.h>
#include <machine/bus.h>
/*
* This file defines the public interface to the IOAT driver.
*/
/*
* Enables an interrupt for this operation. Typically, you would only enable
* this on the last operation in a group
*/
#define DMA_INT_EN 0x1
#define DMA_ALL_FLAGS (DMA_INT_EN)
typedef void *bus_dmaengine_t;
struct bus_dmadesc;
typedef void (*bus_dmaengine_callback_t)(void *arg);
/*
* Called first to acquire a reference to the DMA channel
*/
bus_dmaengine_t ioat_get_dmaengine(uint32_t channel_index);
/*
* Acquire must be called before issuing an operation to perform. Release is
* called after. Multiple operations can be issued within the context of one
* acquire and release
*/
void ioat_acquire(bus_dmaengine_t dmaengine);
void ioat_release(bus_dmaengine_t dmaengine);
/* Issues the copy data operation */
struct bus_dmadesc *ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
void *callback_arg, uint32_t flags);
/*
* Issues a null operation. This issues the operation to the hardware, but the
* hardware doesn't do anything with it.
*/
struct bus_dmadesc *ioat_null(bus_dmaengine_t dmaengine,
bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
#endif /* __IOAT_H__ */

104
sys/dev/ioat/ioat_hw.h Normal file
View File

@ -0,0 +1,104 @@
/*-
* Copyright (C) 2012 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
__FBSDID("$FreeBSD$");
#ifndef __IOAT_HW_H__
#define __IOAT_HW_H__
#define IOAT_MAX_CHANNELS 32
#define IOAT_CHANCNT_OFFSET 0x00
#define IOAT_XFERCAP_OFFSET 0x01
#define IOAT_GENCTRL_OFFSET 0x02
#define IOAT_INTRCTRL_OFFSET 0x03
#define IOAT_INTRCTRL_MASTER_INT_EN 0x01
#define IOAT_ATTNSTATUS_OFFSET 0x04
#define IOAT_CBVER_OFFSET 0x08
#define IOAT_VER_3_0 0x30
#define IOAT_VER_3_3 0x33
#define IOAT_INTRDELAY_OFFSET 0x0C
#define IOAT_CS_STATUS_OFFSET 0x0E
#define IOAT_DMACAPABILITY_OFFSET 0x10
/* DMA Channel Registers */
#define IOAT_CHANCTRL_OFFSET 0x80
#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200
#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
#define IOAT_CHANCTRL_INT_REARM 0x0001
#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\
IOAT_CHANCTRL_ANY_ERR_ABORT_EN)
#define IOAT_CHANCMD_OFFSET 0x84
#define IOAT_CHANCMD_RESET 0x20
#define IOAT_CHANCMD_SUSPEND 0x04
#define IOAT_DMACOUNT_OFFSET 0x86
#define IOAT_CHANSTS_OFFSET_LOW 0x88
#define IOAT_CHANSTS_OFFSET_HIGH 0x8C
#define IOAT_CHANSTS_OFFSET 0x88
#define IOAT_CHANSTS_STATUS 0x7ULL
#define IOAT_CHANSTS_ACTIVE 0x0
#define IOAT_CHANSTS_IDLE 0x1
#define IOAT_CHANSTS_SUSPENDED 0x2
#define IOAT_CHANSTS_HALTED 0x3
#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL
#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL)
#define IOAT_CHAINADDR_OFFSET_LOW 0x90
#define IOAT_CHAINADDR_OFFSET_HIGH 0x94
#define IOAT_CHANCMP_OFFSET_LOW 0x98
#define IOAT_CHANCMP_OFFSET_HIGH 0x9C
#define IOAT_CHANERR_OFFSET 0xA8
#define IOAT_CFG_CHANERR_INT_OFFSET 0x180
#define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184
#define IOAT_MIN_ORDER 4
#define IOAT_MAX_ORDER 16
#endif /* __IOAT_HW_H__ */

447
sys/dev/ioat/ioat_internal.h Normal file
View File

@ -0,0 +1,447 @@
/*-
* Copyright (C) 2012 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
__FBSDID("$FreeBSD$");
#ifndef __IOAT_INTERNAL_H__
#define __IOAT_INTERNAL_H__
#define DEVICE2SOFTC(dev) ((struct ioat_softc *) device_get_softc(dev))
#define ioat_read_chancnt(ioat) \
ioat_read_1((ioat), IOAT_CHANCNT_OFFSET)
#define ioat_read_xfercap(ioat) \
ioat_read_1((ioat), IOAT_XFERCAP_OFFSET)
#define ioat_write_intrctrl(ioat, value) \
ioat_write_1((ioat), IOAT_INTRCTRL_OFFSET, (value))
#define ioat_read_cbver(ioat) \
(ioat_read_1((ioat), IOAT_CBVER_OFFSET) & 0xFF)
#define ioat_read_dmacapability(ioat) \
ioat_read_4((ioat), IOAT_DMACAPABILITY_OFFSET)
#define ioat_write_chanctrl(ioat, value) \
ioat_write_2((ioat), IOAT_CHANCTRL_OFFSET, (value))
static __inline uint64_t
ioat_bus_space_read_8_lower_first(bus_space_tag_t tag,
bus_space_handle_t handle, bus_size_t offset)
{
return (bus_space_read_4(tag, handle, offset) |
((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32);
}
static __inline void
ioat_bus_space_write_8_lower_first(bus_space_tag_t tag,
bus_space_handle_t handle, bus_size_t offset, uint64_t val)
{
bus_space_write_4(tag, handle, offset, val);
bus_space_write_4(tag, handle, offset + 4, val >> 32);
}
#ifdef i386
#define ioat_bus_space_read_8 ioat_bus_space_read_8_lower_first
#define ioat_bus_space_write_8 ioat_bus_space_write_8_lower_first
#else
#define ioat_bus_space_read_8(tag, handle, offset) \
bus_space_read_8((tag), (handle), (offset))
#define ioat_bus_space_write_8(tag, handle, offset, val) \
bus_space_write_8((tag), (handle), (offset), (val))
#endif
#define ioat_read_1(ioat, offset) \
bus_space_read_1((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset))
#define ioat_read_2(ioat, offset) \
bus_space_read_2((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset))
#define ioat_read_4(ioat, offset) \
bus_space_read_4((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset))
#define ioat_read_8(ioat, offset) \
ioat_bus_space_read_8((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset))
#define ioat_read_double_4(ioat, offset) \
ioat_bus_space_read_8_lower_first((ioat)->pci_bus_tag, \
(ioat)->pci_bus_handle, (offset))
#define ioat_write_1(ioat, offset, value) \
bus_space_write_1((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset), (value))
#define ioat_write_2(ioat, offset, value) \
bus_space_write_2((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset), (value))
#define ioat_write_4(ioat, offset, value) \
bus_space_write_4((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset), (value))
#define ioat_write_8(ioat, offset, value) \
ioat_bus_space_write_8((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
(offset), (value))
#define ioat_write_double_4(ioat, offset, value) \
ioat_bus_space_write_8_lower_first((ioat)->pci_bus_tag, \
(ioat)->pci_bus_handle, (offset), (value))
MALLOC_DECLARE(M_IOAT);
SYSCTL_DECL(_hw_ioat);
void ioat_log_message(int verbosity, char *fmt, ...);
struct ioat_dma_hw_descriptor {
uint32_t size;
union {
uint32_t control_raw;
struct {
uint32_t int_enable:1;
uint32_t src_snoop_disable:1;
uint32_t dest_snoop_disable:1;
uint32_t completion_update:1;
uint32_t fence:1;
uint32_t null:1;
uint32_t src_page_break:1;
uint32_t dest_page_break:1;
uint32_t bundle:1;
uint32_t dest_dca:1;
uint32_t hint:1;
uint32_t reserved:13;
#define IOAT_OP_COPY 0x00
uint32_t op:8;
} control;
} u;
uint64_t src_addr;
uint64_t dest_addr;
uint64_t next;
uint64_t reserved;
uint64_t reserved2;
uint64_t user1;
uint64_t user2;
};
struct ioat_fill_hw_descriptor {
uint32_t size;
union {
uint32_t control_raw;
struct {
uint32_t int_enable:1;
uint32_t reserved:1;
uint32_t dest_snoop_disable:1;
uint32_t completion_update:1;
uint32_t fence:1;
uint32_t reserved2:2;
uint32_t dest_page_break:1;
uint32_t bundle:1;
uint32_t reserved3:15;
#define IOAT_OP_FILL 0x01
uint32_t op:8;
} control;
} u;
uint64_t src_data;
uint64_t dest_addr;
uint64_t next;
uint64_t reserved;
uint64_t next_dest_addr;
uint64_t user1;
uint64_t user2;
};
struct ioat_xor_hw_descriptor {
uint32_t size;
union {
uint32_t control_raw;
struct {
uint32_t int_enable:1;
uint32_t src_snoop_disable:1;
uint32_t dest_snoop_disable:1;
uint32_t completion_update:1;
uint32_t fence:1;
uint32_t src_count:3;
uint32_t bundle:1;
uint32_t dest_dca:1;
uint32_t hint:1;
uint32_t reserved:13;
#define IOAT_OP_XOR 0x87
#define IOAT_OP_XOR_VAL 0x88
uint32_t op:8;
} control;
} u;
uint64_t src_addr;
uint64_t dest_addr;
uint64_t next;
uint64_t src_addr2;
uint64_t src_addr3;
uint64_t src_addr4;
uint64_t src_addr5;
};
struct ioat_xor_ext_hw_descriptor {
uint64_t src_addr6;
uint64_t src_addr7;
uint64_t src_addr8;
uint64_t next;
uint64_t reserved[4];
};
struct ioat_pq_hw_descriptor {
uint32_t size;
union {
uint32_t control_raw;
struct {
uint32_t int_enable:1;
uint32_t src_snoop_disable:1;
uint32_t dest_snoop_disable:1;
uint32_t completion_update:1;
uint32_t fence:1;
uint32_t src_count:3;
uint32_t bundle:1;
uint32_t dest_dca:1;
uint32_t hint:1;
uint32_t p_disable:1;
uint32_t q_disable:1;
uint32_t reserved:11;
#define IOAT_OP_PQ 0x89
#define IOAT_OP_PQ_VAL 0x8a
uint32_t op:8;
} control;
} u;
uint64_t src_addr;
uint64_t p_addr;
uint64_t next;
uint64_t src_addr2;
uint64_t src_addr3;
uint8_t coef[8];
uint64_t q_addr;
};
struct ioat_pq_ext_hw_descriptor {
uint64_t src_addr4;
uint64_t src_addr5;
uint64_t src_addr6;
uint64_t next;
uint64_t src_addr7;
uint64_t src_addr8;
uint64_t reserved[2];
};
struct ioat_pq_update_hw_descriptor {
uint32_t size;
union {
uint32_t control_raw;
struct {
uint32_t int_enable:1;
uint32_t src_snoop_disable:1;
uint32_t dest_snoop_disable:1;
uint32_t completion_update:1;
uint32_t fence:1;
uint32_t src_cnt:3;
uint32_t bundle:1;
uint32_t dest_dca:1;
uint32_t hint:1;
uint32_t p_disable:1;
uint32_t q_disable:1;
uint32_t reserved:3;
uint32_t coef:8;
#define IOAT_OP_PQ_UP 0x8b
uint32_t op:8;
} control;
} u;
uint64_t src_addr;
uint64_t p_addr;
uint64_t next;
uint64_t src_addr2;
uint64_t p_src;
uint64_t q_src;
uint64_t q_addr;
};
struct ioat_raw_hw_descriptor {
uint64_t field[8];
};
struct bus_dmadesc {
bus_dmaengine_callback_t callback_fn;
void *callback_arg;
};
struct ioat_descriptor {
struct bus_dmadesc bus_dmadesc;
union {
struct ioat_dma_hw_descriptor *dma;
struct ioat_fill_hw_descriptor *fill;
struct ioat_xor_hw_descriptor *xor;
struct ioat_xor_ext_hw_descriptor *xor_ext;
struct ioat_pq_hw_descriptor *pq;
struct ioat_pq_ext_hw_descriptor *pq_ext;
struct ioat_raw_hw_descriptor *raw;
} u;
uint32_t id;
uint32_t length;
enum validate_flags *validate_result;
bus_addr_t hw_desc_bus_addr;
};
/* One of these per allocated PCI device. */
struct ioat_softc {
bus_dmaengine_t dmaengine;
#define to_ioat_softc(_dmaeng) \
({ \
bus_dmaengine_t *_p = (_dmaeng); \
(struct ioat_softc *)((char *)_p - \
offsetof(struct ioat_softc, dmaengine)); \
})
int version;
struct mtx submit_lock;
int num_interrupts;
device_t device;
bus_space_tag_t pci_bus_tag;
bus_space_handle_t pci_bus_handle;
int pci_resource_id;
struct resource *pci_resource;
uint32_t max_xfer_size;
struct resource *res;
int rid;
void *tag;
bus_dma_tag_t hw_desc_tag;
bus_dmamap_t hw_desc_map;
bus_dma_tag_t comp_update_tag;
bus_dmamap_t comp_update_map;
uint64_t *comp_update;
bus_addr_t comp_update_bus_addr;
struct callout timer;
boolean_t is_resize_pending;
boolean_t is_completion_pending;
boolean_t is_reset_pending;
boolean_t is_channel_running;
boolean_t is_waiting_for_ack;
uint32_t xfercap_log;
uint32_t head;
uint32_t tail;
uint16_t reserved;
uint32_t ring_size_order;
bus_addr_t last_seen;
struct ioat_descriptor **ring;
struct mtx cleanup_lock;
};
static inline uint64_t
ioat_get_chansts(struct ioat_softc *ioat)
{
uint64_t status;
if (ioat->version >= IOAT_VER_3_3)
status = ioat_read_8(ioat, IOAT_CHANSTS_OFFSET);
else
/* Must read lower 4 bytes before upper 4 bytes. */
status = ioat_read_double_4(ioat, IOAT_CHANSTS_OFFSET);
return (status);
}
static inline void
ioat_write_chancmp(struct ioat_softc *ioat, uint64_t addr)
{
if (ioat->version >= IOAT_VER_3_3)
ioat_write_8(ioat, IOAT_CHANCMP_OFFSET_LOW, addr);
else
ioat_write_double_4(ioat, IOAT_CHANCMP_OFFSET_LOW, addr);
}
static inline void
ioat_write_chainaddr(struct ioat_softc *ioat, uint64_t addr)
{
if (ioat->version >= IOAT_VER_3_3)
ioat_write_8(ioat, IOAT_CHAINADDR_OFFSET_LOW, addr);
else
ioat_write_double_4(ioat, IOAT_CHAINADDR_OFFSET_LOW, addr);
}
static inline boolean_t
is_ioat_active(uint64_t status)
{
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
}
static inline boolean_t
is_ioat_idle(uint64_t status)
{
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_IDLE);
}
static inline boolean_t
is_ioat_halted(uint64_t status)
{
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
}
static inline boolean_t
is_ioat_suspended(uint64_t status)
{
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
}
static inline void
ioat_suspend(struct ioat_softc *ioat)
{
ioat_write_1(ioat, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_SUSPEND);
}
static inline void
ioat_reset(struct ioat_softc *ioat)
{
ioat_write_1(ioat, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_RESET);
}
static inline boolean_t
ioat_reset_pending(struct ioat_softc *ioat)
{
uint8_t cmd;
cmd = ioat_read_1(ioat, IOAT_CHANCMD_OFFSET);
return ((cmd & IOAT_CHANCMD_RESET) != 0);
}
#endif /* __IOAT_INTERNAL_H__ */

256
sys/dev/ioat/ioat_test.c Normal file
View File

@ -0,0 +1,256 @@
/*-
* Copyright (C) 2012 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/ioccom.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include "ioat.h"
#include "ioat_hw.h"
#include "ioat_internal.h"
#include "ioat_test.h"
MALLOC_DEFINE(M_IOAT_TEST, "ioat_test", "ioat test allocations");
#define IOAT_TEST_SIZE 0x40000
#define IOAT_MAX_BUFS 8
struct test_transaction {
uint8_t num_buffers;
void *buf[IOAT_MAX_BUFS];
uint32_t length;
struct ioat_test *test;
};
static int g_thread_index = 1;
static struct cdev *g_ioat_cdev = NULL;
static void
ioat_test_transaction_destroy(struct test_transaction *tx)
{
int i;
for (i = 0; i < IOAT_MAX_BUFS; i++) {
if (tx->buf[i] != NULL) {
contigfree(tx->buf[i], IOAT_TEST_SIZE, M_IOAT_TEST);
tx->buf[i] = NULL;
}
}
free(tx, M_IOAT_TEST);
}
static struct
test_transaction *ioat_test_transaction_create(uint8_t num_buffers,
uint32_t buffer_size)
{
struct test_transaction *tx;
int i;
tx = malloc(sizeof(struct test_transaction), M_IOAT_TEST, M_NOWAIT | M_ZERO);
if (tx == NULL)
return (NULL);
tx->num_buffers = num_buffers;
tx->length = buffer_size;
for (i = 0; i < num_buffers; i++) {
tx->buf[i] = contigmalloc(buffer_size, M_IOAT_TEST, M_NOWAIT,
0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0);
if (tx->buf[i] == NULL) {
ioat_test_transaction_destroy(tx);
return (NULL);
}
}
return (tx);
}
static void
ioat_dma_test_callback(void *arg)
{
struct test_transaction *tx;
struct ioat_test *test;
tx = arg;
test = tx->test;
if (memcmp(tx->buf[0], tx->buf[1], tx->length) != 0) {
ioat_log_message(0, "miscompare found\n");
test->status = IOAT_TEST_MISCOMPARE;
}
atomic_add_32(&test->num_completions, 1);
ioat_test_transaction_destroy(tx);
if (test->num_completions == test->num_loops)
wakeup(test);
}
static void
ioat_dma_test(void *arg)
{
struct test_transaction *tx;
struct ioat_test *test;
bus_dmaengine_t dmaengine;
uint32_t loops;
int index, i;
test = arg;
loops = test->num_loops;
test->status = IOAT_TEST_OK;
test->num_completions = 0;
index = g_thread_index++;
dmaengine = ioat_get_dmaengine(test->channel_index);
if (dmaengine == NULL) {
ioat_log_message(0, "Couldn't acquire dmaengine\n");
test->status = IOAT_TEST_NO_DMA_ENGINE;
return;
}
ioat_log_message(0, "Thread %d: num_loops remaining: 0x%07x\n", index,
test->num_loops);
for (loops = 0; loops < test->num_loops; loops++) {
bus_addr_t src, dest;
if (loops % 0x10000 == 0) {
ioat_log_message(0, "Thread %d: "
"num_loops remaining: 0x%07x\n", index,
test->num_loops - loops);
}
tx = ioat_test_transaction_create(2, IOAT_TEST_SIZE);
if (tx == NULL) {
ioat_log_message(0, "tx == NULL - memory exhausted\n");
atomic_add_32(&test->num_completions, 1);
test->status = IOAT_TEST_NO_MEMORY;
continue;
}
tx->test = test;
wmb();
/* fill in source buffer */
for (i = 0; i < (IOAT_TEST_SIZE / sizeof(uint32_t)); i++) {
uint32_t val = i + (loops << 16) + (index << 28);
((uint32_t *)tx->buf[0])[i] = ~val;
((uint32_t *)tx->buf[1])[i] = val;
}
src = pmap_kextract((vm_offset_t)tx->buf[0]);
dest = pmap_kextract((vm_offset_t)tx->buf[1]);
ioat_acquire(dmaengine);
ioat_copy(dmaengine, src, dest, IOAT_TEST_SIZE,
ioat_dma_test_callback, tx, DMA_INT_EN);
ioat_release(dmaengine);
}
while (test->num_completions < test->num_loops)
tsleep(test, 0, "compl", 5 * hz);
}
static int
ioat_test_open(struct cdev *dev, int flags, int fmt, struct thread *td)
{
return (0);
}
static int
ioat_test_close(struct cdev *dev, int flags, int fmt, struct thread *td)
{
return (0);
}
static int
ioat_test_ioctl(struct cdev *dev, unsigned long cmd, caddr_t arg, int flag,
struct thread *td)
{
switch (cmd) {
case IOAT_DMATEST:
ioat_dma_test(arg);
break;
default:
return (EINVAL);
}
return (0);
}
static struct cdevsw ioat_cdevsw = {
.d_version = D_VERSION,
.d_flags = 0,
.d_open = ioat_test_open,
.d_close = ioat_test_close,
.d_ioctl = ioat_test_ioctl,
.d_name = "ioat_test",
};
static int
sysctl_enable_ioat_test(SYSCTL_HANDLER_ARGS)
{
int error, enabled;
enabled = (g_ioat_cdev != NULL);
error = sysctl_handle_int(oidp, &enabled, 0, req);
if (error != 0 || req->newptr == NULL)
return (error);
if (enabled != 0 && g_ioat_cdev == NULL) {
g_ioat_cdev = make_dev(&ioat_cdevsw, 0, UID_ROOT, GID_WHEEL,
0600, "ioat_test");
} else if (enabled == 0 && g_ioat_cdev != NULL) {
destroy_dev(g_ioat_cdev);
g_ioat_cdev = NULL;
}
return (0);
}
SYSCTL_PROC(_hw_ioat, OID_AUTO, enable_ioat_test, CTLTYPE_INT | CTLFLAG_RW,
0, 0, sysctl_enable_ioat_test, "I",
"Non-zero: Enable the /dev/ioat_test device");

46
sys/dev/ioat/ioat_test.h Normal file
View File

@ -0,0 +1,46 @@
/*-
* Copyright (C) 2012 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
__FBSDID("$FreeBSD$");
#ifndef __IOAT_TEST_H__
#define __IOAT_TEST_H__
struct ioat_test {
uint32_t channel_index;
uint32_t num_loops;
volatile uint32_t num_completions;
uint32_t status;
};
#define IOAT_TEST_OK 0
#define IOAT_TEST_NO_DMA_ENGINE 1
#define IOAT_TEST_NO_MEMORY 2
#define IOAT_TEST_MISCOMPARE 3
#define IOAT_DMATEST _IOWR('i', 0, struct ioat_test)
#endif /* __IOAT_TEST_H__ */

2
sys/modules/Makefile
View File

@ -158,6 +158,7 @@ SUBDIR= \
${_iir} \
imgact_binmisc \
${_io} \
${_ioat} \
${_ipoib} \
${_ipdivert} \
${_ipfilter} \
@ -630,6 +631,7 @@ _x86bios= x86bios
.if ${MACHINE_CPUARCH} == "amd64"
_cloudabi64= cloudabi64
_ioat= ioat
_ixl= ixl
_ixlv= ixlv
_linux64= linux64

15
sys/modules/ioat/Makefile Normal file
View File

@ -0,0 +1,15 @@
# ioat Loadable Kernel Module
#
# $FreeBSD$
IOAT_SRC_PATH = ${.CURDIR}/../..
.PATH: ${IOAT_SRC_PATH}/dev/ioat
KMOD= ioat
SRCS= ioat.c ioat_test.c
SRCS+= device_if.h bus_if.h pci_if.h
CFLAGS+= -I${IOAT_SRC_PATH}
.include <bsd.kmod.mk>

9
tools/tools/ioat/Makefile Normal file
View File

@ -0,0 +1,9 @@
# $FreeBSD$
PROG= ioatcontrol
SRCS= ioatcontrol.c
MAN= ioatcontrol.8
CFLAGS+= -I${.CURDIR:H:H:H}/sys/dev/ioat
WARNS?= 6
.include <bsd.prog.mk>

75
tools/tools/ioat/ioatcontrol.8 Normal file
View File

@ -0,0 +1,75 @@
.\" Copyright (c) 2015 EMC / Isilon Storage Division
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd August 24, 2015
.Dt IOATCONTROL 8
.Os
.Sh NAME
.Nm ioatcontrol
.Nd Userspace tool to test
.Xr ioat 4
.Sh SYNOPSIS
.Nm
.Ar channel_number
.Ar num_loops
.Sh DESCRIPTION
.Nm
allows one to issue some number of test operations to the
.Xr ioat 4
driver on a specific hardware channel.
.Pp
Each loop will allocate two chunks of memory, write data patterns to them,
submit a DMA request to copy one buffer to the other, and compare the contents
in the callback.
If the contents are not as expected, an error is reported.
.Sh FILES
.Pa /dev/ioat_test
.Pp
The interface between
.Nm
and
.Xr ioat 4 .
.Nm
exposes it with
.Cd hw.ioat.enable_ioat_test=1 .
.Sh SEE ALSO
.Xr ioat 4
.Sh HISTORY
The
.Xr ioat 4
driver first appeared in
.Fx 11.0 .
.Sh AUTHORS
The
.Xr ioat 4
driver and
.Nm
tool were developed by
.An \&Jim Harris Aq Mt jimharris@FreeBSD.org ,
and
.An \&Carl Delsey Aq Mt carl.r.delsey@intel.com .
This manual page was written by
.An \&Conrad Meyer Aq Mt cem@FreeBSD.org .

69
tools/tools/ioat/ioatcontrol.c Normal file
View File

@ -0,0 +1,69 @@
/*-
* Copyright (C) 2012 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
__FBSDID("$FreeBSD$");
#include <sys/ioctl.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <sysexits.h>
#include <unistd.h>
#include "ioat_test.h"
int
main(int argc, char **argv)
{
struct ioat_test t;
int fd;
if (argc < 3) {
printf("Usage: %s <channel #> <num_loops>\n", argv[0]);
return (EX_USAGE);
}
t.channel_index = atoi(argv[1]);
if (t.channel_index > 8) {
printf("Channel number must be between 0 and 7.\n");
return (EX_USAGE);
}
t.num_loops = atoi(argv[2]);
fd = open("/dev/ioat_test", O_RDWR);
if (fd < 0) {
printf("Cannot open /dev/ioat_test\n");
return (EX_UNAVAILABLE);
}
(void)ioctl(fd, IOAT_DMATEST, &t);
close(fd);
return (t.status);
}