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Now that we have UARTs running with fast interrupt handlers the ata

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driver's i/o ops must be locked to avoid chaos.  Extend the cambria
bus tag to support ata and add a spin lock.  The ata driver is
hacked to use that instead of it's builtin hack for ixp425.  Once
the ata driver is fixed to not be confused about byte order we can
generalize the cambria bus tag code and make it generally useful.

While here take advantage of our being ixp435-specific to remove
delays when switching between byte+word accesses and to eliminate
the 2us delay for the uarts (the spin lock overhead looks to do
this for us).
This commit is contained in:
Sam Leffler 2009-06-23 19:29:23 +00:00
parent dbdc502de6
commit ea158edaa6
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=194753
2 changed files with 207 additions and 34 deletions
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58
sys/arm/xscale/ixp425/avila_ata.c
View File

@ -119,7 +119,7 @@ ata_getconfig(struct ixp425_softc *sa)
/* XXX honor hint? (but then no multi-board support) */
/* XXX total hack */
if ((cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435)
if (cpu_is_ixp43x())
return &configs[1]; /* Cambria */
if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0)
return &configs[0]; /* Avila */
@ -191,31 +191,41 @@ ata_avila_attach(device_t dev)
__func__, config->basealt, config->sizealt);
sc->sc_16bit_off = config->off16;
/*
* Craft special resource for ATA bus space ops
* that go through the expansion bus and require
* special hackery to ena/dis 16-bit operations.
*
* XXX probably should just make this generic for
* accessing the expansion bus.
*/
sc->sc_expbus_tag.bs_cookie = sc; /* NB: backpointer */
/* read single */
sc->sc_expbus_tag.bs_r_1 = ata_bs_r_1,
sc->sc_expbus_tag.bs_r_2 = ata_bs_r_2,
/* read multiple */
sc->sc_expbus_tag.bs_rm_2 = ata_bs_rm_2,
sc->sc_expbus_tag.bs_rm_2_s = ata_bs_rm_2_s,
/* write (single) */
sc->sc_expbus_tag.bs_w_1 = ata_bs_w_1,
sc->sc_expbus_tag.bs_w_2 = ata_bs_w_2,
/* write multiple */
sc->sc_expbus_tag.bs_wm_2 = ata_bs_wm_2,
sc->sc_expbus_tag.bs_wm_2_s = ata_bs_wm_2_s,
if (config->base16 != CAMBRIA_CFSEL0_HWBASE) {
/*
* Craft special resource for ATA bus space ops
* that go through the expansion bus and require
* special hackery to ena/dis 16-bit operations.
*
* XXX probably should just make this generic for
* accessing the expansion bus.
*/
sc->sc_expbus_tag.bs_cookie = sc; /* NB: backpointer */
/* read single */
sc->sc_expbus_tag.bs_r_1 = ata_bs_r_1,
sc->sc_expbus_tag.bs_r_2 = ata_bs_r_2,
/* read multiple */
sc->sc_expbus_tag.bs_rm_2 = ata_bs_rm_2,
sc->sc_expbus_tag.bs_rm_2_s = ata_bs_rm_2_s,
/* write (single) */
sc->sc_expbus_tag.bs_w_1 = ata_bs_w_1,
sc->sc_expbus_tag.bs_w_2 = ata_bs_w_2,
/* write multiple */
sc->sc_expbus_tag.bs_wm_2 = ata_bs_wm_2,
sc->sc_expbus_tag.bs_wm_2_s = ata_bs_wm_2_s,
rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag);
rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag);
rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag);
} else {
/*
* On Cambria use the shared CS3 expansion bus tag
* that handles interlock for sharing access with the
* optional UART's.
*/
rman_set_bustag(&sc->sc_ata, &cambria_exp_bs_tag);
rman_set_bustag(&sc->sc_alt_ata, &cambria_exp_bs_tag);
}
rman_set_bushandle(&sc->sc_ata, sc->sc_ioh);
rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag);
rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh);
ixp425_set_gpio(sa, config->gpin, GPIO_TYPE_EDG_RISING);

183
sys/arm/xscale/ixp425/cambria_exp_space.c
View File

@ -23,8 +23,16 @@
*/
/*
* Hack bus space tag for slow devices on the Cambria expansion bus;
* we slow the timing and add a 2us delay between r/w ops.
* Bus space tag for devices on the Cambria expansion bus.
* This interlocks accesses to allow the optional GPS+RS485 UART's
* to share access with the CF-IDE adapter. Note this does not
* slow the timing UART r/w ops because the lock operation does
* this implicitly for us. Also note we do not DELAY after byte/word
* chip select changes; this doesn't seem necessary (as required
* for IXP425/Avila boards).
*
* XXX should make this generic so all expansion bus devices can
* use it but probably not until we eliminate the ATA hacks
*/
#include <sys/cdefs.h>
@ -32,7 +40,10 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <machine/bus.h>
#include <machine/cpu.h>
@ -43,23 +54,160 @@ __FBSDID("$FreeBSD$");
/* Prototypes for all the bus_space structure functions */
bs_protos(exp);
bs_protos(generic);
bs_protos(generic_armv4);
struct expbus_softc {
struct ixp425_softc *sc; /* bus space tag */
struct mtx lock; /* i/o interlock */
bus_size_t csoff; /* CS offset for 8/16 enable */
};
#define EXP_LOCK_INIT(exp) \
mtx_init(&(exp)->lock, "ExpBus", NULL, MTX_SPIN)
#define EXP_LOCK_DESTROY(exp) \
mtx_destroy(&(exp)->lock)
#define EXP_LOCK(exp) mtx_lock_spin(&(exp)->lock)
#define EXP_UNLOCK(exp) mtx_unlock_spin(&(exp)->lock)
/*
* Enable/disable 16-bit ops on the expansion bus.
*/
static __inline void
enable_16(struct ixp425_softc *sc, bus_size_t cs)
{
EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) &~ EXP_BYTE_EN);
}
static __inline void
disable_16(struct ixp425_softc *sc, bus_size_t cs)
{
EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN);
}
static uint8_t
cambria_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
{
DELAY(2);
return bus_space_read_1((struct bus_space *)t, h, o);
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
uint8_t v;
EXP_LOCK(exp);
v = bus_space_read_1(sc->sc_iot, h, o);
EXP_UNLOCK(exp);
return v;
}
static void
cambria_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
{
DELAY(2);
bus_space_write_1((struct bus_space *)t, h, o, v);
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
bus_space_write_1(sc->sc_iot, h, o, v);
EXP_UNLOCK(exp);
}
/* NB: we only define what's needed by uart */
static uint16_t
cambria_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
{
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
uint16_t v;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
v = bus_space_read_2(sc->sc_iot, h, o);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
return v;
}
static void
cambria_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
{
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
bus_space_write_2(sc->sc_iot, h, o, v);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
static void
cambria_bs_rm_2(void *t, bus_space_handle_t h, bus_size_t o,
u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
bus_space_read_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
static void
cambria_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */
static void
cambria_bs_rm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
uint16_t v;
bus_size_t i;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
#if 1
for (i = 0; i < c; i++) {
v = bus_space_read_2(sc->sc_iot, h, o);
d[i] = bswap16(v);
}
#else
bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c);
#endif
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
static void
cambria_bs_wm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
bus_size_t i;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
#if 1
for (i = 0; i < c; i++)
bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i]));
#else
bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c);
#endif
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
/* NB: we only define what's needed by ata+uart */
struct bus_space cambria_exp_bs_tag = {
/* mapping/unmapping */
.bs_map = generic_bs_map,
@ -70,24 +218,39 @@ struct bus_space cambria_exp_bs_tag = {
/* read (single) */
.bs_r_1 = cambria_bs_r_1,
.bs_r_2 = cambria_bs_r_2,
/* write (single) */
.bs_w_1 = cambria_bs_w_1,
.bs_w_2 = cambria_bs_w_2,
/* read multiple */
.bs_rm_2 = cambria_bs_rm_2,
.bs_rm_2_s = cambria_bs_rm_2_s,
/* write multiple */
.bs_wm_2 = cambria_bs_wm_2,
.bs_wm_2_s = cambria_bs_wm_2_s,
};
void
cambria_exp_bus_init(struct ixp425_softc *sc)
{
static struct expbus_softc c3; /* NB: no need to malloc */
uint32_t cs3;
KASSERT(cpu_is_ixp43x(), ("wrong cpu type"));
cambria_exp_bs_tag.bs_cookie = sc->sc_iot;
c3.sc = sc;
c3.csoff = EXP_TIMING_CS3_OFFSET;
EXP_LOCK_INIT(&c3);
cambria_exp_bs_tag.bs_cookie = &c3;
cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
/* XXX force slowest possible timings and byte mode */
EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) | EXP_BYTE_EN);
cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* XXX force GPIO 3+4 for GPS+RS485 uarts */
ixp425_set_gpio(sc, 3, GPIO_TYPE_EDG_RISING);