o Move the buswide_ctxs bitmap to iommu_unit and rename related functions.
o Rename bus_dma_dmar_load_ident() as well. Reviewed by: kib Sponsored by: DARPA/AFRL Differential Revision: https://reviews.freebsd.org/D25852
This commit is contained in:
parent
c7f893a42b
commit
ea4c01156a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=363650
@ -299,7 +299,7 @@ acpi_iommu_get_dma_tag(device_t dev, device_t child)
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}
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}
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bool
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bool
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bus_dma_dmar_set_buswide(device_t dev)
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bus_dma_iommu_set_buswide(device_t dev)
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{
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{
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struct iommu_unit *unit;
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struct iommu_unit *unit;
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device_t parent;
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device_t parent;
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@ -317,12 +317,12 @@ bus_dma_dmar_set_buswide(device_t dev)
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if (slot != 0 || func != 0) {
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if (slot != 0 || func != 0) {
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if (bootverbose) {
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if (bootverbose) {
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device_printf(dev,
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device_printf(dev,
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"dmar%d pci%d:%d:%d requested buswide busdma\n",
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"iommu%d pci%d:%d:%d requested buswide busdma\n",
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unit->unit, busno, slot, func);
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unit->unit, busno, slot, func);
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}
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}
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return (false);
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return (false);
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}
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}
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dmar_set_buswide_ctx(unit, busno);
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iommu_set_buswide_ctx(unit, busno);
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return (true);
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return (true);
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}
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}
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@ -987,7 +987,7 @@ iommu_fini_busdma(struct iommu_unit *unit)
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}
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}
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int
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int
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bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1,
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bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1,
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vm_paddr_t start, vm_size_t length, int flags)
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vm_paddr_t start, vm_size_t length, int flags)
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{
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{
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struct bus_dma_tag_common *tc;
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struct bus_dma_tag_common *tc;
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@ -34,11 +34,13 @@
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#ifndef _SYS_IOMMU_H_
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#ifndef _SYS_IOMMU_H_
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#define _SYS_IOMMU_H_
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#define _SYS_IOMMU_H_
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#include <sys/types.h>
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#include <sys/queue.h>
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#include <sys/queue.h>
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#include <sys/sysctl.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <sys/taskqueue.h>
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#include <sys/tree.h>
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#include <sys/tree.h>
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#include <sys/types.h>
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#include <dev/pci/pcireg.h>
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/* Host or physical memory address, after translation. */
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/* Host or physical memory address, after translation. */
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typedef uint64_t iommu_haddr_t;
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typedef uint64_t iommu_haddr_t;
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@ -96,6 +98,14 @@ struct iommu_unit {
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struct task dmamap_load_task;
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struct task dmamap_load_task;
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TAILQ_HEAD(, bus_dmamap_iommu) delayed_maps;
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TAILQ_HEAD(, bus_dmamap_iommu) delayed_maps;
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struct taskqueue *delayed_taskqueue;
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struct taskqueue *delayed_taskqueue;
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/*
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* Bitmap of buses for which context must ignore slot:func,
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* duplicating the page table pointer into all context table
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* entries. This is a client-controlled quirk to support some
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* NTBs.
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*/
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uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
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};
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};
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/*
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/*
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@ -811,7 +811,7 @@ intel_ntb_map_pci_bars(struct ntb_softc *ntb)
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device_printf(ntb->device, "Unable to create BAR0 map\n");
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device_printf(ntb->device, "Unable to create BAR0 map\n");
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return (ENOMEM);
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return (ENOMEM);
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}
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}
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if (bus_dma_dmar_load_ident(ntb->bar0_dma_tag, ntb->bar0_dma_map,
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if (bus_dma_iommu_load_ident(ntb->bar0_dma_tag, ntb->bar0_dma_map,
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bar->pbase, bar->size, 0)) {
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bar->pbase, bar->size, 0)) {
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device_printf(ntb->device, "Unable to load BAR0 map\n");
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device_printf(ntb->device, "Unable to load BAR0 map\n");
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return (ENOMEM);
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return (ENOMEM);
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@ -343,7 +343,7 @@ ntb_plx_attach(device_t dev)
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* The device occupies whole bus. In translated TLP slot field
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* The device occupies whole bus. In translated TLP slot field
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* keeps LUT index (original bus/slot), function is passed through.
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* keeps LUT index (original bus/slot), function is passed through.
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*/
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*/
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bus_dma_dmar_set_buswide(dev);
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bus_dma_iommu_set_buswide(dev);
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/* Identify chip port we are connected to. */
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/* Identify chip port we are connected to. */
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val = bus_read_4(sc->conf_res, 0x360);
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val = bus_read_4(sc->conf_res, 0x360);
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@ -192,8 +192,8 @@ _bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
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}
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}
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#ifdef _KERNEL
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#ifdef _KERNEL
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bool bus_dma_dmar_set_buswide(device_t dev);
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bool bus_dma_iommu_set_buswide(device_t dev);
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int bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
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int bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
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vm_paddr_t start, vm_size_t length, int flags);
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vm_paddr_t start, vm_size_t length, int flags);
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#endif
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#endif
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@ -196,7 +196,7 @@ ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move,
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IOMMU_PGF_NOALLOC);
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IOMMU_PGF_NOALLOC);
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}
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}
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if (dmar_is_buswide_ctx(unit, busno)) {
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if (iommu_is_buswide_ctx((struct iommu_unit *)unit, busno)) {
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MPASS(!move);
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MPASS(!move);
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for (i = 0; i <= PCI_BUSMAX; i++) {
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for (i = 0; i <= PCI_BUSMAX; i++) {
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ctx_id_entry_init_one(&ctxp[i], domain, ctx_root);
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ctx_id_entry_init_one(&ctxp[i], domain, ctx_root);
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@ -464,6 +464,7 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid,
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{
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{
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struct dmar_domain *domain, *domain1;
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struct dmar_domain *domain, *domain1;
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struct dmar_ctx *ctx, *ctx1;
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struct dmar_ctx *ctx, *ctx1;
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struct iommu_unit *unit;
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dmar_ctx_entry_t *ctxp;
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dmar_ctx_entry_t *ctxp;
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struct sf_buf *sf;
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struct sf_buf *sf;
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int bus, slot, func, error;
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int bus, slot, func, error;
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@ -480,9 +481,10 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid,
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}
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}
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enable = false;
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enable = false;
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TD_PREP_PINNED_ASSERT;
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TD_PREP_PINNED_ASSERT;
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unit = (struct iommu_unit *)dmar;
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DMAR_LOCK(dmar);
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DMAR_LOCK(dmar);
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KASSERT(!dmar_is_buswide_ctx(dmar, bus) || (slot == 0 && func == 0),
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KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0),
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("dmar%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus,
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("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus,
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slot, func));
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slot, func));
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ctx = dmar_find_ctx_locked(dmar, rid);
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ctx = dmar_find_ctx_locked(dmar, rid);
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error = 0;
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error = 0;
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@ -167,15 +167,6 @@ struct dmar_unit {
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struct iommu_map_entries_tailq tlb_flush_entries;
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struct iommu_map_entries_tailq tlb_flush_entries;
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struct task qi_task;
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struct task qi_task;
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struct taskqueue *qi_taskqueue;
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struct taskqueue *qi_taskqueue;
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/*
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* Bitmap of buses for which context must ignore slot:func,
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* duplicating the page table pointer into all context table
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* entries. This is a client-controlled quirk to support some
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* NTBs.
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*/
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uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
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};
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};
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#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock)
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#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock)
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@ -290,8 +281,8 @@ void dmar_quirks_pre_use(struct iommu_unit *dmar);
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int dmar_init_irt(struct dmar_unit *unit);
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int dmar_init_irt(struct dmar_unit *unit);
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void dmar_fini_irt(struct dmar_unit *unit);
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void dmar_fini_irt(struct dmar_unit *unit);
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void dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno);
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void iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno);
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bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno);
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bool iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno);
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extern iommu_haddr_t dmar_high;
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extern iommu_haddr_t dmar_high;
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extern int haw;
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extern int haw;
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@ -593,21 +593,18 @@ DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
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MODULE_DEPEND(dmar, acpi, 1, 1, 1);
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MODULE_DEPEND(dmar, acpi, 1, 1, 1);
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void
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void
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dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
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iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
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{
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{
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struct dmar_unit *dmar;
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dmar = (struct dmar_unit *)unit;
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MPASS(busno <= PCI_BUSMAX);
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MPASS(busno <= PCI_BUSMAX);
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DMAR_LOCK(dmar);
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IOMMU_LOCK(unit);
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dmar->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
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unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
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1 << (busno % (NBBY * sizeof(uint32_t)));
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1 << (busno % (NBBY * sizeof(uint32_t)));
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DMAR_UNLOCK(dmar);
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IOMMU_UNLOCK(unit);
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}
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}
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bool
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bool
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dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)
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iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno)
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{
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{
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MPASS(busno <= PCI_BUSMAX);
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MPASS(busno <= PCI_BUSMAX);
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@ -301,13 +301,13 @@ bus_dma_tag_destroy(bus_dma_tag_t dmat)
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#ifndef ACPI_DMAR
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#ifndef ACPI_DMAR
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bool
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bool
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bus_dma_dmar_set_buswide(device_t dev)
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bus_dma_iommu_set_buswide(device_t dev)
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{
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{
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return (false);
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return (false);
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}
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}
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int
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int
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bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
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bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
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vm_paddr_t start, vm_size_t length, int flags)
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vm_paddr_t start, vm_size_t length, int flags)
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{
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{
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return (0);
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return (0);
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