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Ok With this commit we actually get through

Browse Source 
the mi_startup (or to the last of it).. and
hit a panic after :

uart0: <16550 or compatible> on iodi0
Trap cause = 2 (TLB miss....)

I did have to take the pci bus OUT of the
build to get this far, hit a cache error with
the PCI code in. Interesting thing is the machine
reboots too ;-)
This commit is contained in:
Randall Stewart 2009-11-06 12:52:51 +00:00
parent 6450bdc708
commit eac3c4cd27
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/mips/; revision=198985
5 changed files with 6 additions and 51 deletions
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1
sys/mips/conf/XLR
View File

@ -61,6 +61,7 @@ makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
#profile 2
#options SCHED_ULE # ULE scheduler
options VERBOSE_SYSINIT
options SCHED_4BSD # 4BSD scheduler
#options PREEMPTION # Enable kernel thread preemption
#options FULL_PREEMPTION # Enable kernel thread preemption

1
sys/mips/rmi/bus_space_rmi.c
View File

@ -42,7 +42,6 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h>
#include <machine/cache.h>
void xlr_putc(char);
void xlr_print_int(uint32_t);
static int

2
sys/mips/rmi/clock.c
View File

@ -179,6 +179,7 @@ rmi_early_counter_init()
pic_update_control(1 << (8 + 6));
}
void tick_init(void);
void
platform_initclocks(void)
@ -246,6 +247,7 @@ platform_initclocks(void)
/* Setup count-compare interrupt for vcpu[1-31] */
mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);
}
tick_init();
}
unsigned

4
sys/mips/rmi/files.xlr
View File

@ -14,8 +14,8 @@ mips/rmi/uart_bus_xlr_iodi.c optional uart
mips/rmi/uart_cpu_mips_xlr.c optional uart
mips/rmi/perfmon_kern.c optional xlr_perfmon
mips/rmi/perfmon_percpu.c optional xlr_perfmon
mips/rmi/pcibus.c optional pci
mips/rmi/xlr_pci.c optional pci
#mips/rmi/pcibus.c optional pci
#mips/rmi/xlr_pci.c optional pci
#mips/rmi/xls_ehci.c optional usb ehci
dev/rmi/xlr/rge.c optional rge
mips/rmi/bus_space_rmi.c standard

49
sys/mips/rmi/xlr_machdep.c
View File

@ -368,48 +368,6 @@ mips_init(void)
#endif
}
void (*xlr_putchar)(char)=NULL;
static void
xlr_putc_init(void)
{
uint32_t addr;
addr = (uint32_t)(xlr_boot1_info.uart_putchar & 0x00000000ffffffff);
xlr_putchar = (void (*)(char))(addr);
}
void xlr_putc(char);
void xlr_print_int(uint32_t val);
void
xlr_putc(char c)
{
(*xlr_putchar)(c);
DELAY(1000);
}
void
xlr_print_int(uint32_t val)
{
int i;
int idx;
char ary[16] = {
'0', '1', '2', '3',
'4', '5', '6', '7',
'8', '9', 'a', 'b',
'c', 'd', 'e', 'f'
};
xlr_putc('0');
xlr_putc('x');
for(i=7;i>=0;i--) {
idx = (val >> (i*4)) & 0x0000000f;
xlr_putc(ary[idx]);
}
xlr_putc(' ');
xlr_putc(015);
xlr_putc(012);
}
void tick_init(void);
void
platform_start(__register_t a0 __unused,
__register_t a1 __unused,
@ -454,7 +412,6 @@ platform_start(__register_t a0 __unused,
mips_timer_early_init(platform_get_frequency());
/* Init the time counter in the PIC and local putc routine*/
xlr_putc_init();
rmi_early_counter_init();
/* Init console please */
@ -526,7 +483,6 @@ platform_start(__register_t a0 __unused,
/* Set up hz, among others. */
mips_init();
pcpup = (struct pcpu *)NULL; /* TODO To be removed */
#ifdef SMP
/*
@ -583,13 +539,10 @@ platform_start(__register_t a0 __unused,
* mips_init() XXX NOTE: We may need to move this to SMP based init
* code for each CPU, later.
*/
printf("Here\n");
rmi_spin_mutex_safe = 1;
on_chip_init();
printf("there\n");
mips_timer_init_params(platform_get_frequency(), 0);
printf("ok\n");
tick_init();
printf("Platform specific startup now completes\n");
}
void