Version 0.9.5.17:

o change os glue API to be compatible with Linux so hal.o's can
  be used on any system
o add ABI version to catch driver-HAL mismatches
o move hal version information from ah_osdep.c to binary component
o remove ath_hal_wait os glue component
o assign constant values to all enums to avoid potential compiler
  incompatibilities
o add support for 3Com badged cards (PCI vendor ID)
o add support for IBM mini-pci cards (PCI device ID)
o expose MAC, PHY, and radio hardware revisions
o support for big-endian platforms
o new method to set slot time in us
o bug fix for 5211: beacon timers not setup correctly
o bug fix for 5212: don't crash when handed a 5112 radio

sys/contrib/dev/ath/ah.h

@@ -33,7 +33,7 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGES.
  *
- * $Id: ah.h,v 1.35 2003/07/21 02:36:53 sam Exp $
+ * $Id: ah.h,v 1.41 2003/11/01 01:05:45 sam Exp $
  */
 
 #ifndef _ATH_AH_H_
@@ -55,21 +55,21 @@
  */
 typedef enum {
 	HAL_OK		= 0,	/* No error */
-	HAL_ENXIO,		/* No hardware present */
-	HAL_ENOMEM,		/* Memory allocation failed */
-	HAL_EIO,		/* Hardware didn't respond as expected */
-	HAL_EEMAGIC,		/* EEPROM magic number invalid */
-	HAL_EEVERSION,		/* EEPROM version invalid */
-	HAL_EELOCKED,		/* EEPROM unreadable */
-	HAL_EEBADSUM,		/* EEPROM checksum invalid */
-	HAL_EEREAD,		/* EEPROM read problem */
-	HAL_EEBADMAC,		/* EEPROM mac address invalid */
-	HAL_EESIZE,		/* EEPROM size not supported */
-	HAL_EEWRITE,		/* Attempt to change write-locked EEPROM */
-	HAL_EINVAL,		/* Invalid parameter to function */
-	HAL_ENOTSUPP,		/* Hardware revision not supported */
-	HAL_ESELFTEST,		/* Hardware self-test failed */
-	HAL_EINPROGRESS,	/* Operation incomplete */
+	HAL_ENXIO	= 1,	/* No hardware present */
+	HAL_ENOMEM	= 2,	/* Memory allocation failed */
+	HAL_EIO		= 3,	/* Hardware didn't respond as expected */
+	HAL_EEMAGIC	= 4,	/* EEPROM magic number invalid */
+	HAL_EEVERSION	= 5,	/* EEPROM version invalid */
+	HAL_EELOCKED	= 6,	/* EEPROM unreadable */
+	HAL_EEBADSUM	= 7,	/* EEPROM checksum invalid */
+	HAL_EEREAD	= 8,	/* EEPROM read problem */
+	HAL_EEBADMAC	= 9,	/* EEPROM mac address invalid */
+	HAL_EESIZE	= 10,	/* EEPROM size not supported */
+	HAL_EEWRITE	= 11,	/* Attempt to change write-locked EEPROM */
+	HAL_EINVAL	= 12,	/* Invalid parameter to function */
+	HAL_ENOTSUPP	= 13,	/* Hardware revision not supported */
+	HAL_ESELFTEST	= 14,	/* Hardware self-test failed */
+	HAL_EINPROGRESS	= 15,	/* Operation incomplete */
 } HAL_STATUS;
 
 typedef enum {
@@ -99,10 +99,10 @@ typedef enum {
  */
 typedef enum {
 	HAL_TX_QUEUE_INACTIVE	= 0,		/* queue is inactive/unused */
-	HAL_TX_QUEUE_DATA,			/* data xmit q's */
-	HAL_TX_QUEUE_BEACON,			/* beacon xmit q */
-	HAL_TX_QUEUE_CAB,			/* "crap after beacon" xmit q */
-	HAL_TX_QUEUE_PSPOLL,			/* power-save poll xmit q */
+	HAL_TX_QUEUE_DATA	= 1,		/* data xmit q's */
+	HAL_TX_QUEUE_BEACON	= 2,		/* beacon xmit q */
+	HAL_TX_QUEUE_CAB	= 3,		/* "crap after beacon" xmit q */
+	HAL_TX_QUEUE_PSPOLL	= 4,		/* power-save poll xmit q */
 } HAL_TX_QUEUE;
 
 #define	HAL_NUM_TX_QUEUES	10		/* max possible # of queues */
@@ -189,9 +189,9 @@ typedef enum {
 } HAL_INT;
 
 typedef enum {
-	HAL_RFGAIN_INACTIVE,
-	HAL_RFGAIN_READ_REQUESTED,
-	HAL_RFGAIN_NEED_CHANGE
+	HAL_RFGAIN_INACTIVE		= 0,
+	HAL_RFGAIN_READ_REQUESTED	= 1,
+	HAL_RFGAIN_NEED_CHANGE		= 2
 } HAL_RFGAIN;
 
 /*
@@ -278,9 +278,9 @@ typedef struct {
 } HAL_RATE_SET;
 
 typedef enum {
-	HAL_ANT_VARIABLE,			/* variable by programming */
-	HAL_ANT_FIXED_A,			/* fixed to 11a frequencies */
-	HAL_ANT_FIXED_B,			/* fixed to 11b frequencies */
+	HAL_ANT_VARIABLE = 0,			/* variable by programming */
+	HAL_ANT_FIXED_A	 = 1,			/* fixed to 11a frequencies */
+	HAL_ANT_FIXED_B	 = 2,			/* fixed to 11b frequencies */
 } HAL_ANT_SETTING;
 
 typedef enum {
@@ -296,11 +296,16 @@ typedef struct {
 } HAL_KEYVAL;
 
 typedef enum {
-	HAL_CIPHER_WEP,
-	HAL_CIPHER_AES_CCM,
-	HAL_CIPHER_CKIP
+	HAL_CIPHER_WEP		= 0,
+	HAL_CIPHER_AES_CCM	= 1,
+	HAL_CIPHER_CKIP		= 2
 } HAL_CIPHER;
 
+enum {
+	HAL_SLOT_TIME_9	 = 9,
+	HAL_SLOT_TIME_20 = 20,
+};
+
 /*
  * Per-station beacon timer state.
  */
@@ -325,10 +330,14 @@ struct ath_desc;
  * Clients of the HAL call ath_hal_attach to obtain a reference to an
  * ath_hal structure for use with the device.  Hardware-related operations
  * that follow must call back into the HAL through interface, supplying
- * the reference as the first parameter.
+ * the reference as the first parameter.  Note that before using the
+ * reference returned by ath_hal_attach the caller should verify the
+ * ABI version number.
  */
 struct ath_hal {
 	u_int32_t	ah_magic;	/* consistency check magic number */
+	u_int32_t	ah_abi;		/* HAL ABI version */
+#define	HAL_ABI_VERSION	0x03103100	/* YYMMDDnn */
 	u_int16_t	ah_devid;	/* PCI device ID */
 	u_int16_t	ah_subvendorid;	/* PCI subvendor ID */
 	HAL_SOFTC	ah_sc;		/* back pointer to driver/os state */
@@ -336,6 +345,12 @@ struct ath_hal {
 	HAL_BUS_HANDLE	ah_sh;
 	HAL_CTRY_CODE	ah_countryCode;
 
+	u_int32_t	ah_macVersion;	/* MAC version id */
+	u_int16_t	ah_macRev;	/* MAC revision */
+	u_int16_t	ah_phyRev;	/* PHY revision */
+	u_int16_t	ah_analog5GhzRev;/* 2GHz radio revision */
+	u_int16_t	ah_analog2GhzRev;/* 5GHz radio revision */
+
 	const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *, u_int mode);
 	void		(*ah_detach)(struct ath_hal*);
 
@@ -424,6 +439,7 @@ struct ath_hal {
 	u_int32_t	(*ah_getDefAntenna)(struct ath_hal*);
 	void		(*ah_setDefAntenna)(struct ath_hal*, u_int32_t antenna);
 #endif
+	HAL_BOOL	(*ah_setSlotTime)(struct ath_hal*, u_int);
 
 	/* Key Cache Functions */
 	u_int32_t	(*ah_getKeyCacheSize)(struct ath_hal*);
@@ -524,4 +540,9 @@ extern u_int16_t ath_hal_computetxtime(struct ath_hal *,
  */
 extern	u_int ath_hal_mhz2ieee(u_int mhz, u_int flags);
 extern	u_int ath_hal_ieee2mhz(u_int ieee, u_int flags);
+
+/*
+ * Return a version string for the HAL release.
+ */
+extern	char ath_hal_version[];
 #endif /* _ATH_AH_H_ */

sys/contrib/dev/ath/ah_devid.h

@@ -33,13 +33,19 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGES.
  *
- * $Id: ah_devid.h,v 1.6 2003/06/25 04:50:22 sam Exp $
+ * $Id: ah_devid.h,v 1.7 2003/10/22 21:17:40 sam Exp $
  */
 
 #ifndef _DEV_ATH_DEVID_H_
 #define _DEV_ATH_DEVID_H_
 
 #define ATHEROS_VENDOR_ID	0x168c		/* Atheros PCI vendor ID */
+/*
+ * NB: all Atheros-based devices should have a PCI vendor ID
+ *     of 0x168c, but some vendors, in their infinite wisdom
+ *     do not follow this so we must handle them specially.
+ */
+#define	ATHEROS_3COM_VENDOR_ID	0xa727		/* 3Com PCI vendor ID */
 
 /* AR5210 (for reference) */
 #define AR5210_DEFAULT          0x1107          /* No eeprom HW default */
@@ -57,6 +63,7 @@
 #define AR5212_DEFAULT          0x1113          /* No eeprom HW default */
 #define AR5212_DEVID            0x0013          /* Final ar5212 devid */
 #define AR5212_FPGA             0xf013          /* Emulation board */
+#define	AR5212_DEVID_IBM	0x1014          /* IBM minipci ID */
 
 #define	AR_SUBVENDOR_ID_NOG	0x0e11		/* No 11G subvendor ID */
 #endif /* _DEV_ATH_DEVID_H */

sys/contrib/dev/ath/freebsd/ah_osdep.c

@@ -33,7 +33,7 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGES.
  *
- * $Id: ah_osdep.c,v 1.22 2003/07/26 14:58:00 sam Exp $
+ * $Id: ah_osdep.c,v 1.28 2003/11/01 01:43:21 sam Exp $
  */
 #include "opt_ah.h"
 
@@ -51,10 +51,6 @@
 
 #include <contrib/dev/ath/ah.h>
 
-#define	AH_TIMEOUT	1000
-
-extern	HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
-		u_int32_t mask, u_int32_t val);
 extern	void ath_hal_printf(struct ath_hal *, const char*, ...)
 		__printflike(2,3);
 extern	void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
@@ -81,8 +77,6 @@ SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
 	    0, "Atheros HAL debugging printfs");
 #endif /* AH_DEBUG */
 
-#include "version.h"
-static char ath_hal_version[] = ATH_HAL_VERSION;
 SYSCTL_STRING(_hw_ath_hal, OID_AUTO, version, CTLFLAG_RD, ath_hal_version, 0,
 	"Atheros HAL version");
 
@@ -99,25 +93,6 @@ SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
 	   &ath_hal_additional_swba_backoff, 0,
 	   "Atheros HAL additional SWBA backoff time");
 
-/*
- * Poll the register looking for a specific value.
- */
-HAL_BOOL
-ath_hal_wait(struct ath_hal *ah, u_int reg, u_int32_t mask, u_int32_t val)
-{
-	int i;
-
-	for (i = 0; i < AH_TIMEOUT; i++) {
-		if ((OS_REG_READ(ah, reg) & mask) == val)
-			return AH_TRUE;
-		DELAY(10);
-	}
-	ath_hal_printf(ah, "ath_hal_wait: timeout on reg 0x%x: "
-		"0x%08x & 0x%08x != 0x%08x\n", reg, OS_REG_READ(ah, reg),
-		 mask, val);
-	return AH_FALSE;
-}
-
 void*
 ath_hal_malloc(size_t size)
 {
@@ -269,7 +244,7 @@ ath_hal_alq_get(struct ath_hal *ah)
 }
 
 void
-OS_REG_WRITE(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
+ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
 {
 	if (ath_hal_alq) {
 		struct ale *ale = ath_hal_alq_get(ah);
@@ -281,15 +256,24 @@ OS_REG_WRITE(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
 			alq_post(ath_hal_alq, ale);
 		}
 	}
+#if _BYTE_ORDER == _BIG_ENDIAN
+	if (reg >= 0x4000 && reg < 0x5000)
+		bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val));
+	else
+#endif
 		bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val);
 }
 
 u_int32_t
-OS_REG_READ(struct ath_hal *ah, u_int32_t reg)
+ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
 {
 	u_int32_t val;
 
 	val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg);
+#if _BYTE_ORDER == _BIG_ENDIAN
+	if (reg >= 0x4000 && reg < 0x5000)
+		val = le32toh(val);
+#endif
 	if (ath_hal_alq) {
 		struct ale *ale = ath_hal_alq_get(ah);
 		if (ale) {
@@ -317,7 +301,42 @@ OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
 		}
 	}
 }
-#endif /* AH_DEBUG_ALQ */
+#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
+/*
+ * Memory-mapped device register read/write.  These are here
+ * as routines when debugging support is enabled and/or when
+ * explicitly configured to use function calls.  The latter is
+ * for architectures that might need to do something before
+ * referencing memory (e.g. remap an i/o window).
+ *
+ * NB: see the comments in ah_osdep.h about byte-swapping register
+ *     reads and writes to understand what's going on below.
+ */
+
+void
+ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
+{
+#if _BYTE_ORDER == _BIG_ENDIAN
+	if (reg >= 0x4000 && reg < 0x5000)
+		bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val));
+	else
+#endif
+		bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val);
+}
+
+u_int32_t
+ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
+{
+	u_int32_t val;
+
+	val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg);
+#if _BYTE_ORDER == _BIG_ENDIAN
+	if (reg >= 0x4000 && reg < 0x5000)
+		val = le32toh(val);
+#endif
+	return val;
+}
+#endif /* AH_DEBUG || AH_REGOPS_FUNC */
 
 #ifdef AH_ASSERT
 void
@@ -329,8 +348,17 @@ ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
 }
 #endif /* AH_ASSERT */
 
+/*
+ * Delay n microseconds.
+ */
+void
+ath_hal_delay(int n)
+{
+	DELAY(n);
+}
+
 u_int32_t
-OS_GETUPTIME(struct ath_hal *ah)
+ath_hal_getuptime(struct ath_hal *ah)
 {
 	struct bintime bt;
 	getbinuptime(&bt);
@@ -364,4 +392,3 @@ static moduledata_t ath_hal_mod = {
 };
 DECLARE_MODULE(ath_hal, ath_hal_mod, SI_SUB_DRIVERS, SI_ORDER_ANY);
 MODULE_VERSION(ath_hal, 1);
-MODULE_DEPEND(ath_hal, wlan, 1,1,1);

sys/contrib/dev/ath/freebsd/ah_osdep.h

@@ -33,7 +33,7 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGES.
  *
- * $Id: ah_osdep.h,v 1.9 2003/07/26 14:55:11 sam Exp $
+ * $Id: ah_osdep.h,v 1.10 2003/11/01 01:21:31 sam Exp $
  */
 #ifndef _ATH_AH_OSDEP_H_
 #define _ATH_AH_OSDEP_H_
@@ -42,6 +42,7 @@
  */
 #include <sys/param.h>
 #include <sys/systm.h>
+#include <sys/endian.h>
 
 #include <machine/bus.h>
 
@@ -50,7 +51,12 @@ typedef bus_space_tag_t HAL_BUS_TAG;
 typedef bus_space_handle_t HAL_BUS_HANDLE;
 typedef bus_addr_t HAL_BUS_ADDR;
 
-#define	OS_DELAY(_n)	DELAY(_n)
+/*
+ * Delay n microseconds.
+ */
+extern	void ath_hal_delay(int);
+#define	OS_DELAY(_n)	ath_hal_delay(_n)
+
 #define	OS_INLINE	__inline
 #define	OS_MEMZERO(_a, _size)		bzero((_a), (_size))
 #define	OS_MEMCPY(_dst, _src, _size)	bcopy((_src), (_dst), (_size))
@@ -58,17 +64,61 @@ typedef bus_addr_t HAL_BUS_ADDR;
 	(bcmp((_a), (_b), IEEE80211_ADDR_LEN) == 0)
 
 struct ath_hal;
-extern 	u_int32_t OS_GETUPTIME(struct ath_hal *);
+extern	u_int32_t ath_hal_getuptime(struct ath_hal *);
+#define	OS_GETUPTIME(_ah)	ath_hal_getuptime(_ah)
 
-#ifdef AH_DEBUG_ALQ
-extern	void OS_REG_WRITE(struct ath_hal *, u_int32_t, u_int32_t);
-extern	u_int32_t OS_REG_READ(struct ath_hal *, u_int32_t);
-extern	void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
+/*
+ * Register read/write; we assume the registers will always
+ * be memory-mapped.  Note that register accesses are done
+ * using target-specific functions when debugging is enabled
+ * (AH_DEBUG) or we are explicitly configured this way.  The
+ * latter is used on some platforms where the full i/o space
+ * cannot be directly mapped.
+ */
+#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
+#define	OS_REG_WRITE(_ah, _reg, _val)	ath_hal_reg_write(_ah, _reg, _val)
+#define	OS_REG_READ(_ah, _reg)		ath_hal_reg_read(_ah, _reg)
+
+extern	void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
+extern	u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
 #else
+/*
+ * The hardware registers are native little-endian byte order.
+ * Big-endian hosts are handled by enabling hardware byte-swap
+ * of register reads and writes at reset.  But the PCI clock
+ * domain registers are not byte swapped!  Thus, on big-endian
+ * platforms we have to byte-swap thoese registers specifically.
+ * Most of this code is collapsed at compile time because the
+ * register values are constants.
+ */
+#define	AH_LITTLE_ENDIAN	1234
+#define	AH_BIG_ENDIAN		4321
+
+#if _BYTE_ORDER == _BIG_ENDIAN
+#define OS_REG_WRITE(_ah, _reg, _val) do {				\
+	if ( (_reg) >= 0x4000 && (_reg) < 0x5000)			\
+		bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh,		\
+			(_reg), htole32(_val));			\
+	else								\
+		bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh,		\
+			(_reg), (_val));				\
+} while (0)
+#define OS_REG_READ(_ah, _reg)						\
+	(((_reg) >= 0x4000 && (_reg) < 0x5000) ?			\
+		le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh,	\
+			(_reg))) :					\
+		bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
+#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
 #define	OS_REG_WRITE(_ah, _reg, _val)					\
 	bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
 #define	OS_REG_READ(_ah, _reg)						\
 	((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
+#endif /* _BYTE_ORDER */
+#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
+
+#ifdef AH_DEBUG_ALQ
+extern	void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
+#else
 #define	OS_MARK(_ah, _id, _v)
 #endif
 

sys/contrib/dev/ath/version.h

@@ -33,6 +33,6 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGES.
  *
- * $Id: version.h,v 1.8 2003/08/01 03:11:38 sam Exp $
+ * $Id: version.h,v 1.22 2003/11/01 01:43:21 sam Exp $
  */
-#define	ATH_HAL_VERSION	"0.9.5.2"
+#define	ATH_HAL_VERSION	"0.9.5.17"