From eb27b1567e62ede82694c1d27bc95ecf81210c1f Mon Sep 17 00:00:00 2001
From: Alan Cox <alc@FreeBSD.org>
Date: Tue, 11 May 1999 01:54:52 +0000
Subject: [PATCH] The Intel Pentium Pro's performance counters are 40 bits
 wide.  The Intel manuals specifically say that reading the counters using the
 rdmsr instruction returns a 64 bit value of which the higher 24 bits are
 undefined. The code that reads the counters should then clear the high 24
 bits.

PR:		 i386/10632
---
 sys/i386/i386/perfmon.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sys/i386/i386/perfmon.c b/sys/i386/i386/perfmon.c
index 0720c62ea0f2..8becfbc92409 100644
--- a/sys/i386/i386/perfmon.c
+++ b/sys/i386/i386/perfmon.c
@@ -26,7 +26,7 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: perfmon.c,v 1.16 1998/12/07 21:58:18 archie Exp $
+ *	$Id: perfmon.c,v 1.17 1999/01/12 00:19:32 eivind Exp $
  */
 
 #include <sys/param.h>
@@ -160,7 +160,7 @@ perfmon_stop(int pmc)
 
 	if (perfmon_inuse & (1 << pmc)) {
 		disable_intr();
-		pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]);
+		pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
 		ctl_shadow[pmc] &= ~(PMCF_EN << 16);
 		writectl(pmc);
 		enable_intr();
@@ -177,7 +177,7 @@ perfmon_read(int pmc, quad_t *val)
 
 	if (perfmon_inuse & (1 << pmc)) {
 		if (ctl_shadow[pmc] & (PMCF_EN << 16))
-			*val = rdmsr(msr_pmc[pmc]);
+			*val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
 		else
 			*val = pmc_shadow[pmc];
 		return 0;