- Cleanup i8251 related defines.
- Move i8255 related defines into a separate file.
This commit is contained in:
parent
0f52b1c477
commit
ebd2b74476
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=182835
@ -32,13 +32,25 @@
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/*
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* modified for PC9801 by M.Ishii
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* Kyoto University Microcomputer Club (KMC)
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*/
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/*
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*
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* modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
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*/
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/* define command and status code */
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/* i8251 mode register */
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#define MOD8251_5BITS 0x00
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#define MOD8251_6BITS 0x04
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#define MOD8251_7BITS 0x08
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#define MOD8251_8BITS 0x0c
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#define MOD8251_PENAB 0x10 /* parity enable */
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#define MOD8251_PEVEN 0x20 /* parity even */
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#define MOD8251_STOP1 0x40 /* 1 stop bit */
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#define MOD8251_STOP15 0x80 /* 1.5 stop bit */
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#define MOD8251_STOP2 0xc0 /* 2 stop bit */
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#define MOD8251_CLKx1 0x01 /* x1 */
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#define MOD8251_CLKx16 0x02 /* x16 */
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#define MOD8251_CLKx64 0x03 /* x64 */
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/* i8251 command register */
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#define CMD8251_TxEN 0x01 /* transmit enable */
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#define CMD8251_DTR 0x02 /* assert DTR */
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#define CMD8251_RxEN 0x04 /* receive enable */
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@ -46,59 +58,54 @@
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#define CMD8251_ER 0x10 /* error reset */
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#define CMD8251_RTS 0x20 /* assert RTS */
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#define CMD8251_RESET 0x40 /* internal reset */
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#define CMD8251_EH 0x80 /* enter hunt mode (only synchronous mode)*/
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#define CMD8251_EH 0x80 /* enter hunt mode */
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/* i8251 status register */
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#define STS8251_TxRDY 0x01 /* transmit READY */
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#define STS8251_RxRDY 0x02 /* data exists in receive buffer */
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#define STS8251_TxEMP 0x04 /* transmit buffer EMPTY */
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#define STS8251_PE 0x08 /* perity error */
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#define STS8251_OE 0x10 /* overrun error */
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#define STS8251_FE 0x20 /* framing error */
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#define STS8251_BD_SD 0x40 /* break detect (async) / sync detect (sync) */
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#define STS8251_BI 0x40 /* break detect */
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#define STS8251_DSR 0x80 /* DSR is asserted */
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#define STS8251F_TxEMP 0x01 /* transmit buffer EMPTY */
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#define STS8251F_TxRDY 0x02 /* transmit READY */
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#define STS8251F_RxRDY 0x04 /* data exists in receive buffer */
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#define STS8251F_OE 0x10 /* overrun error */
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#define STS8251F_PE 0x20 /* perity error */
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#define STS8251F_BD_SD 0x80 /* break detect (async) / sync detect (sync) */
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/* i8251F line status register */
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#define FLSR_TxEMP 0x01 /* transmit buffer EMPTY */
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#define FLSR_TxRDY 0x02 /* transmit READY */
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#define FLSR_RxRDY 0x04 /* data exists in receive buffer */
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#define FLSR_OE 0x10 /* overrun error */
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#define FLSR_PE 0x20 /* perity error */
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#define FLSR_BI 0x80 /* break detect */
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#define INTR8251F_DTCT 0x60 /* FIFO detection mask */
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#define INTR8251F_INTRV 0x0e /* interrupt event */
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#define INTR8251F_TO 0x0c /* receive timeout */
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#define INTR8251F_LSTS 0x06 /* line status */
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#define INTR8251F_RxRDY 0x04 /* receive READY */
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#define INTR8251F_TxRDY 0x02 /* transmit READY */
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#define INTR8251F_ISEV 0x01 /* event occured */
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#define INTR8251F_MSTS 0x00 /* modem status */
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/* i8251F modem status register */
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#define MSR_DCD 0x80 /* Current Data Carrier Detect */
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#define MSR_RI 0x40 /* Current Ring Indicator */
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#define MSR_DSR 0x20 /* Current Data Set Ready */
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#define MSR_CTS 0x10 /* Current Clear to Send */
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#define MSR_DDCD 0x08 /* DCD has changed state */
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#define MSR_TERI 0x04 /* RI has toggled low to high */
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#define MSR_DDSR 0x02 /* DSR has changed state */
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#define MSR_DCTS 0x01 /* CTS has changed state */
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#define CTRL8251F_ENABLE 0x01 /* enable FIFO */
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#define CTRL8251F_RCV_RST 0x02 /* reset receive FIFO */
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#define CTRL8251F_XMT_RST 0x04 /* reset transmit FIFO */
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/* i8251F interrupt identification register */
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#define IIR_FIFO_CK1 0x40
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#define IIR_FIFO_CK2 0x20
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#define IIR_IMASK 0x0f
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#define IIR_RXTOUT 0x0c /* Receiver timeout */
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#define IIR_RLS 0x06 /* Line status change */
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#define IIR_RXRDY 0x04 /* Receiver ready */
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#define IIR_TXRDY 0x02 /* Transmitter ready */
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#define IIR_NOPEND 0x01 /* Transmitter ready */
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#define IIR_MLSC 0x00 /* Modem status */
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#define MOD8251_5BITS 0x00
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#define MOD8251_6BITS 0x04
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#define MOD8251_7BITS 0x08
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#define MOD8251_8BITS 0x0c
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#define MOD8251_PDISAB 0x00 /* parity disable */
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#define MOD8251_PODD 0x10 /* parity odd */
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#define MOD8251_PEVEN 0x30 /* parity even */
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#define MOD8251_STOP1 0x40 /* stop bit len = 1bit */
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#define MOD8251_STOP2 0xc0 /* stop bit len = 2bit */
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#define MOD8251_CLKX16 0x02 /* x16 */
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#define MOD8251_CLKX1 0x01 /* x1 */
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#define CICSCD_CD 0x20 /* CD */
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#define CICSCD_CS 0x40 /* CS */
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#define CICSCD_CI 0x80 /* CI */
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#define CICSCDF_CS 0x10 /* CS */
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#define CICSCDF_DR 0x20 /* DR */
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#define CICSCDF_CI 0x40 /* CI */
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#define CICSCDF_CD 0x80 /* CD */
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/* interrupt mask control */
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#define IEN_Rx 0x01
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#define IEN_TxEMP 0x02
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#define IEN_Tx 0x04
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/* i8251F fifo control register */
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#define FIFO_ENABLE 0x01 /* Turn the FIFO on */
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#define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
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#define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
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#define FIFO_LSR_EN 0x08
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#define FIFO_MSR_EN 0x10
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#define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
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#define FIFO_TRIGGER_4 0x40 /* ibid 4 */
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#define FIFO_TRIGGER_8 0x80 /* ibid 8 */
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#define FIFO_TRIGGER_14 0xc0 /* ibid 14 */
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46
sys/dev/ic/i8255.h
Normal file
46
sys/dev/ic/i8255.h
Normal file
@ -0,0 +1,46 @@
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/*-
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* Copyright (c) 2008 TAKAHASHI Yoshihiro
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_IC_I8255_H_
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#define _DEV_IC_I8255_H_
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/*
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* modem status via SYSTM_PORTB
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*/
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#define CICSCD_CD 0x20 /* CD */
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#define CICSCD_CS 0x40 /* CS */
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#define CICSCD_CI 0x80 /* CI */
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/*
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* control intrline via SYSTM_PORTC
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*/
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#define IEN_Rx 0x01
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#define IEN_TxEMP 0x02
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#define IEN_Tx 0x04
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#endif /* _DEV_IC_I8255_H_ */
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@ -121,6 +121,7 @@
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#include <dev/ic/ns16550.h>
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#ifdef PC98
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#include <dev/ic/i8251.h>
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#include <dev/ic/i8255.h>
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#include <dev/ic/rsa.h>
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#endif
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@ -1784,8 +1785,8 @@ comopen(struct tty *tp, struct cdev *dev)
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pc98_msrint_start(dev);
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if (com->pc98_8251fifo) {
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com->pc98_8251fifo_enable = 1;
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outb(I8251F_fcr, CTRL8251F_ENABLE |
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CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
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outb(I8251F_fcr,
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FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
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}
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}
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#endif
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@ -1803,8 +1804,7 @@ comopen(struct tty *tp, struct cdev *dev)
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*/
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for (i = 0; i < 500; i++) {
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sio_setreg(com, com_fifo,
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FIFO_RCV_RST | FIFO_XMT_RST
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| com->fifo_image);
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FIFO_RCV_RST | FIFO_XMT_RST | com->fifo_image);
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#ifdef PC98
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if (com->pc98_if_type == COM_IF_RSA98III)
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outb(com->rsabase + rsa_frr , 0x00);
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@ -1955,7 +1955,7 @@ comclose(tp)
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#ifdef PC98
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if (com->pc98_8251fifo) {
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if (com->pc98_8251fifo_enable)
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outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
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outb(I8251F_fcr, FIFO_XMT_RST | FIFO_RCV_RST);
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com->pc98_8251fifo_enable = 0;
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}
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#endif
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@ -1997,8 +1997,8 @@ siobusycheck(chan)
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#ifdef PC98
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else if ((IS_8251(com->pc98_if_type) &&
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((com->pc98_8251fifo_enable &&
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(inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP))
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== (STS8251F_TxRDY | STS8251F_TxEMP)) ||
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(inb(I8251F_lsr) & (FLSR_TxRDY | FLSR_TxEMP))
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== (FLSR_TxRDY | FLSR_TxEMP)) ||
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(!com->pc98_8251fifo_enable &&
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(inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
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== (STS8251_TxRDY | STS8251_TxEMP)))) ||
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@ -2298,12 +2298,12 @@ status_read:;
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more_intr:
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line_status = 0;
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if (com->pc98_8251fifo_enable) {
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if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY;
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if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY;
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if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE;
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if (tmp & STS8251F_PE) line_status |= LSR_PE;
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if (tmp & STS8251F_OE) line_status |= LSR_OE;
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if (tmp & STS8251F_BD_SD) line_status |= LSR_BI;
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if (tmp & FLSR_TxRDY) line_status |= LSR_TXRDY;
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if (tmp & FLSR_RxRDY) line_status |= LSR_RXRDY;
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if (tmp & FLSR_TxEMP) line_status |= LSR_TSRE;
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if (tmp & FLSR_PE) line_status |= LSR_PE;
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if (tmp & FLSR_OE) line_status |= LSR_OE;
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if (tmp & FLSR_BI) line_status |= LSR_BI;
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} else {
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if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
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if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
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@ -2311,7 +2311,7 @@ status_read:;
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if (tmp & STS8251_PE) line_status |= LSR_PE;
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if (tmp & STS8251_OE) line_status |= LSR_OE;
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if (tmp & STS8251_FE) line_status |= LSR_FE;
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if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
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if (tmp & STS8251_BI) line_status |= LSR_BI;
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}
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} else {
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#endif /* PC98 */
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@ -2345,15 +2345,15 @@ status_read:;
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if (IS_8251(com->pc98_if_type)) {
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if (com->pc98_8251fifo_enable) {
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recv_data = inb(I8251F_data);
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if (tmp & (STS8251F_PE | STS8251F_OE |
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STS8251F_BD_SD)) {
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if (tmp &
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(FLSR_PE | FLSR_OE | FLSR_BI)) {
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pc98_i8251_or_cmd(com, CMD8251_ER);
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recv_data = 0;
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}
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} else {
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recv_data = inb(com->data_port);
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if (tmp & (STS8251_PE | STS8251_OE |
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STS8251_FE | STS8251_BD_SD)) {
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STS8251_FE | STS8251_BI)) {
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pc98_i8251_or_cmd(com, CMD8251_ER);
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recv_data = 0;
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}
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@ -2626,7 +2626,7 @@ if (com->iptr - com->ibuf == 8)
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}
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if (IS_8251(com->pc98_if_type)) {
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if (com->pc98_8251fifo_enable) {
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if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY)
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if ((tmp = inb(I8251F_lsr)) & FLSR_RxRDY)
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goto more_intr;
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} else {
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if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
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@ -3874,10 +3874,10 @@ pc98_get_modem_status(struct com_s *com)
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int stat2;
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stat2 = inb(I8251F_msr);
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if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR;
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if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI;
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if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR;
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if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS;
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if ( stat2 & MSR_DCD ) msr |= TIOCM_CAR;
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if ( stat2 & MSR_RI ) msr |= TIOCM_RI;
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if ( stat2 & MSR_DSR ) msr |= TIOCM_DSR;
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if ( stat2 & MSR_CTS ) msr |= TIOCM_CTS;
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#if COM_CARRIER_DETECT_EMULATE
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if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
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msr |= TIOCM_CAR;
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@ -4005,7 +4005,7 @@ pc98_i8251_clear_cmd(struct com_s *com, int x)
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outb(com->cmd_port, tmp);
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com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
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if (com->pc98_8251fifo_enable)
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outb(I8251F_fcr, CTRL8251F_ENABLE);
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outb(I8251F_fcr, FIFO_ENABLE);
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COM_INT_ENABLE
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}
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@ -4021,7 +4021,7 @@ pc98_i8251_or_cmd(struct com_s *com, int x)
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outb(com->cmd_port, tmp);
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com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
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if (com->pc98_8251fifo_enable)
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outb(I8251F_fcr, CTRL8251F_ENABLE);
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outb(I8251F_fcr, FIFO_ENABLE);
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COM_INT_ENABLE
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}
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@ -4037,7 +4037,7 @@ pc98_i8251_set_cmd(struct com_s *com, int x)
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outb(com->cmd_port, tmp);
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com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
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if (com->pc98_8251fifo_enable)
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outb(I8251F_fcr, CTRL8251F_ENABLE);
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outb(I8251F_fcr, FIFO_ENABLE);
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COM_INT_ENABLE
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}
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@ -4053,7 +4053,7 @@ pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
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outb(com->cmd_port, tmp);
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com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
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if (com->pc98_8251fifo_enable)
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outb(I8251F_fcr, CTRL8251F_ENABLE);
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outb(I8251F_fcr, FIFO_ENABLE);
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COM_INT_ENABLE
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}
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@ -4088,8 +4088,7 @@ pc98_i8251_reset(struct com_s *com, int mode, int command)
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pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
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DELAY(10);
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if (com->pc98_8251fifo_enable)
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outb(I8251F_fcr, CTRL8251F_ENABLE |
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CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
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outb(I8251F_fcr, FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
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}
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static void
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@ -4131,11 +4130,10 @@ com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
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}
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if ( cflag&PARENB ) {
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if ( cflag&PARODD )
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cfcr |= MOD8251_PODD;
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cfcr |= MOD8251_PENAB;
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else
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cfcr |= MOD8251_PEVEN;
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} else
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cfcr |= MOD8251_PDISAB;
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cfcr |= MOD8251_PENAB | MOD8251_PEVEN;
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}
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if ( cflag&CSTOPB )
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cfcr |= MOD8251_STOP2;
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@ -4143,9 +4141,9 @@ com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
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cfcr |= MOD8251_STOP1;
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if ( count & 0x10000 )
|
||||
cfcr |= MOD8251_CLKX1;
|
||||
cfcr |= MOD8251_CLKx1;
|
||||
else
|
||||
cfcr |= MOD8251_CLKX16;
|
||||
cfcr |= MOD8251_CLKx16;
|
||||
|
||||
while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
|
||||
;
|
||||
|
Loading…
Reference in New Issue
Block a user