Teach the PCI code to parse MSI extended capabilities. Re-arrange the
pcicfg struct a bit to hold extcap structures instead of structure members.
This commit is contained in:
parent
251998aaee
commit
ec40a9f9d0
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=120063
@ -431,14 +431,22 @@ pci_read_extcap(device_t pcib, pcicfgregs *cfg)
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/* Process this entry */
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switch (REG(ptr, 1)) {
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case PCIY_PMG: /* PCI power management */
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if (cfg->pp_cap == 0) {
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cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
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cfg->pp_status = ptr + PCIR_POWER_STATUS;
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cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
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if (cfg->pp.pp_cap == 0) {
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cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
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cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
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cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
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if ((nextptr - ptr) > PCIR_POWER_DATA)
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cfg->pp_data = ptr + PCIR_POWER_DATA;
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cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
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}
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break;
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case PCIY_MSI: /* PCI MSI */
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cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
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if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT)
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cfg->msi.msi_data = PCIR_MSI_DATA_64BIT;
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else
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cfg->msi.msi_data = PCIR_MSI_DATA;
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cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
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PCIM_MSICTRL_MMC_MASK)>>1);
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default:
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break;
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}
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@ -477,22 +485,23 @@ pci_set_powerstate_method(device_t dev, device_t child, int state)
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uint16_t status;
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int result;
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if (cfg->pp_cap != 0) {
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status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
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if (cfg->pp.pp_cap != 0) {
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status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
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& ~PCIM_PSTAT_DMASK;
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result = 0;
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switch (state) {
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case PCI_POWERSTATE_D0:
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status |= PCIM_PSTAT_D0;
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break;
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case PCI_POWERSTATE_D1:
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if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
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if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) {
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status |= PCIM_PSTAT_D1;
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} else {
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result = EOPNOTSUPP;
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}
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break;
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case PCI_POWERSTATE_D2:
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if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
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if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) {
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status |= PCIM_PSTAT_D2;
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} else {
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result = EOPNOTSUPP;
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@ -505,7 +514,8 @@ pci_set_powerstate_method(device_t dev, device_t child, int state)
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result = EINVAL;
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}
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if (result == 0)
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PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
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PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status,
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2);
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} else {
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result = ENXIO;
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}
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@ -520,8 +530,8 @@ pci_get_powerstate_method(device_t dev, device_t child)
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uint16_t status;
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int result;
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if (cfg->pp_cap != 0) {
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status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
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if (cfg->pp.pp_cap != 0) {
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status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
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switch (status & PCIM_PSTAT_DMASK) {
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case PCIM_PSTAT_D0:
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result = PCI_POWERSTATE_D0;
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@ -671,16 +681,26 @@ pci_print_verbose(struct pci_devinfo *dinfo)
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if (cfg->intpin > 0)
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printf("\tintpin=%c, irq=%d\n",
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cfg->intpin +'a' -1, cfg->intline);
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if (cfg->pp_cap) {
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if (cfg->pp.pp_cap) {
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uint16_t status;
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status = pci_read_config(cfg->dev, cfg->pp_status, 2);
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status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
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printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
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cfg->pp_cap & PCIM_PCAP_SPEC,
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cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
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cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
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cfg->pp.pp_cap & PCIM_PCAP_SPEC,
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cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
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cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
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status & PCIM_PSTAT_DMASK);
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}
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if (cfg->msi.msi_data) {
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int ctrl;
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ctrl = cfg->msi.msi_ctrl;
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printf("\tMSI supports %d message%s%s%s\n",
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cfg->msi.msi_msgnum,
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(cfg->msi.msi_msgnum == 1) ? "" : "s",
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(ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
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(ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
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}
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}
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}
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@ -349,7 +349,7 @@
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#define PCIR_MSI_ADDR 0x4
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#define PCIR_MSI_ADDR_HIGH 0x8
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#define PCIR_MSI_DATA 0x8
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#define PCIR_MSI_DATA_HIGH 0xc
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#define PCIR_MSI_DATA_64BIT 0xc
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#define PCIR_MSI_MASK 0x10
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#define PCIR_MSI_PENDING 0x14
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@ -51,6 +51,21 @@ typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */
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typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */
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#endif
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/* Interesting values for PCI power management */
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struct pcicfg_pp {
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uint16_t pp_cap; /* PCI power management capabilities */
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uint8_t pp_status; /* config space address of PCI power status reg */
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uint8_t pp_pmcsr; /* config space address of PMCSR reg */
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uint8_t pp_data; /* config space address of PCI power data reg */
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};
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/* Interesting values for PCI MSI */
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struct pcicfg_msi {
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uint16_t msi_ctrl; /* Message Control */
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uint8_t msi_msgnum; /* Number of messages */
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uint16_t msi_data; /* Location of MSI data word */
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};
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/* config header information common to all header types */
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typedef struct pcicfg {
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@ -85,11 +100,8 @@ typedef struct pcicfg {
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uint8_t slot; /* config space slot address */
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uint8_t func; /* config space function number */
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uint16_t pp_cap; /* PCI power management capabilities */
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uint8_t pp_status; /* config space address of PCI power status reg */
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uint8_t pp_pmcsr; /* config space address of PMCSR reg */
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uint8_t pp_data; /* config space address of PCI power data reg */
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struct pcicfg_pp pp; /* pci power management */
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struct pcicfg_msi msi; /* pci msi */
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} pcicfgregs;
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/* additional type 1 device config header information (PCI to PCI bridge) */
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