NTB: MFV 2f887b9a: Rename Intel code names to platform names
Mechanically replace "SOC" with "ATOM" to match Linux. No functional change. Original Linux commit log follows: Instead of using the platform code names, use the correct platform names to identify the respective Intel NTB hardware. Authored by: Dave Jiang Obtained from: Linux (Dual BSD/GPL driver) Sponsored by: EMC / Isilon Storage Division
This commit is contained in:
Conrad Meyer
parent
3a8a0a9dfa
commit
eccd1f0a14
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=289648
@ -60,16 +60,16 @@ __FBSDID("$FreeBSD$");
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* be picked up and redistributed in Linux with a dual GPL/BSD license.
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*/
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#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, SOC_DB_COUNT)
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#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT)
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#define NTB_HB_TIMEOUT 1 /* second */
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#define SOC_LINK_RECOVERY_TIME 500 /* ms */
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#define ATOM_LINK_RECOVERY_TIME 500 /* ms */
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#define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev))
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enum ntb_device_type {
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NTB_XEON,
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NTB_SOC
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NTB_ATOM
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};
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/* ntb_conn_type are hardware numbers, cannot change. */
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@ -287,11 +287,11 @@ static void ntb_free_msix_vec(struct ntb_softc *ntb);
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static struct ntb_hw_info *ntb_get_device_info(uint32_t device_id);
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static void ntb_detect_max_mw(struct ntb_softc *ntb);
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static int ntb_detect_xeon(struct ntb_softc *ntb);
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static int ntb_detect_soc(struct ntb_softc *ntb);
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static int ntb_detect_atom(struct ntb_softc *ntb);
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static int ntb_xeon_init_dev(struct ntb_softc *ntb);
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static int ntb_soc_init_dev(struct ntb_softc *ntb);
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static int ntb_atom_init_dev(struct ntb_softc *ntb);
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static void ntb_teardown_xeon(struct ntb_softc *ntb);
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static void configure_soc_secondary_side_bars(struct ntb_softc *ntb);
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static void configure_atom_secondary_side_bars(struct ntb_softc *ntb);
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static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx,
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enum ntb_bar regbar);
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static void xeon_set_sbar_base_and_limit(struct ntb_softc *,
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@ -301,19 +301,19 @@ static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr,
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static int xeon_setup_b2b_mw(struct ntb_softc *,
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const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr);
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static inline bool link_is_up(struct ntb_softc *ntb);
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static inline bool soc_link_is_err(struct ntb_softc *ntb);
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static inline bool atom_link_is_err(struct ntb_softc *ntb);
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static inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *);
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static inline enum ntb_width ntb_link_sta_width(struct ntb_softc *);
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static void soc_link_hb(void *arg);
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static void atom_link_hb(void *arg);
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static void ntb_db_event(struct ntb_softc *ntb, uint32_t vec);
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static void recover_soc_link(void *arg);
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static void recover_atom_link(void *arg);
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static bool ntb_poll_link(struct ntb_softc *ntb);
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static void save_bar_parameters(struct ntb_pci_bar_info *bar);
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static struct ntb_hw_info pci_ids[] = {
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/* XXX: PS/SS IDs left out until they are supported. */
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{ 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B",
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NTB_SOC, 0 },
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NTB_ATOM, 0 },
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{ 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B",
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NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 },
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@ -329,40 +329,40 @@ static struct ntb_hw_info pci_ids[] = {
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NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 |
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NTB_SB01BASE_LOCKUP },
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{ 0x00000000, NULL, NTB_SOC, 0 }
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{ 0x00000000, NULL, NTB_ATOM, 0 }
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};
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static const struct ntb_reg soc_reg = {
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.ntb_ctl = SOC_NTBCNTL_OFFSET,
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.lnk_sta = SOC_LINK_STATUS_OFFSET,
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static const struct ntb_reg atom_reg = {
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.ntb_ctl = ATOM_NTBCNTL_OFFSET,
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.lnk_sta = ATOM_LINK_STATUS_OFFSET,
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.db_size = sizeof(uint64_t),
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.mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 },
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};
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static const struct ntb_alt_reg soc_pri_reg = {
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.db_bell = SOC_PDOORBELL_OFFSET,
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.db_mask = SOC_PDBMSK_OFFSET,
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.spad = SOC_SPAD_OFFSET,
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static const struct ntb_alt_reg atom_pri_reg = {
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.db_bell = ATOM_PDOORBELL_OFFSET,
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.db_mask = ATOM_PDBMSK_OFFSET,
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.spad = ATOM_SPAD_OFFSET,
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};
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static const struct ntb_alt_reg soc_b2b_reg = {
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.db_bell = SOC_B2B_DOORBELL_OFFSET,
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.spad = SOC_B2B_SPAD_OFFSET,
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static const struct ntb_alt_reg atom_b2b_reg = {
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.db_bell = ATOM_B2B_DOORBELL_OFFSET,
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.spad = ATOM_B2B_SPAD_OFFSET,
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};
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static const struct ntb_xlat_reg soc_sec_xlat = {
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static const struct ntb_xlat_reg atom_sec_xlat = {
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#if 0
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/* "FIXME" says the Linux driver. */
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.bar0_base = SOC_SBAR0BASE_OFFSET,
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.bar2_base = SOC_SBAR2BASE_OFFSET,
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.bar4_base = SOC_SBAR4BASE_OFFSET,
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.bar0_base = ATOM_SBAR0BASE_OFFSET,
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.bar2_base = ATOM_SBAR2BASE_OFFSET,
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.bar4_base = ATOM_SBAR4BASE_OFFSET,
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.bar2_limit = SOC_SBAR2LMT_OFFSET,
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.bar4_limit = SOC_SBAR4LMT_OFFSET,
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.bar2_limit = ATOM_SBAR2LMT_OFFSET,
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.bar4_limit = ATOM_SBAR4LMT_OFFSET,
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#endif
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.bar2_xlat = SOC_SBAR2XLAT_OFFSET,
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.bar4_xlat = SOC_SBAR4XLAT_OFFSET,
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.bar2_xlat = ATOM_SBAR2XLAT_OFFSET,
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.bar4_xlat = ATOM_SBAR4XLAT_OFFSET,
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};
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static const struct ntb_reg xeon_reg = {
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@ -501,14 +501,14 @@ ntb_attach(device_t device)
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ntb->features = p->features;
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ntb->b2b_mw_idx = B2B_MW_DISABLED;
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/* Heartbeat timer for NTB_SOC since there is no link interrupt */
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/* Heartbeat timer for NTB_ATOM since there is no link interrupt */
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callout_init(&ntb->heartbeat_timer, 1);
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callout_init(&ntb->lr_timer, 1);
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mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN);
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mtx_init(&ntb->ctx_lock, "ntb ctx", NULL, MTX_SPIN);
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if (ntb->type == NTB_SOC)
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error = ntb_detect_soc(ntb);
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if (ntb->type == NTB_ATOM)
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error = ntb_detect_atom(ntb);
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else
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error = ntb_detect_xeon(ntb);
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if (error)
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@ -519,8 +519,8 @@ ntb_attach(device_t device)
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error = ntb_map_pci_bars(ntb);
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if (error)
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goto out;
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if (ntb->type == NTB_SOC)
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error = ntb_soc_init_dev(ntb);
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if (ntb->type == NTB_ATOM)
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error = ntb_atom_init_dev(ntb);
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else
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error = ntb_xeon_init_dev(ntb);
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if (error)
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@ -965,14 +965,14 @@ ntb_teardown_interrupts(struct ntb_softc *ntb)
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}
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/*
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* Doorbell register and mask are 64-bit on SoC, 16-bit on Xeon. Abstract it
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* Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it
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* out to make code clearer.
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*/
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static inline uint64_t
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db_ioread(struct ntb_softc *ntb, uint64_t regoff)
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{
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if (ntb->type == NTB_SOC)
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if (ntb->type == NTB_ATOM)
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return (ntb_reg_read(8, regoff));
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KASSERT(ntb->type == NTB_XEON, ("bad ntb type"));
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@ -992,7 +992,7 @@ db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val)
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if (regoff == ntb->self_reg->db_mask)
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DB_MASK_ASSERT(ntb, MA_OWNED);
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if (ntb->type == NTB_SOC) {
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if (ntb->type == NTB_ATOM) {
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ntb_reg_write(8, regoff, val);
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return;
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}
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@ -1138,8 +1138,8 @@ static void
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ntb_detect_max_mw(struct ntb_softc *ntb)
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{
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if (ntb->type == NTB_SOC) {
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ntb->mw_count = SOC_MW_COUNT;
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if (ntb->type == NTB_ATOM) {
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ntb->mw_count = ATOM_MW_COUNT;
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return;
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}
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@ -1185,19 +1185,19 @@ ntb_detect_xeon(struct ntb_softc *ntb)
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}
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static int
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ntb_detect_soc(struct ntb_softc *ntb)
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ntb_detect_atom(struct ntb_softc *ntb)
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{
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uint32_t ppd, conn_type;
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ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4);
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ntb->ppd = ppd;
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if ((ppd & SOC_PPD_DEV_TYPE) != 0)
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if ((ppd & ATOM_PPD_DEV_TYPE) != 0)
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ntb->dev_type = NTB_DEV_DSD;
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else
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ntb->dev_type = NTB_DEV_USD;
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conn_type = (ppd & SOC_PPD_CONN_TYPE) >> 8;
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conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8;
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switch (conn_type) {
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case NTB_CONN_B2B:
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ntb->conn_type = conn_type;
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@ -1274,62 +1274,62 @@ ntb_xeon_init_dev(struct ntb_softc *ntb)
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}
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static int
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ntb_soc_init_dev(struct ntb_softc *ntb)
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ntb_atom_init_dev(struct ntb_softc *ntb)
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{
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KASSERT(ntb->conn_type == NTB_CONN_B2B,
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("Unsupported NTB configuration (%d)\n", ntb->conn_type));
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ntb->spad_count = SOC_SPAD_COUNT;
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ntb->db_count = SOC_DB_COUNT;
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ntb->db_vec_count = SOC_DB_MSIX_VECTOR_COUNT;
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ntb->db_vec_shift = SOC_DB_MSIX_VECTOR_SHIFT;
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ntb->spad_count = ATOM_SPAD_COUNT;
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ntb->db_count = ATOM_DB_COUNT;
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ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT;
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ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT;
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ntb->db_valid_mask = (1ull << ntb->db_count) - 1;
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ntb->reg = &soc_reg;
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ntb->self_reg = &soc_pri_reg;
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ntb->peer_reg = &soc_b2b_reg;
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ntb->xlat_reg = &soc_sec_xlat;
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ntb->reg = &atom_reg;
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ntb->self_reg = &atom_pri_reg;
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ntb->peer_reg = &atom_b2b_reg;
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ntb->xlat_reg = &atom_sec_xlat;
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/*
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* FIXME - MSI-X bug on early SOC HW, remove once internal issue is
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* FIXME - MSI-X bug on early Atom HW, remove once internal issue is
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* resolved. Mask transaction layer internal parity errors.
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*/
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pci_write_config(ntb->device, 0xFC, 0x4, 4);
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configure_soc_secondary_side_bars(ntb);
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configure_atom_secondary_side_bars(ntb);
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/* Enable Bus Master and Memory Space on the secondary side */
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ntb_reg_write(2, SOC_PCICMD_OFFSET,
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ntb_reg_write(2, ATOM_PCICMD_OFFSET,
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PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
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/* Initiate PCI-E link training */
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ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO);
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callout_reset(&ntb->heartbeat_timer, 0, soc_link_hb, ntb);
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callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb);
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return (0);
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}
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/* XXX: Linux driver doesn't seem to do any of this for SoC. */
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/* XXX: Linux driver doesn't seem to do any of this for Atom. */
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static void
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configure_soc_secondary_side_bars(struct ntb_softc *ntb)
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configure_atom_secondary_side_bars(struct ntb_softc *ntb)
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{
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if (ntb->dev_type == NTB_DEV_USD) {
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ntb_reg_write(8, SOC_PBAR2XLAT_OFFSET,
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ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
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XEON_B2B_BAR2_DSD_ADDR64);
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ntb_reg_write(8, SOC_PBAR4XLAT_OFFSET,
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ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
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XEON_B2B_BAR4_DSD_ADDR64);
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ntb_reg_write(8, SOC_MBAR23_OFFSET, XEON_B2B_BAR2_USD_ADDR64);
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ntb_reg_write(8, SOC_MBAR45_OFFSET, XEON_B2B_BAR4_USD_ADDR64);
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ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_USD_ADDR64);
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ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_USD_ADDR64);
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} else {
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ntb_reg_write(8, SOC_PBAR2XLAT_OFFSET,
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ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
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XEON_B2B_BAR2_USD_ADDR64);
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ntb_reg_write(8, SOC_PBAR4XLAT_OFFSET,
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ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
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XEON_B2B_BAR4_USD_ADDR64);
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ntb_reg_write(8, SOC_MBAR23_OFFSET, XEON_B2B_BAR2_DSD_ADDR64);
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ntb_reg_write(8, SOC_MBAR45_OFFSET, XEON_B2B_BAR4_DSD_ADDR64);
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ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_DSD_ADDR64);
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ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_DSD_ADDR64);
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}
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}
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@ -1542,28 +1542,28 @@ link_is_up(struct ntb_softc *ntb)
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return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0);
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}
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KASSERT(ntb->type == NTB_SOC, ("ntb type"));
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return ((ntb->ntb_ctl & SOC_CNTL_LINK_DOWN) == 0);
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KASSERT(ntb->type == NTB_ATOM, ("ntb type"));
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return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0);
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}
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static inline bool
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soc_link_is_err(struct ntb_softc *ntb)
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atom_link_is_err(struct ntb_softc *ntb)
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{
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uint32_t status;
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KASSERT(ntb->type == NTB_SOC, ("ntb type"));
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KASSERT(ntb->type == NTB_ATOM, ("ntb type"));
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status = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET);
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if ((status & SOC_LTSSMSTATEJMP_FORCEDETECT) != 0)
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status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
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if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0)
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return (true);
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status = ntb_reg_read(4, SOC_IBSTERRRCRVSTS0_OFFSET);
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return ((status & SOC_IBIST_ERR_OFLOW) != 0);
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status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
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return ((status & ATOM_IBIST_ERR_OFLOW) != 0);
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}
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/* SOC does not have link status interrupt, poll on that platform */
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/* Atom does not have link status interrupt, poll on that platform */
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static void
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soc_link_hb(void *arg)
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atom_link_hb(void *arg)
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{
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struct ntb_softc *ntb = arg;
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sbintime_t timo, poll_ts;
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@ -1583,53 +1583,53 @@ soc_link_hb(void *arg)
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if (ntb_poll_link(ntb))
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ntb_link_event(ntb);
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if (!link_is_up(ntb) && soc_link_is_err(ntb)) {
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if (!link_is_up(ntb) && atom_link_is_err(ntb)) {
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/* Link is down with error, proceed with recovery */
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callout_reset(&ntb->lr_timer, 0, recover_soc_link, ntb);
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callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb);
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return;
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}
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out:
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callout_reset(&ntb->heartbeat_timer, timo, soc_link_hb, ntb);
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callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb);
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}
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static void
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soc_perform_link_restart(struct ntb_softc *ntb)
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atom_perform_link_restart(struct ntb_softc *ntb)
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{
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uint32_t status;
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/* Driver resets the NTB ModPhy lanes - magic! */
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ntb_reg_write(1, SOC_MODPHY_PCSREG6, 0xe0);
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ntb_reg_write(1, SOC_MODPHY_PCSREG4, 0x40);
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ntb_reg_write(1, SOC_MODPHY_PCSREG4, 0x60);
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ntb_reg_write(1, SOC_MODPHY_PCSREG6, 0x60);
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ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0);
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ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40);
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ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60);
|
||||
ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60);
|
||||
|
||||
/* Driver waits 100ms to allow the NTB ModPhy to settle */
|
||||
pause("ModPhy", hz / 10);
|
||||
|
||||
/* Clear AER Errors, write to clear */
|
||||
status = ntb_reg_read(4, SOC_ERRCORSTS_OFFSET);
|
||||
status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET);
|
||||
status &= PCIM_AER_COR_REPLAY_ROLLOVER;
|
||||
ntb_reg_write(4, SOC_ERRCORSTS_OFFSET, status);
|
||||
ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status);
|
||||
|
||||
/* Clear unexpected electrical idle event in LTSSM, write to clear */
|
||||
status = ntb_reg_read(4, SOC_LTSSMERRSTS0_OFFSET);
|
||||
status |= SOC_LTSSMERRSTS0_UNEXPECTEDEI;
|
||||
ntb_reg_write(4, SOC_LTSSMERRSTS0_OFFSET, status);
|
||||
status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET);
|
||||
status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
|
||||
ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status);
|
||||
|
||||
/* Clear DeSkew Buffer error, write to clear */
|
||||
status = ntb_reg_read(4, SOC_DESKEWSTS_OFFSET);
|
||||
status |= SOC_DESKEWSTS_DBERR;
|
||||
ntb_reg_write(4, SOC_DESKEWSTS_OFFSET, status);
|
||||
status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET);
|
||||
status |= ATOM_DESKEWSTS_DBERR;
|
||||
ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status);
|
||||
|
||||
status = ntb_reg_read(4, SOC_IBSTERRRCRVSTS0_OFFSET);
|
||||
status &= SOC_IBIST_ERR_OFLOW;
|
||||
ntb_reg_write(4, SOC_IBSTERRRCRVSTS0_OFFSET, status);
|
||||
status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
|
||||
status &= ATOM_IBIST_ERR_OFLOW;
|
||||
ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status);
|
||||
|
||||
/* Releases the NTB state machine to allow the link to retrain */
|
||||
status = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET);
|
||||
status &= ~SOC_LTSSMSTATEJMP_FORCEDETECT;
|
||||
ntb_reg_write(4, SOC_LTSSMSTATEJMP_OFFSET, status);
|
||||
status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
|
||||
status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
|
||||
ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1758,9 +1758,9 @@ ntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused,
|
||||
{
|
||||
uint32_t cntl;
|
||||
|
||||
if (ntb->type == NTB_SOC) {
|
||||
if (ntb->type == NTB_ATOM) {
|
||||
pci_write_config(ntb->device, NTB_PPD_OFFSET,
|
||||
ntb->ppd | SOC_PPD_INIT_LINK, 4);
|
||||
ntb->ppd | ATOM_PPD_INIT_LINK, 4);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -1812,13 +1812,13 @@ ntb_link_disable(struct ntb_softc *ntb)
|
||||
}
|
||||
|
||||
static void
|
||||
recover_soc_link(void *arg)
|
||||
recover_atom_link(void *arg)
|
||||
{
|
||||
struct ntb_softc *ntb = arg;
|
||||
unsigned speed, width, oldspeed, oldwidth;
|
||||
uint32_t status32;
|
||||
|
||||
soc_perform_link_restart(ntb);
|
||||
atom_perform_link_restart(ntb);
|
||||
|
||||
/*
|
||||
* There is a potential race between the 2 NTB devices recovering at
|
||||
@ -1826,14 +1826,14 @@ recover_soc_link(void *arg)
|
||||
* and the driver will be stuck in this loop forever. Add a random
|
||||
* interval to the recovery time to prevent this race.
|
||||
*/
|
||||
status32 = arc4random() % SOC_LINK_RECOVERY_TIME;
|
||||
pause("Link", (SOC_LINK_RECOVERY_TIME + status32) * hz / 1000);
|
||||
status32 = arc4random() % ATOM_LINK_RECOVERY_TIME;
|
||||
pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000);
|
||||
|
||||
if (soc_link_is_err(ntb))
|
||||
if (atom_link_is_err(ntb))
|
||||
goto retry;
|
||||
|
||||
status32 = ntb_reg_read(4, ntb->reg->ntb_ctl);
|
||||
if ((status32 & SOC_CNTL_LINK_DOWN) != 0)
|
||||
if ((status32 & ATOM_CNTL_LINK_DOWN) != 0)
|
||||
goto out;
|
||||
|
||||
status32 = ntb_reg_read(4, ntb->reg->lnk_sta);
|
||||
@ -1846,12 +1846,12 @@ recover_soc_link(void *arg)
|
||||
goto retry;
|
||||
|
||||
out:
|
||||
callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, soc_link_hb,
|
||||
callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb,
|
||||
ntb);
|
||||
return;
|
||||
|
||||
retry:
|
||||
callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_soc_link,
|
||||
callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link,
|
||||
ntb);
|
||||
}
|
||||
|
||||
@ -1864,7 +1864,7 @@ ntb_poll_link(struct ntb_softc *ntb)
|
||||
uint32_t ntb_cntl;
|
||||
uint16_t reg_val;
|
||||
|
||||
if (ntb->type == NTB_SOC) {
|
||||
if (ntb->type == NTB_ATOM) {
|
||||
ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
|
||||
if (ntb_cntl == ntb->ntb_ctl)
|
||||
return (false);
|
||||
|
||||
@ -81,48 +81,48 @@
|
||||
#define XEON_B2B_XLAT_OFFSETL 0x0144
|
||||
#define XEON_B2B_XLAT_OFFSETU 0x0148
|
||||
|
||||
#define SOC_MW_COUNT 2
|
||||
#define SOC_DB_COUNT 34
|
||||
#define SOC_DB_MSIX_VECTOR_COUNT 34
|
||||
#define SOC_DB_MSIX_VECTOR_SHIFT 1
|
||||
#define SOC_SPAD_COUNT 16
|
||||
#define ATOM_MW_COUNT 2
|
||||
#define ATOM_DB_COUNT 34
|
||||
#define ATOM_DB_MSIX_VECTOR_COUNT 34
|
||||
#define ATOM_DB_MSIX_VECTOR_SHIFT 1
|
||||
#define ATOM_SPAD_COUNT 16
|
||||
|
||||
#define SOC_PCICMD_OFFSET 0xb004
|
||||
#define SOC_MBAR23_OFFSET 0xb018
|
||||
#define SOC_MBAR45_OFFSET 0xb020
|
||||
#define SOC_DEVCTRL_OFFSET 0xb048
|
||||
#define SOC_LINK_STATUS_OFFSET 0xb052
|
||||
#define SOC_ERRCORSTS_OFFSET 0xb110
|
||||
#define ATOM_PCICMD_OFFSET 0xb004
|
||||
#define ATOM_MBAR23_OFFSET 0xb018
|
||||
#define ATOM_MBAR45_OFFSET 0xb020
|
||||
#define ATOM_DEVCTRL_OFFSET 0xb048
|
||||
#define ATOM_LINK_STATUS_OFFSET 0xb052
|
||||
#define ATOM_ERRCORSTS_OFFSET 0xb110
|
||||
|
||||
#define SOC_SBAR2XLAT_OFFSET 0x0008
|
||||
#define SOC_SBAR4XLAT_OFFSET 0x0010
|
||||
#define SOC_PDOORBELL_OFFSET 0x0020
|
||||
#define SOC_PDBMSK_OFFSET 0x0028
|
||||
#define SOC_NTBCNTL_OFFSET 0x0060
|
||||
#define SOC_EBDF_OFFSET 0x0064
|
||||
#define SOC_SPAD_OFFSET 0x0080
|
||||
#define SOC_SPADSEMA_OFFSET 0x00c0
|
||||
#define SOC_STKYSPAD_OFFSET 0x00c4
|
||||
#define SOC_PBAR2XLAT_OFFSET 0x8008
|
||||
#define SOC_PBAR4XLAT_OFFSET 0x8010
|
||||
#define SOC_B2B_DOORBELL_OFFSET 0x8020
|
||||
#define SOC_B2B_SPAD_OFFSET 0x8080
|
||||
#define SOC_B2B_SPADSEMA_OFFSET 0x80c0
|
||||
#define SOC_B2B_STKYSPAD_OFFSET 0x80c4
|
||||
#define ATOM_SBAR2XLAT_OFFSET 0x0008
|
||||
#define ATOM_SBAR4XLAT_OFFSET 0x0010
|
||||
#define ATOM_PDOORBELL_OFFSET 0x0020
|
||||
#define ATOM_PDBMSK_OFFSET 0x0028
|
||||
#define ATOM_NTBCNTL_OFFSET 0x0060
|
||||
#define ATOM_EBDF_OFFSET 0x0064
|
||||
#define ATOM_SPAD_OFFSET 0x0080
|
||||
#define ATOM_SPADSEMA_OFFSET 0x00c0
|
||||
#define ATOM_STKYSPAD_OFFSET 0x00c4
|
||||
#define ATOM_PBAR2XLAT_OFFSET 0x8008
|
||||
#define ATOM_PBAR4XLAT_OFFSET 0x8010
|
||||
#define ATOM_B2B_DOORBELL_OFFSET 0x8020
|
||||
#define ATOM_B2B_SPAD_OFFSET 0x8080
|
||||
#define ATOM_B2B_SPADSEMA_OFFSET 0x80c0
|
||||
#define ATOM_B2B_STKYSPAD_OFFSET 0x80c4
|
||||
|
||||
#define SOC_MODPHY_PCSREG4 0x1c004
|
||||
#define SOC_MODPHY_PCSREG6 0x1c006
|
||||
#define ATOM_MODPHY_PCSREG4 0x1c004
|
||||
#define ATOM_MODPHY_PCSREG6 0x1c006
|
||||
|
||||
#define SOC_IP_BASE 0xc000
|
||||
#define SOC_DESKEWSTS_OFFSET (SOC_IP_BASE + 0x3024)
|
||||
#define SOC_LTSSMERRSTS0_OFFSET (SOC_IP_BASE + 0x3180)
|
||||
#define SOC_LTSSMSTATEJMP_OFFSET (SOC_IP_BASE + 0x3040)
|
||||
#define SOC_IBSTERRRCRVSTS0_OFFSET (SOC_IP_BASE + 0x3324)
|
||||
#define ATOM_IP_BASE 0xc000
|
||||
#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
|
||||
#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
|
||||
#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
|
||||
#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
|
||||
|
||||
#define SOC_DESKEWSTS_DBERR (1 << 15)
|
||||
#define SOC_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
|
||||
#define SOC_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
|
||||
#define SOC_IBIST_ERR_OFLOW 0x7fff7fff
|
||||
#define ATOM_DESKEWSTS_DBERR (1 << 15)
|
||||
#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
|
||||
#define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
|
||||
#define ATOM_IBIST_ERR_OFLOW 0x7fff7fff
|
||||
|
||||
#define NTB_CNTL_CFG_LOCK (1 << 0)
|
||||
#define NTB_CNTL_LINK_DISABLE (1 << 1)
|
||||
@ -132,7 +132,7 @@
|
||||
#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
|
||||
#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
|
||||
#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
|
||||
#define SOC_CNTL_LINK_DOWN (1 << 16)
|
||||
#define ATOM_CNTL_LINK_DOWN (1 << 16)
|
||||
|
||||
#define XEON_PBAR23SZ_OFFSET 0x00d0
|
||||
#define XEON_PBAR45SZ_OFFSET 0x00d1
|
||||
@ -145,9 +145,9 @@
|
||||
#define XEON_PPD_CONN_TYPE 0x0003
|
||||
#define XEON_PPD_DEV_TYPE 0x0010
|
||||
#define XEON_PPD_SPLIT_BAR 0x0040
|
||||
#define SOC_PPD_INIT_LINK 0x0008
|
||||
#define SOC_PPD_CONN_TYPE 0x0300
|
||||
#define SOC_PPD_DEV_TYPE 0x1000
|
||||
#define ATOM_PPD_INIT_LINK 0x0008
|
||||
#define ATOM_PPD_CONN_TYPE 0x0300
|
||||
#define ATOM_PPD_DEV_TYPE 0x1000
|
||||
|
||||
/* All addresses are in low 32-bit space so 32-bit BARs can function */
|
||||
#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull
|
||||
|
||||
Loading…
Reference in New Issue
Block a user