Rework RX filter programming by providing separate handler for
DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
This commit is contained in:
Pyun YongHyeon
parent
6bd823f334
commit
ed15702f7e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=217548
@ -149,6 +149,9 @@ static int sis_ioctl(struct ifnet *, u_long, caddr_t);
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static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
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static int sis_resume(device_t);
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static int sis_rxeof(struct sis_softc *);
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static void sis_rxfilter(struct sis_softc *);
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static void sis_rxfilter_ns(struct sis_softc *);
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static void sis_rxfilter_sis(struct sis_softc *);
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static void sis_start(struct ifnet *);
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static void sis_startl(struct ifnet *);
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static void sis_stop(struct sis_softc *);
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@ -806,80 +809,117 @@ sis_mchash(struct sis_softc *sc, const uint8_t *addr)
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}
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static void
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sis_setmulti_ns(struct sis_softc *sc)
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sis_rxfilter(struct sis_softc *sc)
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{
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struct ifnet *ifp;
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struct ifmultiaddr *ifma;
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uint32_t h = 0, i, filtsave;
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int bit, index;
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ifp = sc->sis_ifp;
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SIS_LOCK_ASSERT(sc);
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if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
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SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
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SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
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return;
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}
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/*
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* We have to explicitly enable the multicast hash table
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* on the NatSemi chip if we want to use it, which we do.
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*/
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SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
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SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
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filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
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/* first, zot all the existing hash bits */
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for (i = 0; i < 32; i++) {
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
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CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
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}
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if_maddr_rlock(ifp);
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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h = sis_mchash(sc,
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LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
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index = h >> 3;
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bit = h & 0x1F;
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
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if (bit > 0xF)
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bit -= 0x10;
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SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
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}
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if_maddr_runlock(ifp);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
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if (sc->sis_type == SIS_TYPE_83815)
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sis_rxfilter_ns(sc);
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else
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sis_rxfilter_sis(sc);
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}
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static void
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sis_setmulti_sis(struct sis_softc *sc)
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sis_rxfilter_ns(struct sis_softc *sc)
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{
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struct ifnet *ifp;
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struct ifmultiaddr *ifma;
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uint32_t h, i, n, ctl;
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uint32_t h, i, filter;
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int bit, index;
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ifp = sc->sis_ifp;
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filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
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if (filter & SIS_RXFILTCTL_ENABLE) {
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/*
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* Filter should be disabled to program other bits.
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*/
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
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CSR_READ_4(sc, SIS_RXFILT_CTL);
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}
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filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
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NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
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SIS_RXFILTCTL_ALLMULTI);
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if (ifp->if_flags & IFF_BROADCAST)
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filter |= SIS_RXFILTCTL_BROAD;
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/*
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* For the NatSemi chip, we have to explicitly enable the
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* reception of ARP frames, as well as turn on the 'perfect
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* match' filter where we store the station address, otherwise
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* we won't receive unicasts meant for this host.
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*/
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filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
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if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
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filter |= SIS_RXFILTCTL_ALLMULTI;
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if (ifp->if_flags & IFF_PROMISC)
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filter |= SIS_RXFILTCTL_ALLPHYS;
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} else {
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/*
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* We have to explicitly enable the multicast hash table
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* on the NatSemi chip if we want to use it, which we do.
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*/
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filter |= NS_RXFILTCTL_MCHASH;
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/* first, zot all the existing hash bits */
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for (i = 0; i < 32; i++) {
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
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(i * 2));
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CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
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}
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if_maddr_rlock(ifp);
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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h = sis_mchash(sc,
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LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
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index = h >> 3;
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bit = h & 0x1F;
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
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index);
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if (bit > 0xF)
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bit -= 0x10;
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SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
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}
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if_maddr_runlock(ifp);
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}
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
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CSR_READ_4(sc, SIS_RXFILT_CTL);
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}
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static void
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sis_rxfilter_sis(struct sis_softc *sc)
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{
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struct ifnet *ifp;
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struct ifmultiaddr *ifma;
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uint32_t filter, h, i, n;
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uint16_t hashes[16];
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ifp = sc->sis_ifp;
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/* hash table size */
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if (sc->sis_rev >= SIS_REV_635 ||
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sc->sis_rev == SIS_REV_900B)
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if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
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n = 16;
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else
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n = 8;
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ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
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filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
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if (filter & SIS_RXFILTCTL_ENABLE) {
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL);
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CSR_READ_4(sc, SIS_RXFILT_CTL);
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}
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filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
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SIS_RXFILTCTL_ALLMULTI);
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if (ifp->if_flags & IFF_BROADCAST)
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ctl |= SIS_RXFILTCTL_BROAD;
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filter |= SIS_RXFILTCTL_BROAD;
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if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
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ctl |= SIS_RXFILTCTL_ALLMULTI;
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if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
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filter |= SIS_RXFILTCTL_ALLMULTI;
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if (ifp->if_flags & IFF_PROMISC)
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ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
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filter |= SIS_RXFILTCTL_ALLPHYS;
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for (i = 0; i < n; i++)
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hashes[i] = ~0;
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} else {
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@ -897,7 +937,7 @@ sis_setmulti_sis(struct sis_softc *sc)
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}
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if_maddr_runlock(ifp);
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if (i > n) {
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ctl |= SIS_RXFILTCTL_ALLMULTI;
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filter |= SIS_RXFILTCTL_ALLMULTI;
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for (i = 0; i < n; i++)
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hashes[i] = ~0;
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}
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@ -908,7 +948,8 @@ sis_setmulti_sis(struct sis_softc *sc)
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CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
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}
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
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CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
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CSR_READ_4(sc, SIS_RXFILT_CTL);
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}
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static void
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@ -2104,41 +2145,7 @@ sis_initl(struct sis_softc *sc)
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
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}
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/*
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* For the NatSemi chip, we have to explicitly enable the
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* reception of ARP frames, as well as turn on the 'perfect
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* match' filter where we store the station address, otherwise
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* we won't receive unicasts meant for this host.
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*/
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if (sc->sis_type == SIS_TYPE_83815) {
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SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
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SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
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}
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/* If we want promiscuous mode, set the allframes bit. */
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if (ifp->if_flags & IFF_PROMISC) {
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SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
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} else {
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SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
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}
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/*
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* Set the capture broadcast bit to capture broadcast frames.
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*/
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if (ifp->if_flags & IFF_BROADCAST) {
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SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
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} else {
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SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
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}
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/*
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* Load the multicast filter.
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*/
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if (sc->sis_type == SIS_TYPE_83815)
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sis_setmulti_ns(sc);
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else
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sis_setmulti_sis(sc);
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sis_rxfilter(sc);
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/* Turn the receive filter on */
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SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
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@ -2252,27 +2259,19 @@ sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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if (ifp->if_flags & IFF_UP) {
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if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
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((ifp->if_flags ^ sc->sis_if_flags) &
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(IFF_PROMISC | IFF_ALLMULTI)) != 0) {
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if (sc->sis_type == SIS_TYPE_83815)
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sis_setmulti_ns(sc);
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else
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sis_setmulti_sis(sc);
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} else
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(IFF_PROMISC | IFF_ALLMULTI)) != 0)
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sis_rxfilter(sc);
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else
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sis_initl(sc);
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} else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
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} else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
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sis_stop(sc);
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}
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sc->sis_if_flags = ifp->if_flags;
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SIS_UNLOCK(sc);
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error = 0;
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break;
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case SIOCADDMULTI:
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case SIOCDELMULTI:
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SIS_LOCK(sc);
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if (sc->sis_type == SIS_TYPE_83815)
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sis_setmulti_ns(sc);
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else
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sis_setmulti_sis(sc);
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sis_rxfilter(sc);
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SIS_UNLOCK(sc);
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break;
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case SIOCGIFMEDIA:
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