Fix the style of locore-v4.S and locore-v6.S to help find any common code.
This commit is contained in:
Andrew Turner
parent
365a1e502e
commit
ed5bb96b5d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=282024
@ -250,7 +250,7 @@ virt_done:
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/* init arm will return the new stack pointer. */
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mov sp, r0
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bl _C_LABEL(mi_startup) /* call mi_startup()! */
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bl _C_LABEL(mi_startup) /* call mi_startup()! */
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adr r0, .Lmainreturned
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b _C_LABEL(panic)
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@ -428,7 +428,7 @@ ENTRY(longjmp)
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END(longjmp)
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.data
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.global _C_LABEL(esym)
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.global _C_LABEL(esym)
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_C_LABEL(esym): .word _C_LABEL(end)
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ENTRY_NP(abort)
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@ -441,7 +441,7 @@ ENTRY_NP(sigcode)
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/*
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* Call the sigreturn system call.
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*
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*
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* We have to load r7 manually rather than using
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* "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
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* correct. Using the alternative places esigcode at the address
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@ -52,13 +52,13 @@ __FBSDID("$FreeBSD$");
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.align 2
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/*
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* On entry for FreeBSD boot ABI:
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* r0 - metadata pointer or 0 (boothowto on AT91's boot2)
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* r1 - if (r0 == 0) then metadata pointer
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* On entry for Linux boot ABI:
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* On entry for FreeBSD boot ABI:
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* r0 - metadata pointer or 0 (boothowto on AT91's boot2)
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* r1 - if (r0 == 0) then metadata pointer
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* On entry for Linux boot ABI:
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* r0 - 0
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* r1 - machine type (passed as arg2 to initarm)
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* r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
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* r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
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*
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* For both types of boot we gather up the args, put them in a struct arm_boot_params
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* structure and pass that to initarm.
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@ -66,17 +66,17 @@ __FBSDID("$FreeBSD$");
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.globl btext
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btext:
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ASENTRY_NP(_start)
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STOP_UNWINDING /* Can't unwind into the bootloader! */
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STOP_UNWINDING /* Can't unwind into the bootloader! */
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/* Make sure interrupts are disabled. */
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/* Make sure interrupts are disabled. */
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cpsid ifa
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mov r8, r0 /* 0 or boot mode from boot2 */
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mov r9, r1 /* Save Machine type */
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mov r10, r2 /* Save meta data */
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mov r8, r0 /* 0 or boot mode from boot2 */
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mov r9, r1 /* Save Machine type */
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mov r10, r2 /* Save meta data */
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mov r11, r3 /* Future expansion */
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/*
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/*
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* Check whether data cache is enabled. If it is, then we know
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* current tags are valid (not power-on garbage values) and there
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* might be dirty lines that need cleaning. Disable cache to prevent
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@ -119,13 +119,13 @@ ASENTRY_NP(_start)
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/*
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* Map PA == VA
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*/
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/* Find the start kernels load address */
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/* Find the start kernels load address */
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adr r5, _start
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ldr r2, =(PTE1_OFFSET)
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bic r5, r2
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mov r1, r5
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mov r2, r5
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/* Map 64MiB, preserved over calls to build_pagetables */
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/* Map 64MiB, preserved over calls to build_pagetables */
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mov r3, #64
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bl build_pagetables
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@ -142,41 +142,41 @@ ASENTRY_NP(_start)
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#endif
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bl init_mmu
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/* Switch to virtual addresses. */
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/* Switch to virtual addresses. */
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ldr pc, =1f
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1:
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/* Setup stack, clear BSS */
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/* Setup stack, clear BSS */
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ldr r1, =.Lstart
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ldmia r1, {r1, r2, sp} /* Set initial stack and */
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add sp, sp, #INIT_ARM_STACK_SIZE
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sub r2, r2, r1 /* get zero init data */
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sub r2, r2, r1 /* get zero init data */
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mov r3, #0
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2:
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str r3, [r1], #0x0004 /* get zero init data */
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subs r2, r2, #4
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subs r2, r2, #4
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bgt 2b
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mov r1, #28 /* loader info size is 28 bytes also second arg */
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subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
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mov r0, sp /* loader info pointer is first arg */
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bic sp, sp, #7 /* align stack to 8 bytes */
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str r1, [r0] /* Store length of loader info */
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mov r1, #28 /* loader info size is 28 bytes also second arg */
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subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
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mov r0, sp /* loader info pointer is first arg */
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bic sp, sp, #7 /* align stack to 8 bytes */
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str r1, [r0] /* Store length of loader info */
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str r8, [r0, #4] /* Store r0 from boot loader */
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str r9, [r0, #8] /* Store r1 from boot loader */
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str r10, [r0, #12] /* store r2 from boot loader */
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str r11, [r0, #16] /* store r3 from boot loader */
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str r5, [r0, #20] /* store the physical address */
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adr r4, Lpagetable /* load the pagetable address */
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adr r4, Lpagetable /* load the pagetable address */
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ldr r5, [r4, #4]
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str r5, [r0, #24] /* store the pagetable address */
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mov fp, #0 /* trace back starts here */
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bl _C_LABEL(initarm) /* Off we go */
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/* init arm will return the new stack pointer. */
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/* init arm will return the new stack pointer. */
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mov sp, r0
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bl _C_LABEL(mi_startup) /* call mi_startup()! */
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bl _C_LABEL(mi_startup) /* call mi_startup()! */
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ldr r0, =.Lmainreturned
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b _C_LABEL(panic)
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@ -219,8 +219,8 @@ translate_va_to_pa:
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mov pc, lr
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/*
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* Init MMU
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* r0 - The table base address
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* Init MMU
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* r0 - the table base address
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*/
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ASENTRY_NP(init_mmu)
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@ -267,11 +267,11 @@ END(init_mmu)
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/*
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* Init SMP coherent mode, enable caching and switch to final MMU table.
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* Called with disabled caches
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* r0 - The table base address
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* r1 - clear bits for aux register
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* r2 - set bits for aux register
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* Init SMP coherent mode, enable caching and switch to final MMU table.
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* Called with disabled caches
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* r0 - The table base address
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* r1 - clear bits for aux register
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* r2 - set bits for aux register
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*/
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ASENTRY_NP(reinit_mmu)
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push {r4-r11, lr}
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@ -331,11 +331,11 @@ END(reinit_mmu)
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/*
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* Builds the page table
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* r0 - The table base address
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* r1 - The physical address (trashed)
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* r2 - The virtual address (trashed)
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* r3 - The number of 1MiB sections
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* r4 - Trashed
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* r0 - The table base address
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* r1 - The physical address (trashed)
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* r2 - The virtual address (trashed)
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* r3 - The number of 1MiB sections
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* r4 - Trashed
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*
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* Addresses must be 1MiB aligned
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*/
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@ -350,15 +350,15 @@ build_pagetables:
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#endif
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orr r1, r4
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/* Move the virtual address to the correct bit location */
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/* Move the virtual address to the correct bit location */
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lsr r2, #(PTE1_SHIFT - 2)
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mov r4, r3
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1:
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str r1, [r0, r2]
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add r2, r2, #4
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add r1, r1, #(PTE1_SIZE)
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adds r4, r4, #-1
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add r2, r2, #4
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add r1, r1, #(PTE1_SIZE)
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adds r4, r4, #-1
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bhi 1b
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mov pc, lr
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@ -372,7 +372,7 @@ VA_TO_PA_POINTER(Lpagetable, boot_pt1)
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.word svcstk /* must remain in order together. */
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.Lmainreturned:
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.asciz "main() returned"
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.asciz "main() returned"
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.align 2
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.bss
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@ -380,8 +380,8 @@ svcstk:
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.space INIT_ARM_STACK_SIZE * MAXCPU
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/*
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* Memory for the initial pagetable. We are unable to place this in
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* the bss as this will be cleared after the table is loaded.
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* Memory for the initial pagetable. We are unable to place this in
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* the bss as this will be cleared after the table is loaded.
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*/
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.section ".init_pagetable"
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.align 14 /* 16KiB aligned */
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@ -398,7 +398,7 @@ boot_pt1:
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#if defined(SMP)
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ASENTRY_NP(mpentry)
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/* Make sure interrupts are disabled. */
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/* Make sure interrupts are disabled. */
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cpsid ifa
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/* Setup core, disable all caches. */
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@ -419,7 +419,7 @@ ASENTRY_NP(mpentry)
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mcr CP15_ICIALLU
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ISB
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/* Find the delta between VA and PA */
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/* Find the delta between VA and PA */
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adr r0, Lpagetable
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bl translate_va_to_pa
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@ -433,7 +433,7 @@ ASENTRY_NP(mpentry)
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mul r2, r1, r0 /* Point sp to initstack */
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add sp, sp, r2 /* area for this processor. */
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/* Switch to virtual addresses. */
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/* Switch to virtual addresses. */
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ldr pc, =1f
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1:
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mov fp, #0 /* trace back starts here */
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@ -466,7 +466,7 @@ ENTRY_NP(cpu_halt)
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/*
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* _cpu_reset_address contains the address to branch to, to complete
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* the cpu reset after turning the MMU off
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* This variable is provided by the hardware specific code
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* This variable is provided by the hardware specific code
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*/
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.Lcpu_reset_address:
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.word _C_LABEL(cpu_reset_address)
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@ -498,38 +498,37 @@ END(abort)
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ENTRY_NP(sigcode)
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mov r0, sp
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add r0, r0, #SIGF_UC
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add r0, r0, #SIGF_UC
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/*
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* Call the sigreturn system call.
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* Call the sigreturn system call.
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*
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* We have to load r7 manually rather than using
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* "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
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* "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
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* correct. Using the alternative places esigcode at the address
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* of the data rather than the address one past the data.
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* of the data rather than the address one past the data.
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*/
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ldr r7, [pc, #12] /* Load SYS_sigreturn */
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ldr r7, [pc, #12] /* Load SYS_sigreturn */
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swi SYS_sigreturn
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/* Well if that failed we better exit quick ! */
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/* Well if that failed we better exit quick ! */
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ldr r7, [pc, #8] /* Load SYS_exit */
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ldr r7, [pc, #8] /* Load SYS_exit */
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swi SYS_exit
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/* Branch back to retry SYS_sigreturn */
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/* Branch back to retry SYS_sigreturn */
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b . - 16
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END(sigcode)
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.word SYS_sigreturn
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.word SYS_exit
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.align 2
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.global _C_LABEL(esigcode)
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.global _C_LABEL(esigcode)
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_C_LABEL(esigcode):
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.data
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.global szsigcode
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.global szsigcode
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szsigcode:
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.long esigcode-sigcode
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