Convert the mx driver to miibus.
In order to make this work, I created a pseudo-PHY driver to deal with Macronix chips that use the built-in NWAY support and symbol mode port. This is actually all of them, with the exception of the original MX98713 which presents its NWAY support via the MII serial interface. The mxphy driver actually manipulates the controller registers directly rather than using the miibus_readreg()/miibus_writereg() bus interface since there are no MII registers to read. The mx driver itself pretends that the NWAY interface is a PHY locayed at MII address 31 for the sole purpose of allowing the mxphy_probe() routine to know when it needs to attach to a host controller.
This commit is contained in:
Bill Paul
parent
35c0baa6b7
commit
ed8c6514c4
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=52282
@ -38,6 +38,7 @@
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.Nd
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Macronix 98713/98715/98725 fast ethernet device driver
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.Sh SYNOPSIS
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.Cd "controller miibus0"
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.Cd "device mx0"
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.Sh DESCRIPTION
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The
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@ -38,6 +38,7 @@
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.Nd
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Macronix 98713/98715/98725 fast ethernet device driver
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.Sh SYNOPSIS
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.Cd "controller miibus0"
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.Cd "device mx0"
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.Sh DESCRIPTION
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The
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@ -116,13 +116,13 @@ device ax0 # ASIX AX88140A
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device de0 # DEC/Intel DC21x4x (``Tulip'')
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device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
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device le0 # Lance
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device mx0 # Macronix 98713/98715/98725 (``PMAC'')
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device pn0 # Lite-On 82c168/82c169 (``PNIC'')
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# PCI Ethernet NICs that use the common MII bus controller code.
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controller miibus0 # MII bus support
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device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
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device dm0 # Davicom DM9100/DM9102
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device pn0 # Lite-On 82c168/82c169 (``PNIC'')
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device mx0 # Macronix 98713/98715/98725 (``PMAC'')
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device rl0 # RealTek 8129/8139
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device sf0 # Adaptec AIC-6915 (``Starfire'')
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device sis0 # Silicon Integrated Systems SiS 900/SiS 7016
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@ -116,13 +116,13 @@ device ax0 # ASIX AX88140A
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device de0 # DEC/Intel DC21x4x (``Tulip'')
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device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
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device le0 # Lance
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device mx0 # Macronix 98713/98715/98725 (``PMAC'')
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device pn0 # Lite-On 82c168/82c169 (``PNIC'')
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# PCI Ethernet NICs that use the common MII bus controller code.
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controller miibus0 # MII bus support
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device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
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device dm0 # Davicom DM9100/DM9102
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device pn0 # Lite-On 82c168/82c169 (``PNIC'')
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device mx0 # Macronix 98713/98715/98725 (``PMAC'')
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device rl0 # RealTek 8129/8139
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device sf0 # Adaptec AIC-6915 (``Starfire'')
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device sis0 # Silicon Integrated Systems SiS 900/SiS 7016
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@ -161,7 +161,6 @@ device ppi0 # Parallel port interface device
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device ax0 # ASIX AX88140A
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device de0 # DEC/Intel DC21x4x (``Tulip'')
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device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
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device mx0 # Macronix 98713/98715/98725 (``PMAC'')
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device pn0 # Lite-On 82c168/82c169 (``PNIC'')
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device tx0 # SMC 9432TX (83c170 ``EPIC'')
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device vx0 # 3Com 3c590, 3c595 (``Vortex'')
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@ -170,6 +169,7 @@ device vx0 # 3Com 3c590, 3c595 (``Vortex'')
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controller miibus0 # MII bus support
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device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
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device dm0 # Davicom DM9100/DM9102
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device mx0 # Macronix 98713/98715/98725 (``PMAC'')
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device rl0 # RealTek 8129/8139
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device sf0 # Adaptec AIC-6915 (``Starfire'')
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device sis0 # Silicon Integrated Systems SiS 900/SiS 7016
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487
sys/dev/mii/mxphy.c
Normal file
487
sys/dev/mii/mxphy.c
Normal file
@ -0,0 +1,487 @@
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/*
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* pseudo-driver for internal NWAY support on Macronix 98713/98715/98725
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* PMAC controller chips. The Macronix chips use the same internal
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* NWAY register layout as the DEC/Intel 21143. Technically we're
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* abusing the miibus code to handle the media selection and NWAY
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* support here since there is no MII interface. However the logical
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* operations are roughly the same, and the alternative is to create
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* a fake MII interface in the driver, which is harder to do.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/socket.h>
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#include <sys/errno.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <machine/clock.h>
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#include <machine/bus_pio.h>
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#include <machine/bus_memio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <pci/if_mxreg.h>
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#include "miibus_if.h"
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#if !defined(lint)
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static const char rcsid[] =
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"$FreeBSD$";
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#endif
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#define MX_SETBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) | x)
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#define MX_CLRBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) & ~x)
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struct mxphy_softc {
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struct mii_softc mx_mii;
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u_int32_t mx_linkstate;
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u_int32_t mx_media;
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};
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static int mxphy_probe __P((device_t));
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static int mxphy_attach __P((device_t));
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static int mxphy_detach __P((device_t));
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static device_method_t mxphy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, mxphy_probe),
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DEVMETHOD(device_attach, mxphy_attach),
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DEVMETHOD(device_detach, mxphy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ 0, 0 }
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};
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static devclass_t mxphy_devclass;
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static driver_t mxphy_driver = {
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"mxphy",
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mxphy_methods,
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sizeof(struct mxphy_softc)
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};
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DRIVER_MODULE(mxphy, miibus, mxphy_driver, mxphy_devclass, 0, 0);
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int mxphy_service __P((struct mii_softc *, struct mii_data *, int));
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void mxphy_status __P((struct mii_softc *));
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static int mxphy_auto __P((struct mii_softc *, int));
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static void mxphy_auto_timeout __P((void *));
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static void mxphy_reset __P((struct mii_softc *));
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static int mxphy_probe(dev)
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device_t dev;
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{
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struct mii_attach_args *ma;
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ma = device_get_ivars(dev);
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/*
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* The mx driver will report the Macronix vendor ID
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* and the 98715 device ID to let us know that it wants
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* us to attach. Actually, we could also be attached
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* in the case of a 98713A chip, but there's no point
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* in differentiating between the two since we do the
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* same things for both.
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*/
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if (ma->mii_id1 != MX_VENDORID ||
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ma->mii_id2 != MX_DEVICEID_987x5)
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return(ENXIO);
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device_set_desc(dev, "Macronix NWAY media interface");
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return (0);
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}
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static int mxphy_attach(dev)
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device_t dev;
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{
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struct mxphy_softc *msc;
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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msc = device_get_softc(dev);
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sc = &msc->mx_mii;
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = mxphy_service;
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sc->mii_pdata = mii;
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sc->mii_flags |= MIIF_NOISOLATE;
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mii->mii_instance++;
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
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BMCR_ISO);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
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BMCR_LOOP|BMCR_S100);
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/*mxphy_reset(sc);*/
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sc->mii_capabilities =
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BMSR_ANEG|BMSR_100TXFDX|BMSR_100TXHDX|BMSR_10TFDX|BMSR_10THDX;
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sc->mii_capabilities &= ma->mii_capmask;
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device_printf(dev, " ");
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if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
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printf("no media present");
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else
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mii_add_media(mii, sc->mii_capabilities, sc->mii_inst);
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printf("\n");
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#undef ADD
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int mxphy_detach(dev)
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device_t dev;
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{
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struct mxphy_softc *sc;
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struct mii_data *mii;
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sc = device_get_softc(dev);
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mii = device_get_softc(device_get_parent(dev));
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sc->mx_mii.mii_dev = NULL;
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LIST_REMOVE(&sc->mx_mii, mii_list);
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return(0);
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}
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int
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mxphy_service(xsc, mii, cmd)
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struct mii_softc *xsc;
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struct mii_data *mii;
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int cmd;
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{
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struct mx_softc *mx_sc;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg;
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u_int32_t mode;
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struct mxphy_softc *msc = (struct mxphy_softc *)xsc;
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struct mii_softc *sc = (struct mii_softc *)&msc->mx_mii;
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mx_sc = mii->mii_ifp->if_softc;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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return (0);
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}
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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mode = CSR_READ_4(mx_sc, MX_NETCFG);
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mode &= ~(MX_NETCFG_FULLDUPLEX|MX_NETCFG_PORTSEL|
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MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER|MX_NETCFG_SPEEDSEL);
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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mxphy_reset(sc);
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(void) mxphy_auto(sc, 1);
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msc->mx_linkstate = msc->mx_media = 0;
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break;
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case IFM_100_T4:
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/*
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* XXX Not supported as a manual setting right now.
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*/
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return (EINVAL);
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case IFM_100_TX:
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mode |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS|
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MX_NETCFG_SCRAMBLER;
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
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mode |= MX_NETCFG_FULLDUPLEX;
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else
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mode &= ~MX_NETCFG_FULLDUPLEX;
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MX_CLRBIT(mx_sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
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CSR_WRITE_4(mx_sc, MX_NETCFG, mode);
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break;
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case IFM_10_T:
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mode &= ~MX_NETCFG_PORTSEL;
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mode |= MX_NETCFG_SPEEDSEL;
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
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mode |= MX_NETCFG_FULLDUPLEX;
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else
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mode &= ~MX_NETCFG_FULLDUPLEX;
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MX_CLRBIT(mx_sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
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CSR_WRITE_4(mx_sc, MX_NETCFG, mode);
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break;
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default:
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return(EINVAL);
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break;
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
|
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|
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/*
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* Only used for autonegotiation.
|
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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return (0);
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|
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/*
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* Is the interface even up?
|
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
|
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*/
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reg = CSR_READ_4(mx_sc, MX_10BTSTAT) &
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(MX_TSTAT_LS10|MX_TSTAT_LS100);
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reg = CSR_READ_4(mx_sc, MX_10BTSTAT) &
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(MX_TSTAT_LS10|MX_TSTAT_LS100);
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|
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if (reg == msc->mx_linkstate)
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return (0);
|
||||
if (!reg) {
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msc->mx_linkstate = reg;
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break;
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}
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msc->mx_media = 0;
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sc->mii_ticks = 0;
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msc->mx_linkstate = reg;
|
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mxphy_reset(sc);
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if (mxphy_auto(sc, 0) == EJUSTRETURN)
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return (0);
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break;
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}
|
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|
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/* Update the media status. */
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mxphy_status(sc);
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|
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/* Callback if something changed. */
|
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if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
|
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MIIBUS_STATCHG(sc->mii_dev);
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DELAY(100000);
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sc->mii_active = mii->mii_media_active;
|
||||
}
|
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return (0);
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||||
}
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||||
|
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void
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mxphy_status(sc)
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struct mii_softc *sc;
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||||
{
|
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struct mii_data *mii = sc->mii_pdata;
|
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int /*bmsr, bmcr,*/ reg, anlpar;
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struct mx_softc *mx_sc;
|
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struct mxphy_softc *msc = (struct mxphy_softc *)sc;
|
||||
|
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mx_sc = mii->mii_ifp->if_softc;
|
||||
|
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mii->mii_media_status = IFM_AVALID;
|
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mii->mii_media_active = IFM_ETHER;
|
||||
|
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reg = CSR_READ_4(mx_sc, MX_10BTSTAT) &
|
||||
(MX_TSTAT_LS10|MX_TSTAT_LS100);
|
||||
|
||||
if (!(reg & MX_TSTAT_LS10) || !(reg & MX_TSTAT_LS100))
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
|
||||
if (CSR_READ_4(mx_sc, MX_10BTCTRL) & MX_TCTL_AUTONEGENBL &&
|
||||
CSR_READ_4(mx_sc, MX_10BTSTAT) & MX_TSTAT_ANEGSTAT) {
|
||||
if (!(CSR_READ_4(mx_sc, MX_10BTSTAT) & 0xFFFF0000)) {
|
||||
/* Erg, still trying, I guess... */
|
||||
if (CSR_READ_4(mx_sc, MX_10BTSTAT) &
|
||||
MX_TSTAT_LP_CAN_NWAY) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
} else
|
||||
msc->mx_media = 0;
|
||||
}
|
||||
|
||||
if (CSR_READ_4(mx_sc, MX_10BTSTAT) & MX_TSTAT_LP_CAN_NWAY) {
|
||||
anlpar = CSR_READ_4(mx_sc, MX_10BTSTAT) >> 16;
|
||||
if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
else if (anlpar & ANLPAR_TX_FD)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_TX)
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else if (anlpar & ANLPAR_10_FD)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_10)
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
msc->mx_media = mii->mii_media_active;
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (msc->mx_media)
|
||||
mii->mii_media_active = msc->mx_media;
|
||||
reg = CSR_READ_4(mx_sc, MX_10BTSTAT) &
|
||||
(MX_TSTAT_LS10|MX_TSTAT_LS100);
|
||||
|
||||
msc->mx_linkstate = reg;
|
||||
if (!(reg & MX_TSTAT_LS100))
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
msc->mx_media = mii->mii_media_active;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int
|
||||
mxphy_auto(mii, waitfor)
|
||||
struct mii_softc *mii;
|
||||
int waitfor;
|
||||
{
|
||||
int i;
|
||||
struct mx_softc *sc;
|
||||
|
||||
sc = mii->mii_pdata->mii_ifp->if_softc;
|
||||
|
||||
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
|
||||
CSR_WRITE_4(sc, MX_10BTCTRL, 0x3FFFF);
|
||||
MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
|
||||
MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX);
|
||||
MX_SETBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
|
||||
MX_SETBIT(sc, MX_10BTCTRL, MX_ASTAT_TXDISABLE);
|
||||
DELAY(1000000);
|
||||
}
|
||||
|
||||
if (waitfor) {
|
||||
/* Wait 500ms for it to complete. */
|
||||
for (i = 0; i < 500; i++) {
|
||||
if ((CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_ANEGSTAT)
|
||||
== MX_ASTAT_AUTONEGCMP)
|
||||
return(0);
|
||||
DELAY(1000);
|
||||
}
|
||||
/*
|
||||
* Don't need to worry about clearing MIIF_DOINGAUTO.
|
||||
* If that's set, a timeout is pending, and it will
|
||||
* clear the flag.
|
||||
*/
|
||||
return(EIO);
|
||||
}
|
||||
|
||||
/*
|
||||
* Just let it finish asynchronously. This is for the benefit of
|
||||
* the tick handler driving autonegotiation. Don't want 500ms
|
||||
* delays all the time while the system is running!
|
||||
*/
|
||||
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
|
||||
mii->mii_flags |= MIIF_DOINGAUTO;
|
||||
timeout(mxphy_auto_timeout, mii, hz >> 1);
|
||||
}
|
||||
return(EJUSTRETURN);
|
||||
}
|
||||
|
||||
static void
|
||||
mxphy_auto_timeout(arg)
|
||||
void *arg;
|
||||
{
|
||||
struct mii_softc *mii = arg;
|
||||
int s;
|
||||
|
||||
s = splnet();
|
||||
mii->mii_flags &= ~MIIF_DOINGAUTO;
|
||||
|
||||
/* Update the media status. */
|
||||
(void) (*mii->mii_service)(mii, mii->mii_pdata, MII_POLLSTAT);
|
||||
splx(s);
|
||||
}
|
||||
|
||||
static void
|
||||
mxphy_reset(mii)
|
||||
struct mii_softc *mii;
|
||||
{
|
||||
struct mx_softc *sc;
|
||||
|
||||
sc = mii->mii_pdata->mii_ifp->if_softc;
|
||||
|
||||
MX_SETBIT(sc, MX_SIARESET, MX_SIA_RESET_NWAY);
|
||||
DELAY(1000);
|
||||
MX_CLRBIT(sc, MX_SIARESET, MX_SIA_RESET_NWAY);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
@ -161,7 +161,6 @@ device ppi0 # Parallel port interface device
|
||||
device ax0 # ASIX AX88140A
|
||||
device de0 # DEC/Intel DC21x4x (``Tulip'')
|
||||
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
|
||||
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
|
||||
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
|
||||
device tx0 # SMC 9432TX (83c170 ``EPIC'')
|
||||
device vx0 # 3Com 3c590, 3c595 (``Vortex'')
|
||||
@ -170,6 +169,7 @@ device vx0 # 3Com 3c590, 3c595 (``Vortex'')
|
||||
controller miibus0 # MII bus support
|
||||
device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
|
||||
device dm0 # Davicom DM9100/DM9102
|
||||
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
|
||||
device rl0 # RealTek 8129/8139
|
||||
device sf0 # Adaptec AIC-6915 (``Starfire'')
|
||||
device sis0 # Silicon Integrated Systems SiS 900/SiS 7016
|
||||
|
||||
@ -5,7 +5,7 @@ S = ${.CURDIR}/../..
|
||||
KMOD = miibus
|
||||
SRCS = mii.c mii_physubr.c ukphy.c ukphy_subr.c bus_if.h
|
||||
SRCS += miibus_if.h device_if.h miibus_if.c exphy.c nsphy.c
|
||||
SRCS += mlphy.c tlphy.c rlphy.c amphy.c
|
||||
SRCS += mlphy.c tlphy.c rlphy.c amphy.c mxphy.c
|
||||
CLEANFILES += device_if.h bus_if.h miibus_if.h miibus_if.c
|
||||
CFLAGS += ${DEBUG_FLAGS}
|
||||
|
||||
|
||||
@ -3,8 +3,8 @@
|
||||
S = ${.CURDIR}/../..
|
||||
.PATH: $S/pci
|
||||
KMOD = if_mx
|
||||
SRCS = if_mx.c opt_bdg.h device_if.h bus_if.h pci_if.h
|
||||
CLEANFILES += opt_bdg.h device_if.h bus_if.h pci_if.h
|
||||
SRCS = if_mx.c opt_bdg.h device_if.h bus_if.h pci_if.h miibus_if.h
|
||||
CLEANFILES += opt_bdg.h device_if.h bus_if.h pci_if.h miibus_if.h
|
||||
CFLAGS += ${DEBUG_FLAGS}
|
||||
|
||||
opt_bdg.h:
|
||||
@ -19,4 +19,7 @@ bus_if.h: $S/kern/makedevops.pl $S/kern/bus_if.m
|
||||
pci_if.h: $S/kern/makedevops.pl $S/pci/pci_if.m
|
||||
perl $S/kern/makedevops.pl -h $S/pci/pci_if.m
|
||||
|
||||
miibus_if.h: $S/kern/makedevops.pl $S/dev/mii/miibus_if.m
|
||||
perl $S/kern/makedevops.pl -h $S/dev/mii/miibus_if.m
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
||||
924
sys/pci/if_mx.c
924
sys/pci/if_mx.c
File diff suppressed because it is too large
Load Diff
@ -479,24 +479,21 @@ struct mx_mii_frame {
|
||||
|
||||
struct mx_softc {
|
||||
struct arpcom arpcom; /* interface info */
|
||||
struct ifmedia ifmedia; /* media info */
|
||||
bus_space_handle_t mx_bhandle; /* bus space handle */
|
||||
bus_space_tag_t mx_btag; /* bus space tag */
|
||||
void *mx_intrhand;
|
||||
struct resource *mx_irq;
|
||||
struct resource *mx_res;
|
||||
device_t mx_miibus;
|
||||
struct mx_type *mx_info; /* Macronix adapter info */
|
||||
struct mx_type *mx_pinfo; /* phy info */
|
||||
u_int8_t mx_unit; /* interface number */
|
||||
u_int8_t mx_type;
|
||||
u_int8_t mx_phy_addr; /* PHY address */
|
||||
u_int8_t mx_tx_pend; /* TX pending */
|
||||
u_int8_t mx_want_auto;
|
||||
u_int8_t mx_autoneg;
|
||||
u_int8_t mx_cachesize;
|
||||
int mx_if_flags;
|
||||
caddr_t mx_ldata_ptr;
|
||||
struct mx_list_data *mx_ldata;
|
||||
struct mx_chain_data mx_cdata;
|
||||
struct callout_handle mx_stat_ch;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -553,38 +550,6 @@ struct mx_softc {
|
||||
*/
|
||||
#define PN_DEVICEID_PNIC_II 0xc115
|
||||
|
||||
/*
|
||||
* Texas Instruments PHY identifiers
|
||||
*/
|
||||
#define TI_PHY_VENDORID 0x4000
|
||||
#define TI_PHY_10BT 0x501F
|
||||
#define TI_PHY_100VGPMI 0x502F
|
||||
|
||||
/*
|
||||
* These ID values are for the NS DP83840A 10/100 PHY
|
||||
*/
|
||||
#define NS_PHY_VENDORID 0x2000
|
||||
#define NS_PHY_83840A 0x5C0F
|
||||
|
||||
/*
|
||||
* Level 1 10/100 PHY
|
||||
*/
|
||||
#define LEVEL1_PHY_VENDORID 0x7810
|
||||
#define LEVEL1_PHY_LXT970 0x000F
|
||||
|
||||
/*
|
||||
* Intel 82555 10/100 PHY
|
||||
*/
|
||||
#define INTEL_PHY_VENDORID 0x0A28
|
||||
#define INTEL_PHY_82555 0x015F
|
||||
|
||||
/*
|
||||
* SEEQ 80220 10/100 PHY
|
||||
*/
|
||||
#define SEEQ_PHY_VENDORID 0x0016
|
||||
#define SEEQ_PHY_80220 0xF83F
|
||||
|
||||
|
||||
/*
|
||||
* PCI low memory base and low I/O base register, and
|
||||
* other PCI registers.
|
||||
@ -623,105 +588,6 @@ struct mx_softc {
|
||||
#define MX_PME_EN 0x0010
|
||||
#define MX_PME_STATUS 0x8000
|
||||
|
||||
#define PHY_UNKNOWN 6
|
||||
|
||||
#define MX_PHYADDR_MIN 0x00
|
||||
#define MX_PHYADDR_MAX 0x1F
|
||||
|
||||
#define PHY_BMCR 0x00
|
||||
#define PHY_BMSR 0x01
|
||||
#define PHY_VENID 0x02
|
||||
#define PHY_DEVID 0x03
|
||||
#define PHY_ANAR 0x04
|
||||
#define PHY_LPAR 0x05
|
||||
#define PHY_ANEXP 0x06
|
||||
|
||||
#define PHY_ANAR_NEXTPAGE 0x8000
|
||||
#define PHY_ANAR_RSVD0 0x4000
|
||||
#define PHY_ANAR_TLRFLT 0x2000
|
||||
#define PHY_ANAR_RSVD1 0x1000
|
||||
#define PHY_ANAR_RSVD2 0x0800
|
||||
#define PHY_ANAR_RSVD3 0x0400
|
||||
#define PHY_ANAR_100BT4 0x0200
|
||||
#define PHY_ANAR_100BTXFULL 0x0100
|
||||
#define PHY_ANAR_100BTXHALF 0x0080
|
||||
#define PHY_ANAR_10BTFULL 0x0040
|
||||
#define PHY_ANAR_10BTHALF 0x0020
|
||||
#define PHY_ANAR_PROTO4 0x0010
|
||||
#define PHY_ANAR_PROTO3 0x0008
|
||||
#define PHY_ANAR_PROTO2 0x0004
|
||||
#define PHY_ANAR_PROTO1 0x0002
|
||||
#define PHY_ANAR_PROTO0 0x0001
|
||||
|
||||
/*
|
||||
* These are the register definitions for the PHY (physical layer
|
||||
* interface chip).
|
||||
*/
|
||||
/*
|
||||
* PHY BMCR Basic Mode Control Register
|
||||
*/
|
||||
#define PHY_BMCR_RESET 0x8000
|
||||
#define PHY_BMCR_LOOPBK 0x4000
|
||||
#define PHY_BMCR_SPEEDSEL 0x2000
|
||||
#define PHY_BMCR_AUTONEGENBL 0x1000
|
||||
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
|
||||
#define PHY_BMCR_ISOLATE 0x0400
|
||||
#define PHY_BMCR_AUTONEGRSTR 0x0200
|
||||
#define PHY_BMCR_DUPLEX 0x0100
|
||||
#define PHY_BMCR_COLLTEST 0x0080
|
||||
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
|
||||
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
|
||||
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
|
||||
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
|
||||
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
|
||||
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
|
||||
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
|
||||
/*
|
||||
* RESET: 1 == software reset, 0 == normal operation
|
||||
* Resets status and control registers to default values.
|
||||
* Relatches all hardware config values.
|
||||
*
|
||||
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
|
||||
*
|
||||
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
|
||||
* Link speed is selected byt his bit or if auto-negotiation if bit
|
||||
* 12 (AUTONEGENBL) is set (in which case the value of this register
|
||||
* is ignored).
|
||||
*
|
||||
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
|
||||
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
|
||||
* determine speed and mode. Should be cleared and then set if PHY configured
|
||||
* for no autoneg on startup.
|
||||
*
|
||||
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
|
||||
*
|
||||
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
|
||||
*
|
||||
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
|
||||
*
|
||||
* COLLTEST: 1 == collision test enabled, 0 == normal operation
|
||||
*/
|
||||
|
||||
/*
|
||||
* PHY, BMSR Basic Mode Status Register
|
||||
*/
|
||||
#define PHY_BMSR_100BT4 0x8000
|
||||
#define PHY_BMSR_100BTXFULL 0x4000
|
||||
#define PHY_BMSR_100BTXHALF 0x2000
|
||||
#define PHY_BMSR_10BTFULL 0x1000
|
||||
#define PHY_BMSR_10BTHALF 0x0800
|
||||
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
|
||||
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
|
||||
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
|
||||
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
|
||||
#define PHY_BMSR_MFPRESUP 0x0040
|
||||
#define PHY_BMSR_AUTONEGCOMP 0x0020
|
||||
#define PHY_BMSR_REMFAULT 0x0010
|
||||
#define PHY_BMSR_CANAUTONEG 0x0008
|
||||
#define PHY_BMSR_LINKSTAT 0x0004
|
||||
#define PHY_BMSR_JABBER 0x0002
|
||||
#define PHY_BMSR_EXTENDED 0x0001
|
||||
|
||||
#ifdef __alpha__
|
||||
#undef vtophys
|
||||
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user