Add support for Intel Stratix 10 platform.

Intel Stratix 10 SoC includes a quad-core arm64 cluster and FPGA fabric.

This adds support for reconfiguring FPGA.

Accessing FPGA core of this SoC require the level of privilege EL3,
while kernel runs in EL1 (lower) level of privilege.

This provides an Intel service layer interface that uses SMCCC to pass
queries to the secure-monitor (EL3).

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D21454

sys/arm64/conf/GENERIC

@@ -110,6 +110,7 @@ options 	SOC_ALLWINNER_A64
 options 	SOC_ALLWINNER_H5
 options 	SOC_CAVM_THUNDERX
 options 	SOC_HISI_HI6220
+options 	SOC_INTEL_STRATIX10
 options 	SOC_BRCM_BCM2837
 options 	SOC_MARVELL_8K
 options 	SOC_ROCKCHIP_RK3328

sys/arm64/intel/firmware.c

@@ -0,0 +1,122 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <dev/fdt/simplebus.h>
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+struct firmware_softc {
+	struct simplebus_softc	simplebus_sc;
+	device_t		dev;
+};
+
+static int
+firmware_probe(device_t dev)
+{
+	phandle_t node;
+
+	node = ofw_bus_get_node(dev);
+
+	/*
+	 * The firmware node has no property compatible.
+	 * Look for a known child.
+	 */
+	if (!fdt_depth_search_compatible(node, "intel,stratix10-svc", 0))
+		return (ENXIO);
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	device_set_desc(dev, "Firmware node");
+
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+firmware_attach(device_t dev)
+{
+	struct firmware_softc *sc;
+	phandle_t node;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	node = ofw_bus_get_node(dev);
+	if (node == -1)
+		return (ENXIO);
+
+	simplebus_init(dev, node);
+
+	/*
+	 * Allow devices to identify.
+	 */
+	bus_generic_probe(dev);
+
+	/*
+	 * Now walk the OFW tree and attach top-level devices.
+	 */
+	for (node = OF_child(node); node > 0; node = OF_peer(node))
+		simplebus_add_device(dev, node, 0, NULL, -1, NULL);
+
+	return (bus_generic_attach(dev));
+}
+
+static int
+firmware_detach(device_t dev)
+{
+
+	return (0);
+}
+
+static device_method_t firmware_methods[] = {
+	DEVMETHOD(device_probe,		firmware_probe),
+	DEVMETHOD(device_attach,	firmware_attach),
+	DEVMETHOD(device_detach,	firmware_detach),
+	DEVMETHOD_END
+};
+
+DEFINE_CLASS_1(firmware, firmware_driver, firmware_methods,
+    sizeof(struct firmware_softc), simplebus_driver);
+
+static devclass_t firmware_devclass;
+
+EARLY_DRIVER_MODULE(firmware, simplebus, firmware_driver, firmware_devclass,
+    0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
+MODULE_VERSION(firmware, 1);

sys/arm64/intel/intel-smc.h

@@ -0,0 +1,99 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_ARM64_INTEL_INTEL_SMC_H_
+#define	_ARM64_INTEL_INTEL_SMC_H_
+
+#include <dev/psci/smccc.h>
+
+/*
+ * Intel SiP return values.
+ */
+#define	INTEL_SIP_SMC_STATUS_OK				0
+#define	INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY		1
+#define	INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED	2
+#define	INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR		4
+#define	INTEL_SIP_SMC_REG_ERROR				5
+#define	INTEL_SIP_SMC_RSU_ERROR				7
+
+/*
+ * Intel SiP calls.
+ */
+#define	INTEL_SIP_SMC_STD_CALL(func)				\
+    SMCCC_FUNC_ID(SMCCC_YIELDING_CALL, SMCCC_64BIT_CALL,	\
+	SMCCC_SIP_SERVICE_CALLS, (func))
+#define	INTEL_SIP_SMC_FAST_CALL(func)				\
+    SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_64BIT_CALL,		\
+	SMCCC_SIP_SERVICE_CALLS, (func))
+
+#define	INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START			1
+#define	INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE			2
+#define	INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE	3
+#define	INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE			4
+#define	INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM		5
+#define	INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK		6
+#define	INTEL_SIP_SMC_FUNCID_REG_READ				7
+#define	INTEL_SIP_SMC_FUNCID_REG_WRITE				8
+#define	INTEL_SIP_SMC_FUNCID_REG_UPDATE				9
+#define	INTEL_SIP_SMC_FUNCID_RSU_STATUS				11
+#define	INTEL_SIP_SMC_FUNCID_RSU_UPDATE				12
+
+#define	INTEL_SIP_SMC_FPGA_CONFIG_START			\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
+#define	INTEL_SIP_SMC_FPGA_CONFIG_WRITE			\
+    INTEL_SIP_SMC_STD_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
+#define	INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE	\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
+#define	INTEL_SIP_SMC_FPGA_CONFIG_ISDONE		\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
+#define	INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM		\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
+#define	INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK		\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
+#define	INTEL_SIP_SMC_REG_READ				\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_REG_READ)
+#define	INTEL_SIP_SMC_REG_WRITE				\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
+#define	INTEL_SIP_SMC_REG_UPDATE			\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
+#define	INTEL_SIP_SMC_RSU_STATUS			\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
+#define	INTEL_SIP_SMC_RSU_UPDATE			\
+    INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
+
+typedef int (*intel_smc_callfn_t)(register_t, register_t, register_t,
+    register_t, register_t, register_t, register_t, register_t,
+    struct arm_smccc_res *res);
+
+#endif /* _ARM64_INTEL_INTEL_SMC_H_ */

sys/arm64/intel/stratix10-soc-fpga-mgr.c

@@ -0,0 +1,290 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Intel Stratix 10 FPGA Manager.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+#include <sys/conf.h>
+#include <sys/uio.h>
+#include <sys/sx.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <arm64/intel/stratix10-svc.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/intr.h>
+
+#define	SVC_BUF_SIZE	(2 * 1024 * 1024)
+
+struct fpgamgr_s10_softc {
+	struct cdev		*mgr_cdev;
+	struct cdev		*mgr_cdev_partial;
+	device_t		dev;
+	device_t		s10_svc_dev;
+	struct s10_svc_mem	mem;
+	struct sx		sx;
+	int			opened;
+};
+
+static int
+fpga_open(struct cdev *dev, int flags __unused,
+    int fmt __unused, struct thread *td __unused)
+{
+	struct fpgamgr_s10_softc *sc;
+	struct s10_svc_msg msg;
+	int ret;
+	int err;
+
+	sc = dev->si_drv1;
+
+	sx_xlock(&sc->sx);
+	if (sc->opened) {
+		sx_xunlock(&sc->sx);
+		return (EBUSY);
+	}
+
+	err = s10_svc_allocate_memory(sc->s10_svc_dev,
+	    &sc->mem, SVC_BUF_SIZE);
+	if (err != 0) {
+		sx_xunlock(&sc->sx);
+		return (ENXIO);
+	}
+
+	bzero(&msg, sizeof(struct s10_svc_msg));
+	msg.command = COMMAND_RECONFIG;
+	if (dev == sc->mgr_cdev_partial)
+		msg.flags |= COMMAND_RECONFIG_FLAG_PARTIAL;
+	ret = s10_svc_send(sc->s10_svc_dev, &msg);
+	if (ret != 0) {
+		sx_xunlock(&sc->sx);
+		return (ENXIO);
+	}
+
+	sc->opened = 1;
+	sx_xunlock(&sc->sx);
+
+	return (0);
+}
+
+static int
+fpga_write(struct cdev *dev, struct uio *uio, int ioflag)
+{
+	struct fpgamgr_s10_softc *sc;
+	vm_offset_t addr;
+	int amnt;
+
+	sc = dev->si_drv1;
+
+	sx_xlock(&sc->sx);
+	if (sc->opened == 0) {
+		/* Device closed. */
+		sx_xunlock(&sc->sx);
+		return (ENXIO);
+	}
+
+	while (uio->uio_resid > 0) {
+		addr = sc->mem.vaddr + sc->mem.fill;
+		if (sc->mem.fill >= SVC_BUF_SIZE)
+			return (ENOMEM);
+		amnt = MIN(uio->uio_resid, (SVC_BUF_SIZE - sc->mem.fill));
+		uiomove((void *)addr, amnt, uio);
+		sc->mem.fill += amnt;
+	}
+
+	sx_xunlock(&sc->sx);
+
+	return (0);
+}
+
+static int
+fpga_close(struct cdev *dev, int flags __unused,
+    int fmt __unused, struct thread *td __unused)
+{
+	struct fpgamgr_s10_softc *sc;
+	struct s10_svc_msg msg;
+	int ret;
+
+	sc = dev->si_drv1;
+
+	sx_xlock(&sc->sx);
+	if (sc->opened == 0) {
+		/* Device closed. */
+		sx_xunlock(&sc->sx);
+		return (ENXIO);
+	}
+
+	/* Submit bitstream */
+	bzero(&msg, sizeof(struct s10_svc_msg));
+	msg.command = COMMAND_RECONFIG_DATA_SUBMIT;
+	msg.payload = (void *)sc->mem.paddr;
+	msg.payload_length = sc->mem.fill;
+	ret = s10_svc_send(sc->s10_svc_dev, &msg);
+	if (ret != 0) {
+		device_printf(sc->dev, "Failed to submit data\n");
+		s10_svc_free_memory(sc->s10_svc_dev, &sc->mem);
+		sc->opened = 0;
+		sx_xunlock(&sc->sx);
+		return (0);
+	}
+
+	/* Claim memory buffer back */
+	bzero(&msg, sizeof(struct s10_svc_msg));
+	msg.command = COMMAND_RECONFIG_DATA_CLAIM;
+	s10_svc_send(sc->s10_svc_dev, &msg);
+
+	s10_svc_free_memory(sc->s10_svc_dev, &sc->mem);
+	sc->opened = 0;
+	sx_xunlock(&sc->sx);
+
+	return (0);
+}
+
+static int
+fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags,
+    struct thread *td)
+{
+
+	return (0);
+}
+
+static struct cdevsw fpga_cdevsw = {
+	.d_version =	D_VERSION,
+	.d_open =	fpga_open,
+	.d_close =	fpga_close,
+	.d_write =	fpga_write,
+	.d_ioctl =	fpga_ioctl,
+	.d_name =	"FPGA Manager",
+};
+
+static int
+fpgamgr_s10_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "intel,stratix10-soc-fpga-mgr"))
+		return (ENXIO);
+
+	device_set_desc(dev, "Stratix 10 SOC FPGA Manager");
+
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+fpgamgr_s10_attach(device_t dev)
+{
+	struct fpgamgr_s10_softc *sc;
+	devclass_t dc;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	dc = devclass_find("s10_svc");
+	if (dc == NULL)
+		return (ENXIO);
+
+	sc->s10_svc_dev = devclass_get_device(dc, 0);
+	if (sc->s10_svc_dev == NULL)
+		return (ENXIO);
+
+	sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,
+	    0600, "fpga%d", device_get_unit(sc->dev));
+	if (sc->mgr_cdev == NULL) {
+		device_printf(dev, "Failed to create character device.\n");
+		return (ENXIO);
+	}
+
+	sc->mgr_cdev_partial = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,
+	    0600, "fpga_partial%d", device_get_unit(sc->dev));
+	if (sc->mgr_cdev_partial == NULL) {
+		device_printf(dev, "Failed to create character device.\n");
+		return (ENXIO);
+	}
+
+	sx_init(&sc->sx, "s10 fpga");
+
+	sc->mgr_cdev->si_drv1 = sc;
+	sc->mgr_cdev_partial->si_drv1 = sc;
+
+	return (0);
+}
+
+static int
+fpgamgr_s10_detach(device_t dev)
+{
+	struct fpgamgr_s10_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	destroy_dev(sc->mgr_cdev);
+	destroy_dev(sc->mgr_cdev_partial);
+
+	sx_destroy(&sc->sx);
+
+	return (0);
+}
+
+static device_method_t fpgamgr_s10_methods[] = {
+	DEVMETHOD(device_probe,		fpgamgr_s10_probe),
+	DEVMETHOD(device_attach,	fpgamgr_s10_attach),
+	DEVMETHOD(device_detach,	fpgamgr_s10_detach),
+	{ 0, 0 }
+};
+
+static driver_t fpgamgr_s10_driver = {
+	"fpgamgr_s10",
+	fpgamgr_s10_methods,
+	sizeof(struct fpgamgr_s10_softc),
+};
+
+static devclass_t fpgamgr_s10_devclass;
+
+DRIVER_MODULE(fpgamgr_s10, simplebus, fpgamgr_s10_driver,
+    fpgamgr_s10_devclass, 0, 0);

sys/arm64/intel/stratix10-svc.c

@@ -0,0 +1,271 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Intel Stratix 10 Service Layer
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/timeet.h>
+#include <sys/timetc.h>
+#include <sys/conf.h>
+#include <sys/uio.h>
+#include <sys/vmem.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <dev/fdt/simplebus.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <arm64/intel/intel-smc.h>
+#include <arm64/intel/stratix10-svc.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/intr.h>
+
+struct s10_svc_softc {
+	device_t		dev;
+	vmem_t			*vmem;
+	intel_smc_callfn_t	callfn;
+};
+
+static int
+s10_data_claim(struct s10_svc_softc *sc)
+{
+	struct arm_smccc_res res;
+	register_t a0, a1, a2;
+	int ret;
+
+	ret = 0;
+
+	while (1) {
+		a0 = INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE;
+		a1 = 0;
+		a2 = 0;
+
+		ret = sc->callfn(a0, a1, a2, 0, 0, 0, 0, 0, &res);
+		if (ret == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY)
+			continue;
+
+		break;
+	}
+
+	return (ret);
+}
+
+int
+s10_svc_send(device_t dev, struct s10_svc_msg *msg)
+{
+	struct s10_svc_softc *sc;
+	struct arm_smccc_res res;
+	register_t a0, a1, a2;
+	int ret;
+
+	sc = device_get_softc(dev);
+
+	a0 = 0;
+	a1 = 0;
+	a2 = 0;
+
+	switch (msg->command) {
+	case COMMAND_RECONFIG:
+		a0 = INTEL_SIP_SMC_FPGA_CONFIG_START;
+		a1 = msg->flags;
+		break;
+	case COMMAND_RECONFIG_DATA_SUBMIT:
+		a0 = INTEL_SIP_SMC_FPGA_CONFIG_WRITE;
+		a1 = (uint64_t)msg->payload;
+		a2 = (uint64_t)msg->payload_length;
+		break;
+	case COMMAND_RECONFIG_DATA_CLAIM:
+		ret = s10_data_claim(sc);
+		return (ret);
+	default:
+		return (-1);
+	}
+
+	ret = sc->callfn(a0, a1, a2, 0, 0, 0, 0, 0, &res);
+
+	return (ret);
+}
+
+int
+s10_svc_allocate_memory(device_t dev, struct s10_svc_mem *mem, int size)
+{
+	struct s10_svc_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	if (size <= 0)
+		return (EINVAL);
+
+	if (vmem_alloc(sc->vmem, size,
+	    M_FIRSTFIT | M_NOWAIT, &mem->paddr)) {
+		device_printf(dev, "Can't allocate memory\n");
+		return (ENOMEM);
+	}
+
+	mem->size = size;
+	mem->fill = 0;
+	mem->vaddr = (vm_offset_t)pmap_mapdev(mem->paddr, mem->size);
+
+	return (0);
+}
+
+void
+s10_svc_free_memory(device_t dev, struct s10_svc_mem *mem)
+{
+	struct s10_svc_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	vmem_free(sc->vmem, mem->paddr, mem->size);
+}
+
+static int
+s10_get_memory(struct s10_svc_softc *sc)
+{
+	struct arm_smccc_res res;
+	vmem_addr_t addr;
+	vmem_size_t size;
+	vmem_t *vmem;
+
+	sc->callfn(INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM,
+	    0, 0, 0, 0, 0, 0, 0, &res);
+	if (res.a0 != INTEL_SIP_SMC_STATUS_OK)
+		return (ENXIO);
+
+	vmem = vmem_create("stratix10 vmem", 0, 0, PAGE_SIZE,
+	    PAGE_SIZE, M_BESTFIT | M_WAITOK);
+	if (vmem == NULL)
+		return (ENXIO);
+
+	addr = res.a1;
+	size = res.a2;
+
+	device_printf(sc->dev, "Shared memory address 0x%lx size 0x%lx\n",
+	    addr, size);
+
+	vmem_add(vmem, addr, size, 0);
+
+	sc->vmem = vmem;
+
+	return (0);
+}
+
+static intel_smc_callfn_t
+s10_svc_get_callfn(struct s10_svc_softc *sc, phandle_t node)
+{
+	char method[16];
+
+	if ((OF_getprop(node, "method", method, sizeof(method))) > 0) {
+		if (strcmp(method, "hvc") == 0)
+			return (arm_smccc_hvc);
+		else if (strcmp(method, "smc") == 0)
+			return (arm_smccc_smc);
+		else
+			device_printf(sc->dev,
+			    "Invalid method \"%s\"\n", method);
+	} else
+		device_printf(sc->dev, "SMC method not provided\n");
+
+	return (NULL);
+}
+
+static int
+s10_svc_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "intel,stratix10-svc"))
+		return (ENXIO);
+
+	device_set_desc(dev, "Stratix 10 SVC");
+
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+s10_svc_attach(device_t dev)
+{
+	struct s10_svc_softc *sc;
+	phandle_t node;
+
+	node = ofw_bus_get_node(dev);
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	if (device_get_unit(dev) != 0)
+		return (ENXIO);
+
+	sc->callfn = s10_svc_get_callfn(sc, node);
+	if (sc->callfn == NULL)
+		return (ENXIO);
+
+	if (s10_get_memory(sc) != 0)
+		return (ENXIO);
+
+	return (0);
+}
+
+static device_method_t s10_svc_methods[] = {
+	DEVMETHOD(device_probe,		s10_svc_probe),
+	DEVMETHOD(device_attach,	s10_svc_attach),
+	{ 0, 0 }
+};
+
+static driver_t s10_svc_driver = {
+	"s10_svc",
+	s10_svc_methods,
+	sizeof(struct s10_svc_softc),
+};
+
+static devclass_t s10_svc_devclass;
+
+EARLY_DRIVER_MODULE(s10_svc, firmware, s10_svc_driver,
+    s10_svc_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);

sys/arm64/intel/stratix10-svc.h

@@ -0,0 +1,60 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory (Department of Computer Science and
+ * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
+ * DARPA SSITH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _ARM64_INTEL_STRATIX10_SVC_H_
+#define	_ARM64_INTEL_STRATIX10_SVC_H_
+
+struct s10_svc_msg {
+	int command;
+#define	COMMAND_RECONFIG		(1 << 0)
+#define	COMMAND_RECONFIG_DATA_SUBMIT	(1 << 1)
+#define	COMMAND_RECONFIG_DATA_CLAIM	(1 << 2)
+	int flags;
+#define	COMMAND_RECONFIG_FLAG_PARTIAL	(1 << 0)
+	void *payload;
+	int payload_length;
+};
+
+struct s10_svc_mem {
+	vm_offset_t paddr;
+	vm_offset_t vaddr;
+	int size;
+	int fill;
+};
+
+int s10_svc_send(device_t dev, struct s10_svc_msg *msg);
+int s10_svc_allocate_memory(device_t dev, struct s10_svc_mem *mem, int size);
+void s10_svc_free_memory(device_t dev, struct s10_svc_mem *mem);
+
+#endif	/* !_ARM64_INTEL_STRATIX10_SVC_H_ */

sys/conf/files.arm64

@@ -174,6 +174,9 @@ arm64/coresight/coresight-dynamic-replicator.c	standard
 arm64/coresight/coresight-etm4x.c		standard
 arm64/coresight/coresight-funnel.c		standard
 arm64/coresight/coresight-tmc.c			standard
+arm64/intel/firmware.c				optional soc_intel_stratix10
+arm64/intel/stratix10-soc-fpga-mgr.c		optional soc_intel_stratix10
+arm64/intel/stratix10-svc.c			optional soc_intel_stratix10
 arm64/qualcomm/qcom_gcc.c			optional qcom_gcc fdt
 contrib/vchiq/interface/compat/vchi_bsd.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"

sys/conf/options.arm64

@@ -19,6 +19,7 @@ SOC_ALLWINNER_H5		opt_soc.h
 SOC_BRCM_BCM2837		opt_soc.h
 SOC_CAVM_THUNDERX		opt_soc.h
 SOC_HISI_HI6220			opt_soc.h
+SOC_INTEL_STRATIX10		opt_soc.h
 SOC_MARVELL_8K			opt_soc.h
 SOC_ROCKCHIP_RK3328		opt_soc.h
 SOC_ROCKCHIP_RK3399		opt_soc.h