Merge i.MX and PowerPC SDHCI drivers
Summary: i.MX5 and PowerPC use a very similar eSDHC controller, which is also similar to the uSDHC controller used by i.MX6. The imx_sdhci driver works almost completely with PowerPC, with some minor tweaks. There is one caveat with this: reset currently does not work on PowerPC, so has been #ifdef'd out until this can be tracked down and fixed. If resets are done the controller will timeout all data transactions. Without a reset, it appears to work just fine. This is part 3, following up r308186 and r308187. Test Plan: This has been tested on a PowerPC QorIQ P1022 board. It has not been tested on i.MX, but no regressions are expected. Reviewed By: imp Differential Revision: https://reviews.freebsd.org/D8407
This commit is contained in:
Justin Hibbits
parent
2b96b955e9
commit
eecaab5275
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=308188
@ -63,6 +63,7 @@ dev/ofw/ofw_subr.c optional aim powerpc
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dev/powermac_nvram/powermac_nvram.c optional powermac_nvram powermac
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dev/quicc/quicc_bfe_fdt.c optional quicc mpc85xx
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dev/scc/scc_bfe_macio.c optional scc powermac
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dev/sdhci/fsl_sdhci.c optional mpc85xx sdhci
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dev/sec/sec.c optional sec mpc85xx
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dev/sound/macio/aoa.c optional snd_davbus | snd_ai2s powermac
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dev/sound/macio/davbus.c optional snd_davbus powermac
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@ -137,7 +138,6 @@ powerpc/mpc85xx/atpic.c optional mpc85xx isa
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powerpc/mpc85xx/ds1553_bus_fdt.c optional ds1553 fdt
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powerpc/mpc85xx/ds1553_core.c optional ds1553
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powerpc/mpc85xx/fsl_diu.c optional mpc85xx diu
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powerpc/mpc85xx/fsl_sdhc.c optional mpc85xx sdhc
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powerpc/mpc85xx/i2c.c optional iicbus fdt
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powerpc/mpc85xx/isa.c optional mpc85xx isa
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powerpc/mpc85xx/lbc.c optional mpc85xx
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@ -28,7 +28,7 @@
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__FBSDID("$FreeBSD$");
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/*
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* SDHCI driver glue for Freescale i.MX SoC family.
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* SDHCI driver glue for Freescale i.MX SoC and QorIQ families.
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*
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* This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
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*/
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@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <sys/callout.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/libkern.h>
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#include <sys/lock.h>
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@ -52,9 +53,11 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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#include <machine/resource.h>
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#ifdef __arm__
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#include <machine/intr.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#endif
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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@ -146,7 +149,6 @@ struct fsl_sdhci_softc {
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#define SDHC_PROT_CDSS (1 << 7)
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#define SDHC_SYS_CTRL 0x2c
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#define SDHC_INT_STATUS 0x30
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/*
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* The clock enable bits exist in different registers for ESDHC vs USDHC, but
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@ -169,6 +171,7 @@ static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6sl-usdhc", HWTYPE_USDHC},
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{"fsl,imx53-esdhc", HWTYPE_ESDHC},
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{"fsl,imx51-esdhc", HWTYPE_ESDHC},
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{"fsl,esdhc", HWTYPE_ESDHC},
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{NULL, HWTYPE_NONE},
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};
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@ -397,6 +400,11 @@ fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t
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if (off == SDHCI_POWER_CONTROL) {
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return;
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}
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#ifdef __powerpc__
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/* XXX Reset doesn't seem to work as expected. Do nothing for now. */
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if (off == SDHCI_SOFTWARE_RESET)
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return;
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#endif
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val32 = RD4(sc, off & ~3);
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val32 &= ~(0xff << (off & 3) * 8);
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@ -531,17 +539,20 @@ fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc)
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val |= SDHCI_CLOCK_INT_STABLE;
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/*
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* On ESDHC hardware the card bus clock enable is in the usual sdhci
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* register but it's a different bit, so transcribe it (note the
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* On i.MX ESDHC hardware the card bus clock enable is in the usual
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* sdhci register but it's a different bit, so transcribe it (note the
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* difference between standard SDHCI_ and Freescale SDHC_ prefixes
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* here). On USDHC hardware there is a force-on bit, but no force-off
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* for the card bus clock (the hardware runs the clock when transfers
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* are active no matter what), so we always say the clock is on.
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* here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but
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* no force-off for the card bus clock (the hardware runs the clock when
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* transfers are active no matter what), so we always say the clock is
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* on.
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* XXX Maybe we should say it's in whatever state the sdhci driver last
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* set it to.
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*/
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if (sc->hwtype == HWTYPE_ESDHC) {
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#ifdef __arm__
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if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN)
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#endif
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val |= SDHCI_CLOCK_CARD_EN;
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} else {
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val |= SDHCI_CLOCK_CARD_EN;
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@ -565,15 +576,18 @@ fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
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sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK;
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if (sc->hwtype == HWTYPE_ESDHC) {
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/*
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* The ESDHC hardware requires the driver to manually start and
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* stop the sd bus clock. If the enable bit is not set, turn
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* off the clock in hardware and we're done, otherwise decode
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* the requested frequency. ESDHC hardware is sdhci 2.0; the
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* sdhci driver will use the original 8-bit divisor field and
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* the "base / 2^N" divisor scheme.
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* The i.MX5 ESDHC hardware requires the driver to manually
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* start and stop the sd bus clock. If the enable bit is not
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* set, turn off the clock in hardware and we're done, otherwise
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* decode the requested frequency. ESDHC hardware is sdhci 2.0;
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* the sdhci driver will use the original 8-bit divisor field
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* and the "base / 2^N" divisor scheme.
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*/
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if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
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#ifdef __arm__
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/* On QorIQ, this is a reserved bit. */
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WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN);
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#endif
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return;
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}
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@ -625,6 +639,7 @@ fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
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val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK);
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val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;
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val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;
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val32 |= SDHC_CLK_IPGEN;
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WR4(sc, SDHCI_CLOCK_CONTROL, val32);
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}
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@ -710,10 +725,10 @@ fsl_sdhci_intr(void *arg)
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*/
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switch (sc->r1bfix_type) {
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case R1BFIX_NODATA:
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intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_RESPONSE;
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intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE;
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break;
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case R1BFIX_AC12:
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intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_DATA_END;
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intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END;
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break;
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default:
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intmask = 0;
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@ -722,8 +737,8 @@ fsl_sdhci_intr(void *arg)
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if (intmask) {
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sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
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if (!fsl_sdhci_r1bfix_is_wait_done(sc)) {
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WR4(sc, SDHC_INT_STATUS, intmask);
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bus_barrier(sc->mem_res, SDHC_INT_STATUS, 4,
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WR4(sc, SDHCI_INT_STATUS, intmask);
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bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4,
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BUS_SPACE_BARRIER_WRITE);
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}
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}
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@ -735,10 +750,54 @@ fsl_sdhci_intr(void *arg)
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static int
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fsl_sdhci_get_ro(device_t bus, device_t child)
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{
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struct fsl_sdhci_softc *sc = device_get_softc(bus);
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return (false);
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if (RD4(sc, SDHCI_PRESENT_STATE) & SDHC_PRES_WPSPL)
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return (false);
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return (true);
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}
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#ifdef __powerpc__
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static uint32_t
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fsl_sdhci_get_platform_clock(device_t dev)
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{
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device_t parent;
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phandle_t node;
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uint32_t clock;
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node = ofw_bus_get_node(dev);
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/* Get sdhci node properties */
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if((OF_getprop(node, "clock-frequency", (void *)&clock,
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sizeof(clock)) <= 0) || (clock == 0)) {
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/*
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* Trying to get clock from parent device (soc) if correct
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* clock cannot be acquired from sdhci node.
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*/
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parent = device_get_parent(dev);
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node = ofw_bus_get_node(parent);
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/* Get soc properties */
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if ((OF_getprop(node, "bus-frequency", (void *)&clock,
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sizeof(clock)) <= 0) || (clock == 0)) {
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device_printf(dev,"Cannot acquire correct sdhci "
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"frequency from DTS.\n");
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return (0);
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}
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/* eSDHC clock is 1/2 platform clock. */
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clock /= 2;
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}
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if (bootverbose)
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device_printf(dev, "Acquired clock: %d from DTS\n", clock);
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return (clock);
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}
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#endif
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static int
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fsl_sdhci_detach(device_t dev)
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{
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@ -752,6 +811,7 @@ fsl_sdhci_attach(device_t dev)
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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int rid, err;
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phandle_t node;
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uint32_t protctl;
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sc->dev = dev;
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@ -807,9 +867,23 @@ fsl_sdhci_attach(device_t dev)
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*
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* XXX need named constants for this stuff.
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*/
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WR4(sc, SDHC_WTMK_LVL, 0x08800880);
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#ifdef __powerpc__
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/* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */
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if ((SVR_VER(mfspr(SPR_SVR)) & 0xfff6) == SVR_P1022 )
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WR4(sc, SDHC_WTMK_LVL, 0x10801080);
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else
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#endif
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WR4(sc, SDHC_WTMK_LVL, 0x08800880);
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/*
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* We read in native byte order in the main driver, but the register
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* defaults to little endian.
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*/
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#ifdef __powerpc__
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sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev);
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#else
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sc->baseclk_hz = imx_ccm_sdhci_hz();
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#endif
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sc->slot.max_clk = sc->baseclk_hz;
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/*
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@ -830,6 +904,16 @@ fsl_sdhci_attach(device_t dev)
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/* XXX put real gpio hookup here. */
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sc->force_card_present = true;
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}
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#ifdef __powerpc__
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/* Default to big-endian on powerpc */
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protctl = RD4(sc, SDHC_PROT_CTRL);
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protctl &= ~SDHC_PROT_EMODE_MASK;
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if (OF_hasprop(node, "little-endian"))
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protctl |= SDHC_PROT_EMODE_LITTLE;
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else
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protctl |= SDHC_PROT_EMODE_BIG;
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WR4(sc, SDHC_PROT_CTRL, protctl);
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#endif
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callout_init(&sc->r1bfix_callout, 1);
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sdhci_init_slot(dev, &sc->slot, 0);
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File diff suppressed because it is too large
Load Diff
@ -1,297 +0,0 @@
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/*-
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* Copyright (c) 2011-2012 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef FSL_SDHC_H_
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#define FSL_SDHC_H_
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcreg.h>
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#include <dev/mmc/mmcvar.h>
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#include <dev/mmc/mmcbrvar.h>
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#include "mmcbr_if.h"
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/*****************************************************************************
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* Private defines
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*****************************************************************************/
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struct slot {
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uint32_t clock;
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};
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struct fsl_sdhc_softc {
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device_t self;
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device_t child;
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bus_space_handle_t bsh;
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bus_space_tag_t bst;
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struct resource *mem_resource;
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int mem_rid;
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struct resource *irq_resource;
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int irq_rid;
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void *ihl;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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uint32_t* dma_mem;
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bus_addr_t dma_phys;
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struct mtx mtx;
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struct task card_detect_task;
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struct callout card_detect_callout;
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struct mmc_host mmc_host;
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struct slot slot;
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uint32_t bus_busy;
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uint32_t platform_clock;
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struct mmc_request *request;
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int data_done;
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int command_done;
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int use_dma;
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uint32_t* data_ptr;
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uint32_t data_offset;
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};
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#define FSL_SDHC_RESET_DELAY 50
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#define FSL_SDHC_BASE_CLOCK_DIV (2)
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#define FSL_SDHC_MAX_DIV (FSL_SDHC_BASE_CLOCK_DIV * 256 * 16)
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#define FSL_SDHC_MIN_DIV (FSL_SDHC_BASE_CLOCK_DIV * 2)
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#define FSL_SDHC_MAX_CLOCK (50000000)
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#define FSL_SDHC_MAX_BLOCK_COUNT (65535)
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#define FSL_SDHC_MAX_BLOCK_SIZE (4096)
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#define FSL_SDHC_FIFO_BUF_SIZE (64) /* Water-mark level. */
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#define FSL_SDHC_FIFO_BUF_WORDS (FSL_SDHC_FIFO_BUF_SIZE / 4)
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#define FSL_SDHC_DMA_SEGMENT_SIZE (1024)
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#define FSL_SDHC_DMA_ALIGNMENT (4)
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#define FSL_SDHC_DMA_BLOCK_SIZE FSL_SDHC_MAX_BLOCK_SIZE
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/*
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* Offsets of SD HC registers
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*/
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enum sdhc_reg_off {
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SDHC_DSADDR = 0x000,
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SDHC_BLKATTR = 0x004,
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SDHC_CMDARG = 0x008,
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SDHC_XFERTYP = 0x00c,
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SDHC_CMDRSP0 = 0x010,
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SDHC_CMDRSP1 = 0x014,
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SDHC_CMDRSP2 = 0x018,
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SDHC_CMDRSP3 = 0x01c,
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SDHC_DATPORT = 0x020,
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SDHC_PRSSTAT = 0x024,
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SDHC_PROCTL = 0x028,
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SDHC_SYSCTL = 0x02c,
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SDHC_IRQSTAT = 0x030,
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SDHC_IRQSTATEN = 0x034,
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SDHC_IRQSIGEN = 0x038,
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SDHC_AUTOC12ERR = 0x03c,
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SDHC_HOSTCAPBLT = 0x040,
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SDHC_WML = 0x044,
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SDHC_FEVT = 0x050,
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SDHC_HOSTVER = 0x0fc,
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SDHC_DCR = 0x40c
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};
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enum sysctl_bit {
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SYSCTL_INITA = 0x08000000,
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SYSCTL_RSTD = 0x04000000,
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SYSCTL_RSTC = 0x02000000,
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SYSCTL_RSTA = 0x01000000,
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SYSCTL_DTOCV = 0x000f0000,
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SYSCTL_SDCLKFS = 0x0000ff00,
|
||||
SYSCTL_DVS = 0x000000f0,
|
||||
SYSCTL_PEREN = 0x00000004,
|
||||
SYSCTL_HCKEN = 0x00000002,
|
||||
SYSCTL_IPGEN = 0x00000001
|
||||
};
|
||||
|
||||
#define HEX_LEFT_SHIFT(x) (4 * x)
|
||||
enum sysctl_shift {
|
||||
SHIFT_DTOCV = HEX_LEFT_SHIFT(4),
|
||||
SHIFT_SDCLKFS = HEX_LEFT_SHIFT(2),
|
||||
SHIFT_DVS = HEX_LEFT_SHIFT(1)
|
||||
};
|
||||
|
||||
enum proctl_bit {
|
||||
PROCTL_WECRM = 0x04000000,
|
||||
PROCTL_WECINS = 0x02000000,
|
||||
PROCTL_WECINT = 0x01000000,
|
||||
PROCTL_RWCTL = 0x00040000,
|
||||
PROCTL_CREQ = 0x00020000,
|
||||
PROCTL_SABGREQ = 0x00010000,
|
||||
PROCTL_CDSS = 0x00000080,
|
||||
PROCTL_CDTL = 0x00000040,
|
||||
PROCTL_EMODE = 0x00000030,
|
||||
PROCTL_D3CD = 0x00000008,
|
||||
PROCTL_DTW = 0x00000006
|
||||
};
|
||||
|
||||
enum dtw {
|
||||
DTW_1 = 0x00000000,
|
||||
DTW_4 = 0x00000002,
|
||||
DTW_8 = 0x00000004
|
||||
};
|
||||
|
||||
enum prsstat_bit {
|
||||
PRSSTAT_DLSL = 0xff000000,
|
||||
PRSSTAT_CLSL = 0x00800000,
|
||||
PRSSTAT_WPSPL = 0x00080000,
|
||||
PRSSTAT_CDPL = 0x00040000,
|
||||
PRSSTAT_CINS = 0x00010000,
|
||||
PRSSTAT_BREN = 0x00000800,
|
||||
PRSSTAT_BWEN = 0x00000400,
|
||||
PRSSTAT_RTA = 0x00000200,
|
||||
PRSSTAT_WTA = 0x00000100,
|
||||
PRSSTAT_SDOFF = 0x00000080,
|
||||
PRSSTAT_PEROFF = 0x00000040,
|
||||
PRSSTAT_HCKOFF = 0x00000020,
|
||||
PRSSTAT_IPGOFF = 0x00000010,
|
||||
PRSSTAT_DLA = 0x00000004,
|
||||
PRSSTAT_CDIHB = 0x00000002,
|
||||
PRSSTAT_CIHB = 0x00000001
|
||||
|
||||
};
|
||||
|
||||
enum irq_bits {
|
||||
IRQ_DMAE = 0x10000000,
|
||||
IRQ_AC12E = 0x01000000,
|
||||
IRQ_DEBE = 0x00400000,
|
||||
IRQ_DCE = 0x00200000,
|
||||
IRQ_DTOE = 0x00100000,
|
||||
IRQ_CIE = 0x00080000,
|
||||
IRQ_CEBE = 0x00040000,
|
||||
IRQ_CCE = 0x00020000,
|
||||
IRQ_CTOE = 0x00010000,
|
||||
IRQ_CINT = 0x00000100,
|
||||
IRQ_CRM = 0x00000080,
|
||||
IRQ_CINS = 0x00000040,
|
||||
IRQ_BRR = 0x00000020,
|
||||
IRQ_BWR = 0x00000010,
|
||||
IRQ_DINT = 0x00000008,
|
||||
IRQ_BGE = 0x00000004,
|
||||
IRQ_TC = 0x00000002,
|
||||
IRQ_CC = 0x00000001
|
||||
};
|
||||
|
||||
enum irq_masks {
|
||||
IRQ_ERROR_DATA_MASK = IRQ_DMAE | IRQ_DEBE | IRQ_DCE | IRQ_DTOE,
|
||||
IRQ_ERROR_CMD_MASK = IRQ_AC12E | IRQ_CIE | IRQ_CTOE | IRQ_CCE |
|
||||
IRQ_CEBE
|
||||
};
|
||||
|
||||
enum dcr_bits {
|
||||
DCR_PRI = 0x0000c000,
|
||||
DCR_SNOOP = 0x00000040,
|
||||
DCR_AHB2MAG_BYPASS = 0x00000020,
|
||||
DCR_RD_SAFE = 0x00000004,
|
||||
DCR_RD_PFE = 0x00000002,
|
||||
DCR_RD_PF_SIZE = 0x00000001
|
||||
};
|
||||
|
||||
#define DCR_PRI_SHIFT (14)
|
||||
|
||||
enum xfertyp_bits {
|
||||
XFERTYP_CMDINX = 0x3f000000,
|
||||
XFERTYP_CMDTYP = 0x00c00000,
|
||||
XFERTYP_DPSEL = 0x00200000,
|
||||
XFERTYP_CICEN = 0x00100000,
|
||||
XFERTYP_CCCEN = 0x00080000,
|
||||
XFERTYP_RSPTYP = 0x00030000,
|
||||
XFERTYP_MSBSEL = 0x00000020,
|
||||
XFERTYP_DTDSEL = 0x00000010,
|
||||
XFERTYP_AC12EN = 0x00000004,
|
||||
XFERTYP_BCEN = 0x00000002,
|
||||
XFERTYP_DMAEN = 0x00000001
|
||||
};
|
||||
|
||||
#define CMDINX_SHIFT (24)
|
||||
|
||||
enum xfertyp_cmdtyp {
|
||||
CMDTYP_NORMAL = 0x00000000,
|
||||
CMDYTP_SUSPEND = 0x00400000,
|
||||
CMDTYP_RESUME = 0x00800000,
|
||||
CMDTYP_ABORT = 0x00c00000
|
||||
};
|
||||
|
||||
enum xfertyp_rsptyp {
|
||||
RSPTYP_NONE = 0x00000000,
|
||||
RSPTYP_136 = 0x00010000,
|
||||
RSPTYP_48 = 0x00020000,
|
||||
RSPTYP_48_BUSY = 0x00030000
|
||||
};
|
||||
|
||||
enum blkattr_bits {
|
||||
BLKATTR_BLKSZE = 0x00001fff,
|
||||
BLKATTR_BLKCNT = 0xffff0000
|
||||
};
|
||||
#define BLKATTR_BLOCK_COUNT(x) (x << 16)
|
||||
|
||||
enum wml_bits {
|
||||
WR_WML = 0x00ff0000,
|
||||
RD_WML = 0x000000ff,
|
||||
};
|
||||
|
||||
enum sdhc_bit_mask {
|
||||
MASK_CLOCK_CONTROL = 0x0000ffff,
|
||||
MASK_IRQ_ALL = IRQ_DMAE | IRQ_AC12E | IRQ_DEBE | IRQ_DCE |
|
||||
IRQ_DTOE | IRQ_CIE | IRQ_CEBE | IRQ_CCE |
|
||||
IRQ_CTOE | IRQ_CINT | IRQ_CRM | IRQ_CINS |
|
||||
IRQ_BRR | IRQ_BWR | IRQ_DINT | IRQ_BGE |
|
||||
IRQ_TC | IRQ_CC,
|
||||
};
|
||||
|
||||
enum sdhc_line {
|
||||
SDHC_DAT_LINE = 0x2,
|
||||
SDHC_CMD_LINE = 0x1
|
||||
};
|
||||
|
||||
#endif /* FSL_SDHC_H_ */
|
||||
Loading…
Reference in New Issue
Block a user