Fix an issue with multicast hash filters on Amlogic and Allwinner boards.
For DWC_GMAC_ALT_DESC implementations, the multicast hash table has only 64 entries. Instead of 8 registers starting at 0x500, a pair of registers at 0x08 and 0x0c are used instead. Approved by: re (hrs) Submitted by: Guy Yur <guyyur@gmail.com>
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=301841
@ -587,14 +587,13 @@ dwc_setup_rxfilter(struct dwc_softc *sc)
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struct ifmultiaddr *ifma;
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struct ifnet *ifp;
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uint8_t *eaddr, val;
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uint32_t crc, ffval, hashbit, hashreg, hi, lo, hash[8], hmask;
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uint32_t crc, ffval, hashbit, hashreg, hi, lo, hash[8];
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int nhash, i;
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DWC_ASSERT_LOCKED(sc);
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ifp = sc->ifp;
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nhash = sc->mactype == DWC_GMAC_ALT_DESC ? 2 : 8;
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hmask = ((nhash << 5) - 1) | 0xf;
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/*
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* Set the multicast (group) filter hash.
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@ -615,11 +614,10 @@ dwc_setup_rxfilter(struct dwc_softc *sc)
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ifma->ifma_addr), ETHER_ADDR_LEN);
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/* Take lower 8 bits and reverse it */
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val = bitreverse(~crc & 0xff) & hmask;
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val = bitreverse(~crc & 0xff);
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if (sc->mactype == DWC_GMAC_ALT_DESC)
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hashreg = (val >> 5) == 0;
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else
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hashreg = (val >> 5);
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val >>= nhash; /* Only need lower 6 bits */
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hashreg = (val >> 5);
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hashbit = (val & 31);
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hash[hashreg] |= (1 << hashbit);
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}
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@ -642,8 +640,13 @@ dwc_setup_rxfilter(struct dwc_softc *sc)
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WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
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WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
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WRITE4(sc, MAC_FRAME_FILTER, ffval);
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for (i = 0; i < nhash; i++)
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WRITE4(sc, HASH_TABLE_REG(i), hash[i]);
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if (sc->mactype == DWC_GMAC_ALT_DESC) {
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WRITE4(sc, GMAC_MAC_HTLOW, hash[0]);
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WRITE4(sc, GMAC_MAC_HTHIGH, hash[1]);
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} else {
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for (i = 0; i < nhash; i++)
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WRITE4(sc, HASH_TABLE_REG(i), hash[i]);
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}
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}
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static int
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@ -53,6 +53,8 @@
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#define FRAME_FILTER_HMC (1 << 2)
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#define FRAME_FILTER_HUC (1 << 1)
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#define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
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#define GMAC_MAC_HTHIGH 0x08
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#define GMAC_MAC_HTLOW 0x0c
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#define GMII_ADDRESS 0x10
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#define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
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#define GMII_ADDRESS_PA_SHIFT 11
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