Use the VM_MEMATTR macros to describe the MAIR offsets.
Remove the duplicate macros that defined a subset of the VM_MEMATTR values. While here use VM_MEMATTR macros when filling in the MAIR register. Reviewed by: alc, markj Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D22241
This commit is contained in:
Andrew Turner
parent
9e387c3da2
commit
ef3e1e13b6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=355213
@ -34,6 +34,7 @@
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#include <machine/hypervisor.h>
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#include <machine/param.h>
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#include <machine/pte.h>
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#include <machine/vm.h>
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#include <machine/vmparam.h>
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#define VIRT_BITS 48
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@ -42,10 +43,6 @@
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.globl kernbase
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.set kernbase, KERNBASE
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#define DEVICE_MEM 0
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#define NORMAL_UNCACHED 1
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#define NORMAL_MEM 2
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/*
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* We assume:
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* MMU on with an identity map, or off
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@ -396,7 +393,7 @@ create_pagetables:
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/* Create the kernel space L2 table */
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mov x6, x26
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mov x7, #NORMAL_MEM
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mov x7, #VM_MEMATTR_WRITE_BACK
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mov x8, #(KERNBASE & L2_BLOCK_MASK)
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mov x9, x28
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bl build_l2_block_pagetable
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@ -433,15 +430,17 @@ create_pagetables:
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mov x6, x27 /* The initial page table */
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#if defined(SOCDEV_PA) && defined(SOCDEV_VA)
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/* Create a table for the UART */
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mov x7, #(ATTR_nG | ATTR_IDX(DEVICE_MEM))
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mov x7, #(ATTR_nG | ATTR_IDX(VM_MEMATTR_DEVICE))
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mov x8, #(SOCDEV_VA) /* VA start */
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mov x9, #(SOCDEV_PA) /* PA start */
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mov x10, #1
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bl build_l1_block_pagetable
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#endif
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/* Create the VA = PA map */
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mov x7, #(ATTR_nG | ATTR_IDX(NORMAL_UNCACHED))
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/*
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* Create the VA = PA map
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*/
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mov x7, #(ATTR_nG | ATTR_IDX(VM_MEMATTR_UNCACHEABLE))
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mov x9, x27
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mov x8, x9 /* VA start (== PA start) */
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mov x10, #1
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@ -658,10 +657,10 @@ start_mmu:
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.align 3
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mair:
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.quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, 0) | \
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MAIR_ATTR(MAIR_NORMAL_NC, 1) | \
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MAIR_ATTR(MAIR_NORMAL_WB, 2) | \
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MAIR_ATTR(MAIR_NORMAL_WT, 3)
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.quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) | \
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MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \
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MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \
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MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH)
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tcr:
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.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \
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TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
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@ -169,14 +169,6 @@ __FBSDID("$FreeBSD$");
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#define PMAP_INLINE
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#endif
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/*
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* These are configured by the mair_el1 register. This is set up in locore.S
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*/
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#define DEVICE_MEMORY 0
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#define UNCACHED_MEMORY 1
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#define CACHED_MEMORY 2
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#ifdef PV_STATS
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#define PV_STAT(x) do { x ; } while (0)
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#else
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@ -707,7 +699,7 @@ pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
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KASSERT(l2_slot != 0, ("..."));
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pmap_store(&l2[l2_slot],
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(pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
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ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
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ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
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}
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KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
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("..."));
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@ -719,7 +711,7 @@ pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
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l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
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pmap_store(&pagetable_dmap[l1_slot],
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(pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
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ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
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ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
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}
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/* Create L2 mappings at the end of the region */
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@ -744,7 +736,7 @@ pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
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l2_slot = pmap_l2_index(va);
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pmap_store(&l2[l2_slot],
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(pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
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ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
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ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
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}
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}
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@ -1268,7 +1260,7 @@ void
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pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
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{
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pmap_kenter(sva, size, pa, DEVICE_MEMORY);
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pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
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}
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/*
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@ -3275,7 +3267,8 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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L3_PAGE);
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if ((prot & VM_PROT_WRITE) == 0)
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new_l3 |= ATTR_AP(ATTR_AP_RO);
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if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
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if ((prot & VM_PROT_EXECUTE) == 0 ||
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m->md.pv_memattr == VM_MEMATTR_DEVICE)
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new_l3 |= ATTR_XN;
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if ((flags & PMAP_ENTER_WIRED) != 0)
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new_l3 |= ATTR_SW_WIRED;
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@ -3543,7 +3536,8 @@ pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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new_l2 |= ATTR_SW_MANAGED;
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new_l2 &= ~ATTR_AF;
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}
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if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
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if ((prot & VM_PROT_EXECUTE) == 0 ||
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m->md.pv_memattr == VM_MEMATTR_DEVICE)
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new_l2 |= ATTR_XN;
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if (va < VM_MAXUSER_ADDRESS)
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new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
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@ -3845,7 +3839,8 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
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pa = VM_PAGE_TO_PHYS(m);
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l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
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ATTR_AP(ATTR_AP_RO) | L3_PAGE;
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if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
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if ((prot & VM_PROT_EXECUTE) == 0 ||
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m->md.pv_memattr == VM_MEMATTR_DEVICE)
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l3_val |= ATTR_XN;
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if (va < VM_MAXUSER_ADDRESS)
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l3_val |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
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@ -5223,7 +5218,7 @@ pmap_mapbios(vm_paddr_t pa, vm_size_t size)
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l2 = pmap_l1_to_l2(pde, va);
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pmap_load_store(l2,
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pa | ATTR_DEFAULT | ATTR_XN |
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ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
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ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
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va += L2_SIZE;
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pa += L2_SIZE;
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@ -5247,7 +5242,7 @@ pmap_mapbios(vm_paddr_t pa, vm_size_t size)
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/* L3 table is linked */
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va = trunc_page(va);
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pa = trunc_page(pa);
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pmap_kenter(va, size, pa, CACHED_MEMORY);
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pmap_kenter(va, size, pa, VM_MEMATTR_WRITE_BACK);
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}
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return ((void *)(va + offset));
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@ -5433,7 +5428,7 @@ pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
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l3 = pmap_load(pte);
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l3 &= ~ATTR_IDX_MASK;
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l3 |= ATTR_IDX(mode);
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if (mode == DEVICE_MEMORY)
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if (mode == VM_MEMATTR_DEVICE)
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l3 |= ATTR_XN;
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pmap_update_entry(kernel_pmap, pte, l3, tmpva,
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@ -5509,7 +5504,8 @@ pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
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if (tmpl1 != 0) {
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pmap_kenter(tmpl1, PAGE_SIZE,
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DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
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DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
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VM_MEMATTR_WRITE_BACK);
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l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
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}
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@ -5651,7 +5647,8 @@ pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
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*/
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if (tmpl2 != 0) {
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pmap_kenter(tmpl2, PAGE_SIZE,
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DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
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DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
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VM_MEMATTR_WRITE_BACK);
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l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
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}
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