diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 0369e9efff7f..68b1ca5ea5b3 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -634,7 +634,6 @@ MLINKS+=fd.4 stderr.4 \ fd.4 stdout.4 MLINKS+=fdt.4 FDT.4 MLINKS+=firewire.4 ieee1394.4 -MLINKS+=fpa.4 fea.4 MLINKS+=fwe.4 if_fwe.4 MLINKS+=fwip.4 if_fwip.4 MLINKS+=fxp.4 if_fxp.4 diff --git a/share/man/man4/fpa.4 b/share/man/man4/fpa.4 index 097442998e8c..5a4d2bffcfaa 100644 --- a/share/man/man4/fpa.4 +++ b/share/man/man4/fpa.4 @@ -4,16 +4,14 @@ .\" .\" $FreeBSD$ .\" -.Dd March 13, 1995 +.Dd February 15, 2017 .Dt FPA 4 .Os .Sh NAME -.Nm fpa , -.Nm fea +.Nm fpa .Nd device drivers for DEC FDDI controllers .Sh SYNOPSIS .Cd "device fpa" -.Cd "device fea" .Pp .Fx only: @@ -21,25 +19,9 @@ only: .Sh DESCRIPTION The .Nm -and -.Nm fea -device drivers provide support for the DEC DEFPA PCI FDDI Controller and -the DEC DEFEA EISA FDDI Controller, respectively. -All variants of either +device driver provide support for the DEC DEFPA PCI FDDI Controller. +All variants of the controller are supported including the DAS and SAS configurations. -.Sh DIAGNOSTICS -.Bl -diag -.It "fea%d: error: desired IRQ of %d does not match device's actual IRQ (%d)" -The device probe detected that the DEFEA board is configured for a different -interrupt than the one specified in the kernel configuration file. -.It "fea%d: error: memory not enabled! ECU reconfiguration required" -The device probe found that no device memory had been configured on the -DEFEA. -Although the DEFEA can be configured with no device memory, this driver -requires a minimum of 1K device memory to be set up. -The ECU (EISA Configuration -Utility) will need to be run to change the settings. -.El .Sh SEE ALSO .Xr arp 4 , .Xr netintro 4 , @@ -47,9 +29,7 @@ Utility) will need to be run to change the settings. .Sh AUTHORS The .Nm -and -.Nm fea -device drivers and this manual page were written by +device driver and this manual page were written by .An Matt Thomas . .Sh CAVEATS Normally, the device driver will not enable the reception of SMT frames. diff --git a/sys/conf/NOTES b/sys/conf/NOTES index 4e1210897a37..fbfb04299a9f 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -1974,7 +1974,6 @@ device xmphy # XaQti XMAC II # ex: Intel EtherExpress Pro/10 and other i82595-based adapters, # Olicom Ethernet PC Card devices. # fe: Fujitsu MB86960A/MB86965A Ethernet -# fea: DEC DEFEA EISA FDDI adapter # fpa: Support for the Digital DEFPA PCI FDDI. `device fddi' is also needed. # fxp: Intel EtherExpress Pro/100B # (hint of prefer_iomap can be done to prefer I/O instead of Mem mapping) @@ -2087,7 +2086,6 @@ device ex device fe hint.fe.0.at="isa" hint.fe.0.port="0x300" -device fea device sn hint.sn.0.at="isa" hint.sn.0.port="0x300" diff --git a/sys/conf/files b/sys/conf/files index 6270a9bb5f6c..d307eb758877 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -2409,10 +2409,9 @@ dev/pci/pcib_if.m standard dev/pci/pcib_support.c standard dev/pci/vga_pci.c optional pci dev/pcn/if_pcn.c optional pcn pci -dev/pdq/if_fea.c optional fea eisa dev/pdq/if_fpa.c optional fpa pci -dev/pdq/pdq.c optional nowerror fea eisa | fpa pci -dev/pdq/pdq_ifsubr.c optional nowerror fea eisa | fpa pci +dev/pdq/pdq.c optional nowerror fpa pci +dev/pdq/pdq_ifsubr.c optional nowerror fpa pci dev/pms/freebsd/driver/ini/src/agtiapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sadisc.c optional pmspcv \ diff --git a/sys/dev/pdq/if_fea.c b/sys/dev/pdq/if_fea.c deleted file mode 100644 index 73c6caeebdad..000000000000 --- a/sys/dev/pdq/if_fea.c +++ /dev/null @@ -1,286 +0,0 @@ -/*- - * Copyright (c) 1995, 1996 Matt Thomas - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* - * DEC PDQ FDDI Controller - * - * This module support the DEFEA EISA FDDI Controller. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include - -static void pdq_eisa_subprobe (pdq_bus_t, u_int32_t, u_int32_t *, u_int32_t *, u_int32_t *); -static void pdq_eisa_devinit (pdq_softc_t *); -static const char * pdq_eisa_match (eisa_id_t); - -static int pdq_eisa_probe (device_t); -static int pdq_eisa_attach (device_t); -static int pdq_eisa_detach (device_t); -static int pdq_eisa_shutdown (device_t); -static void pdq_eisa_ifintr (void *); - -#define DEFEA_IRQS 0x0000FBA9U - -#define DEFEA_INTRENABLE 0x8 /* level interrupt */ -#define DEFEA_DECODE_IRQ(n) ((DEFEA_IRQS >> ((n) << 2)) & 0x0f) - -#define EISA_DEVICE_ID_DEC_DEC3001 0x10a33001 -#define EISA_DEVICE_ID_DEC_DEC3002 0x10a33002 -#define EISA_DEVICE_ID_DEC_DEC3003 0x10a33003 -#define EISA_DEVICE_ID_DEC_DEC3004 0x10a33004 - -static void -pdq_eisa_subprobe(bc, iobase, maddr, msize, irq) - pdq_bus_t bc; - u_int32_t iobase; - u_int32_t *maddr; - u_int32_t *msize; - u_int32_t *irq; -{ - if (irq != NULL) - *irq = DEFEA_DECODE_IRQ(PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_IO_CONFIG_STAT_0) & 3); - *maddr = (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_CMP_0) << 8) - | (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_CMP_1) << 16); - *msize = (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_MASK_0) + 4) << 8; - - return; -} - -static void -pdq_eisa_devinit (sc) - pdq_softc_t *sc; -{ - pdq_uint8_t data; - - /* - * Do the standard initialization for the DEFEA registers. - */ - PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_FUNCTION_CTRL, 0x23); - PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CMP_1_1, (sc->io_bsh >> 8) & 0xF0); - PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CMP_0_1, (sc->io_bsh >> 8) & 0xF0); - PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_SLOT_CTRL, 0x01); - data = PDQ_OS_IORD_8(sc->io_bst, sc->io_bsh, PDQ_EISA_BURST_HOLDOFF); -#if defined(PDQ_IOMAPPED) - PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_BURST_HOLDOFF, data & ~1); -#else - PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_BURST_HOLDOFF, data | 1); -#endif - data = PDQ_OS_IORD_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CONFIG_STAT_0); - PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CONFIG_STAT_0, data | DEFEA_INTRENABLE); - - return; -} - -static const char * -pdq_eisa_match (type) - eisa_id_t type; -{ - switch (type) { - case EISA_DEVICE_ID_DEC_DEC3001: - case EISA_DEVICE_ID_DEC_DEC3002: - case EISA_DEVICE_ID_DEC_DEC3003: - case EISA_DEVICE_ID_DEC_DEC3004: - return ("DEC FDDIcontroller/EISA Adapter"); - break; - default: - break; - } - return (NULL); -} - -static int -pdq_eisa_probe (dev) - device_t dev; -{ - const char *desc; - u_int32_t iobase; - u_int32_t irq; - u_int32_t maddr; - u_int32_t msize; - - u_int32_t eisa_id = eisa_get_id(dev); - - desc = pdq_eisa_match(eisa_id); - if (!desc) { - return (ENXIO); - } - - device_set_desc(dev, desc); - - iobase = eisa_get_slot(dev) * EISA_SLOT_SIZE; - pdq_eisa_subprobe((pdq_bus_t)SYS_RES_IOPORT, iobase, &maddr, &msize, &irq); - - eisa_add_iospace(dev, iobase, 0x200, RESVADDR_NONE); - eisa_add_mspace(dev, maddr, msize, RESVADDR_NONE); - eisa_add_intr(dev, irq, EISA_TRIGGER_LEVEL); - - return (0); -} - -static void -pdq_eisa_ifintr(arg) - void * arg; -{ - pdq_softc_t * sc; - - sc = arg; - - PDQ_LOCK(sc); - (void) pdq_interrupt(sc->sc_pdq); - PDQ_LOCK(sc); - - return; -} - -static int -pdq_eisa_attach (dev) - device_t dev; -{ - pdq_softc_t * sc; - int error; - - sc = device_get_softc(dev); - - sc->dev = dev; - - sc->io_rid = 0; - sc->io_type = SYS_RES_IOPORT; - sc->io = bus_alloc_resource_any(dev, sc->io_type, &sc->io_rid, - RF_ACTIVE); - if (!sc->io) { - device_printf(dev, "Unable to allocate I/O space resource.\n"); - error = ENXIO; - goto bad; - } - sc->io_bsh = rman_get_bushandle(sc->io); - sc->io_bst = rman_get_bustag(sc->io); - - sc->mem_rid = 0; - sc->mem_type = SYS_RES_MEMORY; - sc->mem = bus_alloc_resource_any(dev, sc->mem_type, &sc->mem_rid, - RF_ACTIVE); - if (!sc->mem) { - device_printf(dev, "Unable to allocate memory resource.\n"); - error = ENXIO; - goto bad; - } - sc->mem_bsh = rman_get_bushandle(sc->mem); - sc->mem_bst = rman_get_bustag(sc->mem); - - sc->irq_rid = 0; - sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, - RF_SHAREABLE | RF_ACTIVE); - if (!sc->irq) { - device_printf(dev, "Unable to allocate interrupt resource.\n"); - error = ENXIO; - goto bad; - } - - pdq_eisa_devinit(sc); - error = pdq_ifattach(sc, sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, - PDQ_DEFEA); - if (error) - goto bad; - - error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, - NULL, pdq_eisa_ifintr, sc, &sc->irq_ih); - if (error) { - device_printf(dev, "Failed to setup interrupt handler.\n"); - pdq_ifdetach(sc); - return (error); - } - - return (0); -bad: - pdq_free(dev); - return (error); -} - -static int -pdq_eisa_detach (dev) - device_t dev; -{ - pdq_softc_t * sc; - - sc = device_get_softc(dev); - pdq_ifdetach(sc); - - return (0); -} - -static int -pdq_eisa_shutdown(dev) - device_t dev; -{ - pdq_softc_t * sc; - - sc = device_get_softc(dev); - PDQ_LOCK(sc); - pdq_hwreset(sc->sc_pdq); - PDQ_UNLOCK(sc); - - return (0); -} - -static device_method_t pdq_eisa_methods[] = { - DEVMETHOD(device_probe, pdq_eisa_probe), - DEVMETHOD(device_attach, pdq_eisa_attach), - DEVMETHOD(device_attach, pdq_eisa_detach), - DEVMETHOD(device_shutdown, pdq_eisa_shutdown), - - { 0, 0 } -}; - -static driver_t pdq_eisa_driver = { - "fea", - pdq_eisa_methods, - sizeof(pdq_softc_t), -}; - -DRIVER_MODULE(fea, eisa, pdq_eisa_driver, pdq_devclass, 0, 0); -/* MODULE_DEPEND(fea, eisa, 1, 1, 1); */ -MODULE_DEPEND(fea, fddi, 1, 1, 1); diff --git a/sys/dev/pdq/pdq.c b/sys/dev/pdq/pdq.c index 00add2cbc2ff..9bb86ce6c3dd 100644 --- a/sys/dev/pdq/pdq.c +++ b/sys/dev/pdq/pdq.c @@ -163,10 +163,6 @@ static const char * const * const pdq_pmd_types[] = { static const char * const pdq_descriptions[] = { "DEFPA PCI", - "DEFEA EISA", - "DEFTA TC", - "DEFAA Futurebus", - "DEFQA Q-bus", }; static void @@ -1088,8 +1084,7 @@ pdq_hwreset( state = PDQ_PSTS_ADAPTER_STATE(PDQ_CSR_READ(csrs, csr_port_status)); if (state == PDQS_DMA_UNAVAILABLE) return; - PDQ_CSR_WRITE(csrs, csr_port_data_a, - (state == PDQS_HALTED && pdq->pdq_type != PDQ_DEFTA) ? 0 : PDQ_PRESET_SKIP_SELFTEST); + PDQ_CSR_WRITE(csrs, csr_port_data_a, PDQ_PRESET_SKIP_SELFTEST); PDQ_CSR_WRITE(csrs, csr_port_reset, 1); PDQ_OS_USEC_DELAY(100); PDQ_CSR_WRITE(csrs, csr_port_reset, 0); @@ -1164,13 +1159,11 @@ pdq_stop( pdq_read_fwrev(&pdq->pdq_csrs, &pdq->pdq_fwrev); pdq->pdq_chip_rev = pdq_read_chiprev(&pdq->pdq_csrs); - if (pdq->pdq_type == PDQ_DEFPA) { - /* - * Disable interrupts and DMA. - */ - PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, 0); - PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x10); - } + /* + * Disable interrupts and DMA. + */ + PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, 0); + PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x10); /* * Flush all the databuf queues. @@ -1229,27 +1222,21 @@ pdq_stop( * Allow the DEFPA to do DMA. Then program the physical * addresses of the consumer and descriptor blocks. */ - if (pdq->pdq_type == PDQ_DEFPA) { #ifdef PDQTEST - PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, - PDQ_PFI_MODE_DMA_ENABLE); + PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, + PDQ_PFI_MODE_DMA_ENABLE); #else - PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, - PDQ_PFI_MODE_DMA_ENABLE - /*|PDQ_PFI_MODE_PFI_PCI_INTR*/|PDQ_PFI_MODE_PDQ_PCI_INTR); + PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, + PDQ_PFI_MODE_DMA_ENABLE + /*|PDQ_PFI_MODE_PFI_PCI_INTR*/|PDQ_PFI_MODE_PDQ_PCI_INTR); #endif - } /* * Make sure the unsolicited queue has events ... */ pdq_process_unsolicited_events(pdq); - if ((pdq->pdq_type == PDQ_DEFEA && pdq->pdq_chip_rev == PDQ_CHIP_REV_E) - || pdq->pdq_type == PDQ_DEFTA) - PDQ_CSR_WRITE(csrs, csr_port_data_b, PDQ_DMA_BURST_16LW); - else - PDQ_CSR_WRITE(csrs, csr_port_data_b, PDQ_DMA_BURST_8LW); + PDQ_CSR_WRITE(csrs, csr_port_data_b, PDQ_DMA_BURST_8LW); PDQ_CSR_WRITE(csrs, csr_port_data_a, PDQ_SUB_CMD_DMA_BURST_SIZE_SET); pdq_do_port_control(csrs, PDQ_PCTL_SUB_CMD); @@ -1408,8 +1395,7 @@ pdq_interrupt( pdq_uint32_t data; int progress = 0; - if (pdq->pdq_type == PDQ_DEFPA) - PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18); + PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18); while ((data = PDQ_CSR_READ(csrs, csr_port_status)) & PDQ_PSTS_INTR_PENDING) { progress = 1; @@ -1454,7 +1440,7 @@ pdq_interrupt( pdq_halt_code_t halt_code = PDQ_PSTS_HALT_ID(PDQ_CSR_READ(csrs, csr_port_status)); printf(": halt code = %d (%s)\n", halt_code, pdq_halt_codes[halt_code]); - if (halt_code == PDQH_DMA_ERROR && pdq->pdq_type == PDQ_DEFPA) { + if (halt_code == PDQH_DMA_ERROR) { PDQ_PRINTF(("\tPFI status = 0x%x, Host 0 Fatal Interrupt = 0x%x\n", PDQ_CSR_READ(&pdq->pdq_pci_csrs, csr_pfi_status), data & PDQ_HOST_INT_FATAL_ERROR)); @@ -1503,8 +1489,7 @@ pdq_interrupt( PDQ_CSR_WRITE(csrs, csr_host_int_type_0, PDQ_HOST_INT_XMT_DATA_FLUSH); } } - if (pdq->pdq_type == PDQ_DEFPA) - PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18); + PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18); } return progress; } @@ -1639,9 +1624,8 @@ pdq_initialize( * Initialize the CSR references. * the DEFAA (FutureBus+) skips a longword between registers */ - pdq_init_csrs(&pdq->pdq_csrs, bus, csr_base, pdq->pdq_type == PDQ_DEFAA ? 2 : 1); - if (pdq->pdq_type == PDQ_DEFPA) - pdq_init_pci_csrs(&pdq->pdq_pci_csrs, bus, csr_base, 1); + pdq_init_csrs(&pdq->pdq_csrs, bus, csr_base, 1); + pdq_init_pci_csrs(&pdq->pdq_pci_csrs, bus, csr_base, 1); PDQ_PRINTF(("PDQ CSRs: BASE = " PDQ_OS_CSR_FMT "\n", pdq->pdq_csrs.csr_base)); PDQ_PRINTF((" Port Reset = " PDQ_OS_CSR_FMT " [0x%08x]\n", @@ -1774,7 +1758,7 @@ pdq_initialize( if (state == PDQS_HALTED) { pdq_halt_code_t halt_code = PDQ_PSTS_HALT_ID(PDQ_CSR_READ(&pdq->pdq_csrs, csr_port_status)); printf("Halt code = %d (%s)\n", halt_code, pdq_halt_codes[halt_code]); - if (halt_code == PDQH_DMA_ERROR && pdq->pdq_type == PDQ_DEFPA) + if (halt_code == PDQH_DMA_ERROR) PDQ_PRINTF(("PFI status = 0x%x, Host 0 Fatal Interrupt = 0x%x\n", PDQ_CSR_READ(&pdq->pdq_pci_csrs, csr_pfi_status), PDQ_CSR_READ(&pdq->pdq_csrs, csr_host_int_type_0) & PDQ_HOST_INT_FATAL_ERROR)); diff --git a/sys/dev/pdq/pdq_freebsd.h b/sys/dev/pdq/pdq_freebsd.h index a556b36afffb..a378e05d4e5a 100644 --- a/sys/dev/pdq/pdq_freebsd.h +++ b/sys/dev/pdq/pdq_freebsd.h @@ -86,10 +86,6 @@ extern devclass_t pdq_devclass; enum _pdq_type_t { PDQ_DEFPA, /* PCI-bus */ - PDQ_DEFEA, /* EISA-bus */ - PDQ_DEFTA, /* TurboChannel */ - PDQ_DEFAA, /* FutureBus+ */ - PDQ_DEFQA /* Q-bus */ }; #define sc_ifmedia ifmedia diff --git a/sys/dev/pdq/pdq_ifsubr.c b/sys/dev/pdq/pdq_ifsubr.c index f8df3a7b2b76..ed724df50309 100644 --- a/sys/dev/pdq/pdq_ifsubr.c +++ b/sys/dev/pdq/pdq_ifsubr.c @@ -459,6 +459,8 @@ pdq_ifattach(pdq_softc_t *sc, const pdq_uint8_t *llc, pdq_type_t type) { struct ifnet *ifp; + KASSERT(type == PDQ_DEFPA, ("We only support PCI attachment.")); + ifp = PDQ_IFNET(sc) = if_alloc(IFT_FDDI); if (ifp == NULL) { device_printf(sc->dev, "can not if_alloc()\n"); diff --git a/sys/dev/pdq/pdqreg.h b/sys/dev/pdq/pdqreg.h index a4dea690b154..1d2a15882fef 100644 --- a/sys/dev/pdq/pdqreg.h +++ b/sys/dev/pdq/pdqreg.h @@ -127,52 +127,6 @@ struct _pdq_pci_csrs_t { #define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */ #define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */ -#define PDQ_EISA_BURST_HOLDOFF 0x0040 -#define PDQ_EISA_SLOT_ID 0x0C80 -#define PDQ_EISA_SLOT_CTRL 0x0C84 -#define PDQ_EISA_MEM_ADD_CMP_0 0x0C85 -#define PDQ_EISA_MEM_ADD_CMP_1 0x0C86 -#define PDQ_EISA_MEM_ADD_CMP_2 0x0C87 -#define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88 -#define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89 -#define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A -#define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B -#define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C -#define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D -#define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E -#define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F -#define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90 -#define PDQ_EISA_IO_CMP_0_0 0x0C91 -#define PDQ_EISA_IO_CMP_0_1 0x0C92 -#define PDQ_EISA_IO_CMP_1_0 0x0C93 -#define PDQ_EISA_IO_CMP_1_1 0x0C94 -#define PDQ_EISA_IO_CMP_2_0 0x0C95 -#define PDQ_EISA_IO_CMP_2_1 0x0C96 -#define PDQ_EISA_IO_CMP_3_0 0x0C97 -#define PDQ_EISA_IO_CMP_3_1 0x0C98 -#define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99 -#define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A -#define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B -#define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C -#define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D -#define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E -#define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F -#define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0 -#define PDQ_EISA_MOD_CONFIG_1 0x0CA1 -#define PDQ_EISA_MOD_CONFIG_2 0x0CA2 -#define PDQ_EISA_MOD_CONFIG_3 0x0CA3 -#define PDQ_EISA_MOD_CONFIG_4 0x0CA4 -#define PDQ_EISA_MOD_CONFIG_5 0x0CA5 -#define PDQ_EISA_MOD_CONFIG_6 0x0CA6 -#define PDQ_EISA_MOD_CONFIG_7 0x0CA7 -#define PDQ_EISA_DIP_SWITCH 0x0CA8 -#define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9 -#define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA -#define PDQ_EISA_DMA_CONFIG 0x0CAB -#define PDQ_EISA_INPUT_PORT 0x0CAC -#define PDQ_EISA_OUTPUT_PORT 0x0CAD -#define PDQ_EISA_FUNCTION_CTRL 0x0CAE - #define PDQ_TC_CSR_OFFSET 0x00100000 #define PDQ_TC_CSR_SPACE 0x0040 #define PDQ_FBUS_CSR_OFFSET 0x00200000 diff --git a/sys/dev/pdq/pdqvar.h b/sys/dev/pdq/pdqvar.h index db532732f27a..a84c00bc6624 100644 --- a/sys/dev/pdq/pdqvar.h +++ b/sys/dev/pdq/pdqvar.h @@ -53,10 +53,6 @@ typedef enum _pdq_state_t pdq_state_t; enum _pdq_type_t { PDQ_DEFPA, /* PCI-bus */ - PDQ_DEFEA, /* EISA-bus */ - PDQ_DEFTA, /* TurboChannel */ - PDQ_DEFAA, /* FutureBus+ */ - PDQ_DEFQA /* Q-bus */ }; #if defined(PDQTEST)