Warns fixing. Protect against inappropriate linting, and mark
GCC-specific assemble code as such (in #ifdefs). Fix an easy static variable warning while I'm here.
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1d6911d10f
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=114291
@ -705,9 +705,12 @@ void
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panicifcpuunsupported(void)
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{
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#if !defined(lint)
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#if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
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#error This kernel is not configured for one of the supported CPUs
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#endif
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#else /* lint */
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#endif /* lint */
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#if defined(I386_CPU) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU))
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#error I386_CPU is mutually exclusive with the other cpu types.
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#endif
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@ -746,6 +749,7 @@ static volatile u_int trap_by_rdmsr;
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* be advanced.
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*/
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inthand_t bluetrap6;
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#ifdef __GNUC__
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__asm
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(" \
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.text; \
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@ -757,12 +761,14 @@ __asm
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addl $2, (%esp); /* rdmsr is a 2-byte instruction */ \
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iret \
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");
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#endif
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/*
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* Special exception 13 handler.
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* Accessing non-existent MSR generates general protection fault.
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*/
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inthand_t bluetrap13;
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#ifdef __GNUC__
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__asm
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(" \
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.text; \
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@ -775,6 +781,7 @@ __asm
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addl $2, (%esp); /* rdmsr is a 2-bytes instruction. */ \
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iret; \
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");
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#endif
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/*
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* Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
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@ -1100,7 +1107,7 @@ union msrinfo {
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u_int32_t regs[2];
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};
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u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
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static u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
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/* MSR low, MSR high, flags bit0 */
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{ 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
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{ 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
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@ -705,9 +705,12 @@ void
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panicifcpuunsupported(void)
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{
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#if !defined(lint)
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#if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
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#error This kernel is not configured for one of the supported CPUs
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#endif
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#else /* lint */
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#endif /* lint */
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#if defined(I386_CPU) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU))
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#error I386_CPU is mutually exclusive with the other cpu types.
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#endif
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@ -746,6 +749,7 @@ static volatile u_int trap_by_rdmsr;
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* be advanced.
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*/
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inthand_t bluetrap6;
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#ifdef __GNUC__
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__asm
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(" \
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.text; \
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@ -757,12 +761,14 @@ __asm
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addl $2, (%esp); /* rdmsr is a 2-byte instruction */ \
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iret \
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");
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#endif
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/*
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* Special exception 13 handler.
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* Accessing non-existent MSR generates general protection fault.
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*/
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inthand_t bluetrap13;
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#ifdef __GNUC__
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__asm
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(" \
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.text; \
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@ -775,6 +781,7 @@ __asm
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addl $2, (%esp); /* rdmsr is a 2-bytes instruction. */ \
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iret; \
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");
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#endif
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/*
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* Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
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@ -1100,7 +1107,7 @@ union msrinfo {
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u_int32_t regs[2];
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};
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u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
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static u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
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/* MSR low, MSR high, flags bit0 */
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{ 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
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{ 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
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