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acpi_cpu: fixup for PIIX4E PCI config related to C2

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This is triggered only if BIOS configures ACPI_BITREG_BUS_MASTER_RLD
aka BRLD_EN_BM to 1.
Rationale:
1. we do not support C3 on PIIX4E
2. bus master activity need not break out of C2 state
3. because of CPU_QUIRK_NO_BM_CTRL quirk we may reset bus master
   status which would result in immediate break out from C2

So if you have seen
cpu0: too many short sleeps, backing off to C1
with this chipset before you may want to try cx_lowest of C2 again.

Reviewed by: rpaulo (mentor), njl
Approved by: rpaulo (mentor)
This commit is contained in:
Andriy Gapon 2009-02-19 14:39:52 +00:00
parent 72735687b3
commit f1e1ddc3d9
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=188814
1 changed files with 11 additions and 1 deletions
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12
sys/dev/acpica/acpi_cpu.c
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@ -1082,6 +1082,10 @@ acpi_cpu_quirks(void)
*
* Also, make sure that all interrupts cause a "Stop Break"
* event to exit from C2 state.
* Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
* should be set to zero, otherwise it causes C2 to short-sleep.
* PIIX4 doesn't properly support C3 and bus master activity
* need not break out of C2.
*/
case PCI_REVISION_A_STEP:
case PCI_REVISION_B_STEP:
@ -1094,10 +1098,16 @@ acpi_cpu_quirks(void)
val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"PIIX4: enabling IRQs to generate Stop Break\n"));
"acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
val |= PIIX4_STOP_BREAK_MASK;
pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
}
AcpiGetRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
if (val) {
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
}
break;
default:
break;