Fixed brokeness in the support of the 83C790/Elite Ultra (now that I
finally have the f**king documentation!): 1) Changed all the numeric register offsets to symbolic ones (it should have been this way originally). 2) If 16 bit, disable the shared memory when not using it. Apparantly switching between 8/16bit mode makes the Ultra unhappy unless this is done (i.e. it trashes the bus).
This commit is contained in:
dg
parent
a493330292
commit
f1e9ab81ed
@ -16,7 +16,7 @@
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*/
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/*
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* $Id: if_ed.c,v 1.34 1994/03/01 12:23:33 davidg Exp $
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* $Id: if_ed.c,v 1.35 1994/03/02 05:50:01 davidg Exp $
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*/
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#include "ed.h"
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@ -414,14 +414,15 @@ ed_probe_WD80x3(isa_dev)
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* Assemble together the encoded interrupt number.
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*/
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iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
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((inb(isa_dev->id_iobase + ED_WD_IRR) &
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(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
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((inb(isa_dev->id_iobase + ED_WD_IRR) &
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(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
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/*
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* Translate it using translation table, and check for correctness.
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*/
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if (ed_intr_mask[iptr] != isa_dev->id_irq) {
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printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1,
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ffs(ed_intr_mask[iptr]) - 1);
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return(0);
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}
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/*
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@ -431,17 +432,25 @@ ed_probe_WD80x3(isa_dev)
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inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
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}
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if (sc->is790) {
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outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
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iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
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((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
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outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
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outb(isa_dev->id_iobase + ED_WD790_HWR,
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inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
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iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
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(inb(isa_dev->id_iobase + ED_WD790_GCR) &
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(ED_WD790_GCR_IR1|ED_WD790_GCR_IR0)) >> 2);
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outb(isa_dev->id_iobase + ED_WD790_HWR,
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inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
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if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
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printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1,
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ffs(ed_790_intr_mask[iptr]) - 1, iptr);
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return 0;
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}
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outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
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/*
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* Enable interrupts.
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*/
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outb(isa_dev->id_iobase + ED_WD790_ICR,
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inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
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}
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sc->isa16bit = isa16bit;
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@ -1444,9 +1453,13 @@ ed_start(ifp)
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* may cause a call-back to ed_start)
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* XXX - the call-back to 'start' is a bug, IMHO.
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*/
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case ED_VENDOR_WD_SMC:
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case ED_VENDOR_WD_SMC: {
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto | ED_WD_LAAR_M16EN));
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
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break;
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}
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}
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}
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@ -1465,9 +1478,12 @@ ed_start(ifp)
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outb(sc->asic_addr + ED_3COM_GACFR,
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ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
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break;
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case ED_VENDOR_WD_SMC:
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case ED_VENDOR_WD_SMC: {
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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break;
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}
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}
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}
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} else {
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@ -1823,6 +1839,9 @@ edintr(unit)
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto |=
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ED_WD_LAAR_M16EN));
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR,
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ED_WD_MSR_MENB);
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}
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ed_rint (unit);
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@ -1834,6 +1853,8 @@ edintr(unit)
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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}
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}
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@ -1,7 +1,7 @@
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/*
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* National Semiconductor DS8390 NIC register definitions
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*
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* $Id: if_edreg.h,v 1.12 1994/02/02 02:24:42 davidg Exp $
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* $Id: if_edreg.h,v 1.13 1994/02/02 14:05:58 davidg Exp $
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*
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* Modification history
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*
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@ -602,16 +602,14 @@ struct ed_ring {
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*/
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#define ED_WD_MSR 0
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#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define ED_WD_MSR_MENB 0x40 /* Memory enable */
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#define ED_WD_MSR_RST 0x80 /* Reset board */
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#ifdef TOSH_ETHER
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/* next three definitions for Toshiba */
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#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
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#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
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#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
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1 = 8 bits (R/W) */
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#endif
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#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define ED_WD_MSR_MENB 0x40 /* Memory enable */
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#define ED_WD_MSR_RST 0x80 /* Reset board */
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/*
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* Interface Configuration Register (ICR)
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@ -657,7 +655,7 @@ struct ed_ring {
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#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
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/*
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* The three bit of the encoded IRQ are decoded as follows:
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* The three bits of the encoded IRQ are decoded as follows:
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*
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* IR2 IR1 IR0 IRQ
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* 0 0 0 2/9
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@ -686,6 +684,49 @@ struct ed_ring {
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/* i/o base offset to station address/card-ID PROM */
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#define ED_WD_PROM 8
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/*
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* 83C790 specific registers
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*/
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/*
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* Hardware Support Register (HWR) ('790)
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*/
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#define ED_WD790_HWR 4
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#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */
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#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */
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#define ED_WD790_HWR_SWH 0x80 /* switch register set */
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/*
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* ICR790 Interrupt Control Register for the 83C790
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*/
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#define ED_WD790_ICR 6
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#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
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/*
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* General Control Register (GCR)
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* Enabled with SWH bit=1 in HWR register
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*/
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#define ED_WD790_GCR 0x0d
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#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
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#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
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#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
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#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
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* IR2 IR1 IR0 IRQ
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* 0 0 0 none
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* 0 0 1 9
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* 0 1 0 3
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* 0 1 1 5
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* 1 0 0 7
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* 1 0 1 10
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* 1 1 0 11
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* 1 1 1 15
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*/
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/* i/o base offset to CARD ID */
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#define ED_WD_CARD_ID ED_WD_PROM+6
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@ -16,7 +16,7 @@
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*/
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/*
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* $Id: if_ed.c,v 1.34 1994/03/01 12:23:33 davidg Exp $
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* $Id: if_ed.c,v 1.35 1994/03/02 05:50:01 davidg Exp $
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*/
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#include "ed.h"
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@ -414,14 +414,15 @@ ed_probe_WD80x3(isa_dev)
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* Assemble together the encoded interrupt number.
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*/
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iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
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((inb(isa_dev->id_iobase + ED_WD_IRR) &
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(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
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((inb(isa_dev->id_iobase + ED_WD_IRR) &
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(ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
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/*
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* Translate it using translation table, and check for correctness.
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*/
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if (ed_intr_mask[iptr] != isa_dev->id_irq) {
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printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1,
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ffs(ed_intr_mask[iptr]) - 1);
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return(0);
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}
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/*
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@ -431,17 +432,25 @@ ed_probe_WD80x3(isa_dev)
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inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
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}
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if (sc->is790) {
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outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
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iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
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((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
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outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
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outb(isa_dev->id_iobase + ED_WD790_HWR,
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inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
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iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
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(inb(isa_dev->id_iobase + ED_WD790_GCR) &
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(ED_WD790_GCR_IR1|ED_WD790_GCR_IR0)) >> 2);
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outb(isa_dev->id_iobase + ED_WD790_HWR,
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inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
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if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
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printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
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isa_dev->id_unit, ffs(isa_dev->id_irq) - 1,
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ffs(ed_790_intr_mask[iptr]) - 1, iptr);
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return 0;
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}
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outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
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/*
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* Enable interrupts.
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*/
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outb(isa_dev->id_iobase + ED_WD790_ICR,
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inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
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}
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sc->isa16bit = isa16bit;
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@ -1444,9 +1453,13 @@ ed_start(ifp)
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* may cause a call-back to ed_start)
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* XXX - the call-back to 'start' is a bug, IMHO.
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*/
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case ED_VENDOR_WD_SMC:
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case ED_VENDOR_WD_SMC: {
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto | ED_WD_LAAR_M16EN));
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
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break;
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}
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}
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}
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@ -1465,9 +1478,12 @@ ed_start(ifp)
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outb(sc->asic_addr + ED_3COM_GACFR,
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ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
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break;
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case ED_VENDOR_WD_SMC:
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case ED_VENDOR_WD_SMC: {
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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break;
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}
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}
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}
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} else {
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@ -1823,6 +1839,9 @@ edintr(unit)
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto |=
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ED_WD_LAAR_M16EN));
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR,
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ED_WD_MSR_MENB);
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}
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ed_rint (unit);
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@ -1834,6 +1853,8 @@ edintr(unit)
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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if (sc->is790)
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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}
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}
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@ -1,7 +1,7 @@
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/*
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* National Semiconductor DS8390 NIC register definitions
|
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*
|
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* $Id: if_edreg.h,v 1.12 1994/02/02 02:24:42 davidg Exp $
|
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* $Id: if_edreg.h,v 1.13 1994/02/02 14:05:58 davidg Exp $
|
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*
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* Modification history
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||||
*
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@ -602,16 +602,14 @@ struct ed_ring {
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*/
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#define ED_WD_MSR 0
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#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define ED_WD_MSR_MENB 0x40 /* Memory enable */
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#define ED_WD_MSR_RST 0x80 /* Reset board */
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#ifdef TOSH_ETHER
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/* next three definitions for Toshiba */
|
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#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
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#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
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#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
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1 = 8 bits (R/W) */
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#endif
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#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define ED_WD_MSR_MENB 0x40 /* Memory enable */
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#define ED_WD_MSR_RST 0x80 /* Reset board */
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/*
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* Interface Configuration Register (ICR)
|
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@ -657,7 +655,7 @@ struct ed_ring {
|
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#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
|
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|
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/*
|
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* The three bit of the encoded IRQ are decoded as follows:
|
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* The three bits of the encoded IRQ are decoded as follows:
|
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*
|
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* IR2 IR1 IR0 IRQ
|
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* 0 0 0 2/9
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@ -686,6 +684,49 @@ struct ed_ring {
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/* i/o base offset to station address/card-ID PROM */
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#define ED_WD_PROM 8
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|
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/*
|
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* 83C790 specific registers
|
||||
*/
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/*
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* Hardware Support Register (HWR) ('790)
|
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*/
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#define ED_WD790_HWR 4
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#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */
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#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */
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#define ED_WD790_HWR_SWH 0x80 /* switch register set */
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/*
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* ICR790 Interrupt Control Register for the 83C790
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*/
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#define ED_WD790_ICR 6
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#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
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/*
|
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* General Control Register (GCR)
|
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* Enabled with SWH bit=1 in HWR register
|
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*/
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#define ED_WD790_GCR 0x0d
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#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
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#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
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#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
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#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
|
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* IR2 IR1 IR0 IRQ
|
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* 0 0 0 none
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* 0 0 1 9
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* 0 1 0 3
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* 0 1 1 5
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* 1 0 0 7
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* 1 0 1 10
|
||||
* 1 1 0 11
|
||||
* 1 1 1 15
|
||||
*/
|
||||
|
||||
/* i/o base offset to CARD ID */
|
||||
#define ED_WD_CARD_ID ED_WD_PROM+6
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user